Internal - Memory PDF William Stalling

+
William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 5
Internal Memory
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Control Control
Select Data in Select Sense

Cell Cell
(a) Write (b) Read
Figure 5.1 Memory Cell Operation

Memory Type Category Erasure Write Volatility
Mechanism
Random-access Read-write Electrically,
Electrically Volatile
memory (RAM) memory byte-level
Read-only Masks
memory (ROM) Read-only
Not possible
Programmable memory
ROM (PROM)
Erasable PROM UV light, chip-
(EPROM) level Nonvolatile
Electrically Electrically
Read-mostly Electrically,
Erasable PROM memory byte-level
(EEPROM)
Electrically,
Flash memory
block-level
Table 5.1
Semiconductor Memory Types

+
Dynamic RAM (DRAM)
◼ RAM technology is divided into two technologies:

◼ Dynamic RAM (DRAM)
◼ Static RAM (SRAM)
◼ DRAM
◼ Made with cells that store data as charge on capacitors
◼ Presence or absence of charge in a capacitor is interpreted as

a binary 1 or 0
◼ Requires periodic charge refreshing to maintain data storage
◼ The term dynamic refers to tendency of the stored charge to

leak away, even with power continuously applied

+ DRAM and Refresh Cycles
DRAM vs. SRAM Memory Cell Complexity

Word line Word line Vcc
Pass
transistor
Capacitor
Compl.
Bit Bit
bit
line line
line
(a) DRAM cell (b) Typical SRAM cell
Single-transistor DRAM cell, which is considerably simpler than SRAM cell, leads
to dense, high-capacity DRAM memory chips.
+ DRAM Refresh Cycles and Refresh Rate
Voltage 1 Written Refreshed Refreshed Refreshed

for 1
Threshold
voltage
10s of ms
0 Stored before needing
Voltage refresh cycle Time
for 0
Fig. 17.5 Variations in the voltage across a DRAM cell capacitor after writing
a 1 and subsequent refresh operations.
+
Static RAM
(SRAM)
▪ Digital device that uses the same
logic elements used in the
processor
▪ Binary values are stored using

traditional flip-flop logic gate
configurations
▪ Will hold its data as long as power

is supplied to it

dc voltage
Address line T3 T4
T5 C1 C2 T6
Transistor
Storage
capacitor
T1 T2
Bit line Ground

Ground
B
Bit line Address Bit line

B line B
(a) Dynamic RAM (DRAM) cell (b) Static RAM (SRAM) cell
Figure 5.2 Typical Memory Cell Structures

SRAM versus DRAM
SRAM
◼ Both volatile
◼ Power must be continuously supplied to the
memory to preserve the bit values
◼ Dynamic cell
◼ Simpler to build, smaller
◼ More dense (smaller cells = more cells per unit
area)
DRAM
◼ Less expensive
◼ Requires the supporting refresh circuitry
◼ Tend to be favored for large memory
+ requirements
◼ Used for main memory
◼ Static
◼ Faster
◼ Used for cache memory (both on and off chip)
+
Read Only Memory (ROM)
◼ Contains a permanent pattern of data that cannot be
changed or added to
◼ No power source is required to maintain the bit values in

memory
◼ Data or program is permanently in main memory and never

needs to be loaded from a secondary storage device
◼ Data is actually wired into the chip as part of the fabrication

process
◼ Disadvantages of this:
◼ No room for error, if one bit is wrong the whole batch of ROMs
must be thrown out
◼ Data insertion step includes a relatively large fixed cost

+ Nonvolatile Memory
S u p p ly vo l t a g e
ROM
Word contents
PROM
EPROM 1010
1001
Word
lines
0010
1101
B i t li nes
Read-only memory organization, with the fixed contents
shown on the right.
+
Programmable ROM (PROM)
◼ Less expensive alternative
◼ Nonvolatile and may be written into only once
◼ Writing process is performed electrically and may be

performed by supplier or customer at a time later than the
original chip fabrication
◼ Special equipment is required for the writing process
◼ Provides flexibility and convenience
◼ Attractive for high volume production runs

Read-Mostly Memory
Flash
EPROM EEPROM
Memory
Electrically erasable
programmable read-only Intermediate between
Erasable programmable
memory EPROM and EEPROM in
read-only memory
both cost and functionality
Can be written into at any

time without erasing prior
contents
Uses an electrical erasing
Erasure process can be
technology, does not
performed repeatedly
Combines the advantage of provide byte-level erasure
non-volatility with the
flexibility of being
updatable in place
More expensive than Microchip is organized so
PROM but it has the that a section of memory
advantage of the multiple More expensive than cells are erased in a single
update capability EPROM action or “flash”

+
Error Correction
◼ Hard Failure
◼ Permanent physical defect
◼ Memory cell or cells affected cannot reliably store data but
become stuck at 0 or 1 or switch erratically between 0 and 1
◼ Can be caused by:
◼ Harsh environmental abuse
◼ Manufacturing defects
◼ Wear
◼ Soft Error
◼ Random, non-destructive event that alters the contents of one or
more memory cells
◼ No permanent damage to memory
◼ Can be caused by:
◼ Power supply problems
◼ Alpha particles

Error Signal
Data Out M
Corrector
Data In M M K
f
Memory Compare
K K
f
Figure 5.7 Error-Correcting Code Function

(a) A B (b) A B
1 1 1 0
1 1
1 0 1 0
0
C C
(c) A B (d) A B
1 1 0 1 1 0
1 1
0 0 0 0
0 0
C
C
Figure 5.8 Hamming Error-Correcting Code

Bit Position 7 6 5 4 3 2 1
Position 111 110 101 100 011 010 001

Number
Data Bit D4 D3 D2 D1
Check Bit C4 C2 C1

Bit
12 11 10 9 8 7 6 5 4 3 2 1
Position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Data
D8 D7 D6 D5 D4 D3 D2 D1
Bit
Check
C8 C4 C2 C1
Bit
Figure 5.9 Layout of Data Bits and Check Bits

Bit
12 11 10 9 8 7 6 5 4 3 2 1
position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
number
Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check
C8 C4 C2 C1
bit
Word
stored 0 0 1 1 0 1 0 0 1 1 1 1
as
Word
fetched 0 0 1 1 0 1 1 0 1 1 1 1
as
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Check
0 0 0 1
Bit
Figure 5.10 Check Bit Calculation

C1 = D1 + D2 + D4 + D5 + D7
C2 = D1 + D3 + D4 + D6 + D7
C4 = D2 + D3 + D4 + D8
C8 = D5 + D6 + D7 + D8

For convenience, we would like to generate a 4-bit syndrome
for an 8-bit data word with the following characteristics:
• If the syndrome contains all 0s, no error has been detected.
• If the syndrome contains one and only one bit set to 1, then
an error has occurred in one of the 4 check bits. No correction
is needed.
• If the syndrome contains more than one bit set to 1, then the
numerical value of the syndrome indicates the position of the
data bit in error. This data bit is inverted for correction.

Bit 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1
Position
1 0 9 8 7 6 5 4 3 2 1 0
Position 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Number
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
Data Bit D D D D D D D D D D D D D D D D
1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1
6 5 4 3 2 1 0
Check C C C C C
Bit
1 8 4 2 1
6

C1 = D1 + D2 + D4 + D5 + D7 + D9 + D11 + D12 + D14 + D16
C2 = D1 + D3 + D4 + D6 + D7 + D10 + D11 + D13 + D14
C4 = D2 + D3 + D4 + D8 + D9 + D10 + D11 + D15 + D16
C8 = D5 + D6 + D7 + D8 + D9 + D10 + D11
C16 = D12 + D13 + D14 + D15 + D16

(a) (b) (c)
0 0 0 1 1 0 1
1 1 0
1 0 1 0 1 0
0 0
1 1
(d) (e) (f)
1 0 1 1 0 1 1 0 1
0 0 0
1 0 1 1 1 1
0 0 0
1 1 1
Figure 5.11 Hamming SEC-DED Code

Single-Error Correction Single-Error Correction/
Double-Error Detection
Data Bits Check Bits % Increase Check Bits % Increase
8 4 50 5 62.5
16 5 31.25 6 37.5
32 6 18.75 7 21.875
64 7 10.94 8 12.5
128 8 6.25 9 7.03
256 9 3.52 10 3.91
Table 5.2
Increase in Word Length with Error Correction

SDRAM
Advanced DRAM Organization
◼ One of the most critical system bottlenecks

DDR-DRAM
when using high-performance processors is
the interface to main internal memory
◼ The traditional DRAM chip is constrained

both by its internal architecture and by its
interface to the processor’s memory bus RDRAM
◼ A number of enhancements to the basic
DRAM architecture have been explored
+
◼ The schemes that currently dominate the
market are SDRAM and DDR-DRAM

Capacity and Performance:
The two most important characteristics of

memory
Three performance parameters are used:
Memory cycle time

Access time (latency) Transfer rate
•Access time plus any additional
•For random-access memory it is time required before second •The rate at which data can be
the time it takes to perform a access can commence transferred into or out of a
read or write operation •Additional time may be required memory unit
•For non-random-access memory for transients to die out on signal •For random-access memory it is
it is the time it takes to position lines or to regenerate data if they equal to 1/(cycle time)
the read-write mechanism at the are read destructively
desired location •Concerned with the system bus,
not the processor

Synchronous DRAM (SDRAM)
One of the most widely used forms of DRAM
Exchanges data with the processor

synchronized to an external clock signal and
running at the full speed of the
processor/memory bus without imposing wait
states
With synchronous access the DRAM moves data in

and out under control of the system clock
• The processor or other master issues the instruction
and address information which is latched by the DRAM
• The DRAM then responds after a set number of clock
cycles
• Meanwhile the master can safely do other tasks while
the SDRAM is processing

+ DRAM Packaging
24-pin dual in-line package (DIP)
Vss D4 D3 CAS OE A9 A8 A7 A6 A5 A4 Vss Legend:

24 23 22 21 20 19 18 17 16 15 14 13 Ai Address bit i
CAS Column address strobe
Dj Data bit j
NC No connection
OE Output enable
1 2 3 4 5 6 7 8 9 10 11 12 RAS Row address strobe
WE Write enable
Vcc D1 D2 WE RAS NC A10 A0 A1 A2 A3 Vcc
Typical DRAM package housing a 16M  4 memory.

A0 to A12 Address inputs
BA0, BA1 Bank address lines
CLK Clock input Table 5.3
CKE Clock enable
Chip select
SDRAM
CS
Pin
RAS Row address strobe Assignment
CAS Column address strobe s
WE Write enable
DQ0 to DQ15 Data input/output
DQM Data mask

The SDRAM employs a burst mode to
eliminate the address setup time and row and
column line pre-charge time after the first
access. In burst mode, a series of data bits can
be clocked out rapidly after the first bit has
been accessed. This mode is useful when all the
bits to be accessed are in sequence and in the
same row of the array as the initial access. In
addition, the SDRAM has a multiple-bank
internal architecture that improves
opportunities for on-chip parallelism.

The mode register and associated control logic is
another key feature differentiating SDRAMs from
conventional DRAMs. It provides a mechanism to
customize the SDRAM to suit specific system needs.
The mode register specifies the burst length, which
is the number of separate units of data
synchronously fed
onto the bus. The register also allows the
programmer to adjust the latency between receipt
of a read request and the beginning of data transfer.
The SDRAM performs best when it is transferring

large blocks of data serially, such as for applications
like word processing, spreadsheets, and multimedia
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3
Figure 5.13 SDRAM Read Timing (Burst Length = 4, CAS latency = 2)

In this case, the burst length is 4 and the
latency is 2. The burst read command is
initiated by having CS and CAS low while
holding RAS and WE high at the rising edge
of the clock. The address inputs determine the
starting column address for the burst, and the
mode register sets the type of burst (sequential
or interleave) and the burst length (1, 2, 4, 8,
full page). The delay from the start of the
command to when the data from the first cell
appears on the outputs is equal to the value of
the CAS latency that is set in the mode
register.
+
Double Data Rate SDRAM
(DDR SDRAM)
◼ Developed by the JEDEC Solid State Technology

Association (Electronic Industries Alliance’s
semiconductor-engineering-standardization body)
◼ Numerous companies make DDR chips, which are

widely used in desktop computers and servers
◼ DDR achieves higher data rates in three ways:

◼ First, the data transfer is synchronized to both the rising and
falling edge of the clock, rather than just the rising edge
◼ Second, DDR uses higher clock rate on the bus to increase the
transfer rate
◼ Third, a buffering scheme is used

DDR1 DDR2 DDR3 DDR4
Prefetch buffer 2 4 8 8
(bits)
Voltage level (V) 2.5 1.8 1.5 1.2
Front side bus 200—400 400—1066 800—2133 2133—4266
data rates (Mbps)
Table 5.4
DDR Characteristics

The prefetch buffer is a memory cache
located on the SDRAM chip. It enables
the SDRAM chip to preposition bits to be
placed on the data bus as rapidly as
possible. The DDR I/O bus uses the same
clock rate as the memory chip, but
because it can handle two bits per cycle, it
achieves a data rate that is double the
clock rate. The 2-bit prefetch buffer
enables the SDRAM chip to keep up with
the I/O bus.

The prefetch buffer size determines how many words of data are
fetched (across multiple SDRAM chips) every time a column
command is performed with DDR memories. Because the core of
the DRAM is much slower than the interface, the difference is
bridged by accessing information in parallel and then serializing it
out the interface through a multiplexor (MUX). Thus, DDR
prefetches two words, which means that every time a read or a
write operation is performed, it is performed on two words of data,
and bursts out of, or into, the SDRAM over one clock cycles on
both clock edges for a total of two consecutive operations. As a
result, the DDR I/O interface is twice as fast as the SDRAM core.

For DDR2, a 4-bit buffer is used,
allowing for words to be transferred in
parallel, increasing the effective data rate
by a factor of 4. For DDR3, an 8-bit
buffer is used and a factor of 8 speedup
is achieved (Figure 5.14).

+
Flash Memory
◼ Used both for internal memory and external memory applications
◼ First introduced in the mid-1980’s
◼ Is intermediate between EPROM and EEPROM in both cost and

functionality
◼ Uses an electrical erasing technology like EEPROM
◼ It is possible to erase just blocks of memory rather than an entire

chip
◼ Gets its name because the microchip is organized so that a section

of memory cells are erased in a single action
◼ Does not provide byte-level erasure
◼ Uses only one transistor per bit so it achieves the high density of
EPROM

Control Gate
N+ N+
Drain Source
P-substrate
(a) Transistor structure
+ + + + + +
Control Gate Control Gate
Floating Gate – – – – – –
N+ N+ N+ N+
Drain Source Drain Source
P-substrate P-substrate
(b) Flash memory cell in one state (c) Flash memory cell in zero state
Figure 5.15 Flash Memory Operation

+Flash Memory
S o u r c e l i n es
Control gate
Floating gate
Source
Word
lines
n−
p subs-
trate
n+
B i t li nes Drain
EEPROM or Flash memory organization. Each memory cell is

built of a floating-gate MOS transistor.

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+

Select Data in Select Sense

(a) Write (b) Read

Figure 5.1 Memory Cell Operation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ RAM technology is divided into two technologies:

◼ Made with cells that store data as charge on capacitors

◼ Presence or absence of charge in a capacitor is interpreted as

◼ Requires periodic charge refreshing to maintain data storage

◼ The term dynamic refers to tendency of the stored charge to

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

DRAM vs. SRAM Memory Cell Complexity

Voltage 1 Written Refreshed Refreshed Refreshed

▪ Binary values are stored using

▪ Will hold its data as long as power

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Bit line Ground

Bit line Address Bit line

Figure 5.2 Typical Memory Cell Structures

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ No power source is required to maintain the bit values in

◼ Data or program is permanently in main memory and never

◼ Data is actually wired into the chip as part of the fabrication

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ Less expensive alternative

◼ Nonvolatile and may be written into only once

◼ Writing process is performed electrically and may be

◼ Special equipment is required for the writing process

◼ Provides flexibility and convenience

◼ Attractive for high volume production runs

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Can be written into at any

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.7 Error-Correcting Code Function

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.8 Hamming Error-Correcting Code

Position 111 110 101 100 011 010 001

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.9 Layout of Data Bits and Check Bits

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.10 Check Bit Calculation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

• If the syndrome contains all 0s, no error has been detected.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

C2 = D1 + D3 + D4 + D6 + D7 + D10 + D11 + D13 + D14

C4 = D2 + D3 + D4 + D8 + D9 + D10 + D11 + D15 + D16

C16 = D12 + D13 + D14 + D15 + D16

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.11 Hamming SEC-DED Code

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

◼ One of the most critical system bottlenecks

◼ The traditional DRAM chip is constrained

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

The two most important characteristics of

Three performance parameters are used:

Memory cycle time

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Exchanges data with the processor

With synchronous access the DRAM moves data in

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.