Abstract titled:

Ultra Low-Power and Reconfigurable Architectures.

presented to express the research area/interest in the interaction with members of DRC, on 19
July, 2017, for admission to Integrated Ph.D. programme in the Department of Electronics and
Instrumentation Technology, University of Kashmir.

by
Mujtaba Yousuf Kathjoo
Form No. 1661616/Roll No. 260006
 Motivation : My Interest in the field of Integrated Circuit Design

Integrated circuit designing and manufacturing has developed to an extent, where in it is governed by
set of laws and constraints.
 Moore’s law
 Bell’s Law
 Koomey’s and Gene’s laws

Contraints and Trends :

 inexpensive, small, and extremely low power
 Megatrends, demanding more pervasive and continuous sensing, as well as sense making and
transfer of physical data
 Designing is an entity seen at System level, sub-system level, circuit level
and device level

 Each level defines some promising parameters with regard to development

and improvement.

 Ultra-low voltage digital circuit design is an active research area, especially

for portable applications such as wearable electronics, intelligent remote
sensors, implantable medical devices, and energy-harvesting systems.

 Ultra-low voltage digital circuit design involves process, architecture, and

circuit-level techniques
 Architectural Designing

 Architectures for Arithmetic and Logic circuits

 I/O subsystems including Analog to digital converters and Digital to analog
Converters, Non-Volatile memory design,
 Power managed architectures
 Hardware security implemented architecture to restrain the power loss in
software based processing - as is much desired in the highly evolving field
of Internet of Things[6][7][8][9] and
 Low-Power communicating wireless architectures
 A lot of work has been carried on and is still desired for the design of ultra-low power
digital circuits. It highly involves the near-threshold digital design techniques and is major
contribution area in this field[12].

 Security at hardware level in low-power designs, now a days is achieved by employing non-
linear dynamical systems for designing physical layer of the communication systems. The
synchronization of these dynamical systems determines the security at the physical layer of
these systems

 The current research trend also involves employment of reconfigurable logic designs for
architectural versatility and power efficiency [13][14]. Reconfigurablity denotes that the
functioning/capability of the same design can change with the change in some parameter of
the design. This allows us in having structures capable of performing many tasks using a
single design, thus helping in providing better space and power efficiency.
References:
1. Massimo Alioto (Editor), Enabling the Internet of Things - From Integrated Circuits to Integrated Systems, Springer, Feb 2017
2. M. Alioto, Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans. Circ. Syst. 59(1), 3–29 (2012)
3. Pierre-Emmanuel Gaillardon, Edith Beigne, Suzanne Lesecq, Giovanni De Micheli, A Survey on Low-Power Techniques with Emerging
Technologies: From Devices to Systems, ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Advances
in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies; Volume 12 Issue 2, August 2015 Article No. 12
4. Sharma Anjali, Sohal Harsh, Considerations for Ultra-Low-Power VLSI Design—A Survey, Journal of Nanoelectronics and Optoelectronics,
Volume 12, Number 1, January 2017, pp. 1-21(21)
5. M. Lueders, B. Eversmann, J. Gerber, K. Huber, R. Kuhn, M. Zwerg, D. Schmitt-Landsiedel, R. Brederlow, Architectural and circuit design
techniques for power management of ultra-low-power mcu systems. IEEE Trans. VLSI Syst. 22(11), 2287–2296 (2014)
6. J. Bhadra, S. Ray, Security challenges in mobile and IoT systems, in Proceedings of the SOCC 2016, Seattle, USA (2016)
7. M. Alioto, A. Alvarez, Physically Unclonable Function database (2016), http://www.green-ic.org/pufdb
8. C. Helfmeier, C. Boit, D. Nedospasov, J.-P. Seifert, Cloning Physically Unclonable Functions, in Proceeding of the IEEE International
Symposium on Hardware-Oriented Security and Trust (HOST) (2013), pp. 1–6.
9. NXP Cryptographic Acceleration Technology,
http://www.nxp.com/products/identification-and-security/network-security-technology/cryptographic-acceleration-technology:NETWORK
_SECURITY_CRYPTOG
10. W.-H. Yu, H. Yi, P.-I. Mak, J. Yin, R.P. Martins, A 0.18 V 382 μW bluetooth low-energy (BLE) receiver with 1.33 nW sleep power for energy-
harvesting applications in 28 nm CMOS, in IEEE ISSCC Dig., Tech Papers, 2017, to appear.
11. Mohammad Rafiq Dar, Nasir Ali Kant and Farooq Ahmad Khanday, Electronic Implementation of Fractional-Order Newton–Leipnik Chaotic
System with Application to Communication, Journal of Computational and Nonlinear Dynamics 12(5), 054502, May 15, 2017.
12. L. Lin, S. Jain, M. Alioto, Reconfigurable clock networks for random skew mitigation from sub-threshold to nominal voltage, in IEEE ISSCC
Dig. Tech. Papers (Feb. 2017)
13. M. Khayatzadeh, M. Saligane, J. Wang, M. Alioto, D. Blaauw, D. Sylvester, A reconfigurable dual port memory with error detection and
correction in 28 nm FDSOI, in IEEE ISSCC Dig. Tech. Papers (Feb. 2016), pp. 310–311
14. Sohrab Behnia, Zahra Pazhotan, N. Ezzati, Afshin Akhshani, Reconfigurable chaotic logic gates based on novel chaotic circuit, Elsevier 2014
Thank You