Module 12345

ELE546T
Embedded Systems
Dr. Rohini. P
Department of ECE,
IIITDM Kancheepuram
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Embedded systems
Computers designed for specific purpose

Internet of Things (IoT)
Internet connected embedded systems

Embedded System
 Embedded Systems are everywhere
 Ubiquitous, invisible
Medical
Automotive
 Hidden (computer inside)
 Dedicated purpose
Communications
Military
 Around 5 Billion in today’s world
 Components inside a Embedded system

 Computer – x86 – standard in PC
Comsumer Industrial
 ARM
 A series – Cell phones
 M series – Microcontroller
 R series – Real time

Considerations
Ability to test/verify
Ability to make profit
Lower power consumption
Small size
Time – Correct answer at correct time

The correctness of the system depends on not only on the logical result of the computation but also
on the time at which the results are produced
A correct value at a wrong time is a fault.
5
Embedded System
 Microprocessor
Embedded system  Intel: 4004, ..8080,.. x86

Microcontroller LM3S or TM4C Electrical,
mechanical,  ARM, DEC, SPARC, MIPS, PowerPC,,…
Processor chemical,
I/O Ports or
RAM optical  Microcontroller
devices
ROM
ADC
DAC Analog
signals  Processor + Memory + I/O Ports
Bus
(Interfaces)

Microcontroller
 Memory
 Non-Volatile
ROM Memory Type Category Erasure Write Volatility
Mechanism
EPROM, EEPROM, Flash
Random-access Read-write Electrically,
 Volatile memory (RAM) memory byte-level
Electrically Volatile
RAM (DRAM, SRAM) Read-only

memory (ROM)
Masks
Read-only
Not possible
memory
 Interfaces Programmable
ROM (PROM)
 H/W: Ports Erasable PROM UV light, chip-
Nonvolatile
 S/W: Device Driver (EPROM) level
Electrically
Electrically
 Parallel, Serial, Analog, Time Erasable PROM
Read-mostly
memory
Electrically,
byte-level
(EEPROM)
 I/O Flash memory

Electrically,
block-level
 Memory-mapped vs. I/O-
instructions (I/O-mapped)

Von Neumann Architecture

Harvard Architecture

Microprocessor
Components include:
 Entire CPU fabricated on a chip
 Consists of
 Registers
 ALU
 Control unit
 System bus – for interfacing

Micro computer
Computer system – built using microprocessor
Use external memory and I/O – not inbuilt
Complex and expensive for very small and low cost embedded system application

Microcontroller
Microcomputer- onto a single chip
Inexpensive, small and low power – for use in embedded system design
Operates on data that are fed through input ports, controlled by the software stored in
on-chip memory

Microcontroller
Fast and Effective

Low cost/ Low power
Compatibility

Difference between microcontroller and PC
When PC executes a program- primarily loaded from disk/SSD to an allocated section
of memory
Program is loaded part by part to conserve memory space
There is an operating system that handles low level operations
Microcontroller – no disk to read from

On chip ROM stores the program
Size of the ROM limits the maximum size of program
No operating system – ROM must also include low level routines

History of ARM series Microcontrollers
Architectural ideas developed in 1983 by Acorn computers
The first commercial RISC implementation
The company founded in 1990

Advanced RISC Machine (ARM)
Initially owned by Acorn, Apple and VLSI

ARM Evolution

Why ARM ?
Chips are high-speed processors that are known for their small die size and low power requirements
Probably the most widely used embedded processor architecture and indeed the most widely used
processor architecture of any kind in the world
Some Application examples:

ARM7: iPod
ARM9: Sony Ericsson
ARM11: Apple iPhone, Nokia N93, N100
Mainly used in battery operated devices

Due to low power consumption and reasonably good performance

ARM
Simple RISC based architecture with powerful design
A whole family of ARM exist

Share similar design principles and a common instruction set
Design Philosophy:
Small processor for lower power consumption (for embedded system application)
High code density for limited memory and physical size restrictions
Can interface with slow and low cost memory systems
Reduced die size for processor to accommodate more peripherals

ARM is based on RISC architecture
RISC – supports simple but powerful instructions – execute in a single cycle
Major design features of RISC Architecture:

Instruction: reduced set/ single cycle/ fixed length
Pipeline: decode in one stage
Registers: large number of general purpose registers
Load/ Store Architecture: data processing instructions work on registers only – Load / store
instructions to transfer data from/to memory

ARM features
ARM is different from pure RISC
Variable cycle execution for certain instructions ( multiple register load/store for
higher code density)
In-line barrel shifter results in more complex instruction
Thumb 16 bit instruction set (results in improvement in code density by about 30%)
Conditional execution

Popular ARM architecture
ARM 7
3 Pipeline stages (fetch/decode/execute)
High code density and low power consumption
Most widely used for low end systems
ARM9
Compatible with ARM 7
5 stage pipeline (Fetch/decode/execute/memory/write)
Separate instruction and data cache
ARM10
6 stage pipeline (Fetch/issue/decode/execute/memory/write)

Pipelining
Mechanism for overlapped execution of input set - partitioning computation into k-sub computations.
Very nominal increase in the cost of implementation
Significant speedup ( ideally k-folds)
ARM 7
ARM 9

Pipelining in ARM

With Complex instructions

Processor Design
Instruction set Architecture
Instructions supported
Registers (GPRs, special)
Data Types (char, integer, float)
Addressing mode
Memory Access

Registers

Memory

Memory map of TM4C123

Assembly Language
Label field is optional and starts in the first column - used to identify the position in memory of
the current instruction
Opcode field specifies the processor command to execute
Operand field specifies where to find the data to execute the instruction
Comment field is also optional and is ignored by the assembler, but it allows you to describe the
software making it easier to understand
Label Opcode Operands Comment

Func MOV R0, #100 ; this sets R0 to 100
BX LR ; this is a function return

List of Symbols
Ra Rd Rm Rn Rt and Rt2 represent registers
{Rd,} represents an optional destination register
#imm16 represents a 16-bit constant, 0 to 65535
{cond} represents an optional logical condition as listed in Table 2.10
{type} encloses an optional data type
Rm {, shift} specifies an optional shift on Rm
Rn {, #offset} specifies an optional offset to Rn

Conditions – {cond}
Suffix Flags Meaning
EQ Z=1 Equal
NE Z=0 Not equal
CS or HS C=1 Higher or same, unsigned ≥
CC or LO C=0 Lower, unsigned <
MI N=1 Negative
PL N=0 Positive or zero
VS V=1 Overflow
VC V=0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N=V Greater than or equal, signed ≥
LT N≠V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N ≠ V Less than or equal, signed ≤

Addressing Modes and Operands
Immediate addressing
MOV R0,#100 ; R0=100, immediate addressing

Indexed addressing
Data is in memory and a register will contain a pointer to the data
LDR R0,[R1] ; R0= value pointed to by R1

LDR R0,[R1,#4] ; R0= word pointed to by R1+4
LDR R0,[R1,#4]! ; first R1=R1+4, then R0= word pointed to by R1
LDR R0,[R1],#4 ; R0= word pointed to by R1, then R1=R1+4
LDR R0,[R1,R2] ; R0= word pointed to by R1+R2
LDR R0,[R1,R2, LSL #2] ; R0= word pointed to by R1+4*R2

PC relative addressing
Indexed addressing mode using the PC as the pointer
B Location ; jump to Location, using PC-relative addressing
BL Subroutine ; call Subroutine, using PC-relative addressing

Memory Access
An aligned access - word-aligned address is used for a word, a halfword-aligned
address is used for a halfword access
An unaligned word access - accessing a 32-bit object (4 bytes) but the address is not
evenly divisible by 4
Address of an aligned word access will have its bottom two LSB = 0
Address of an aligned halfword access will have its bottom bit equal to zero

Instruction set
Logical Operations
Examples:
AND{S}{cond} {Rd,} Rn, ;Rd=Rn&op2
ORR{S}{cond} {Rd,} Rn, ;Rd=Rn|op2
EOR{S}{cond} {Rd,} Rn, ;Rd=Rn^op2
BIC{S}{cond} {Rd,} Rn, ;Rd=Rn&(~op2)
ORN{S}{cond} {Rd,} Rn, ;Rd=Rn|(~op2)

Instruction set
 Shift Operations
Examples:
LSR{S}{cond} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned)
LSR{S}{cond} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned)
ASR{S}{cond} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed)
ASR{S}{cond} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed)
LSL{S}{cond} Rd, Rm, Rs ; shift left Rd=Rm< <Rs
LSL{S}{cond} Rd, Rm, #n ; shift left Rd=Rm<<n

Instruction set
Arithmetic Operations
ADD{S}{cond} {Rd,} Rn, ;Rd = Rn + op2

ADD{S}{cond} {Rd,} Rn, #im12 ;Rd = Rn + im12
SUB{S}{cond} {Rd,} Rn, ;Rd = Rn - op2
SUB{S}{cond} {Rd,} Rn, #im12 ;Rd = Rn - im12
RSB{S}{cond} {Rd,} Rn, ;Rd = op2 - Rn
RSB{S}{cond} {Rd,} Rn, #im12 ;Rd = im12 - Rn
CMP{cond} Rn, ;Rn - op2
CMN{cond} Rn, ;Rn - (-op2)

Instruction set
Memory Access Instructions
mechanisms to read from and write to memory

LDR{type}{cond} Rd, [Rn] ; load memory at [Rn] to Rd
STR{type}{cond} Rt, [Rn] ; store Rt to memory at [Rn]
LDR{type}{cond} Rd, [Rn, #n] ; load memory at [Rn+n] to Rd
STR{type}{cond} Rt, [Rn, #n] ; store Rt to memory [Rn+n]
LDR{type}{cond} Rd, [Rn,Rm,LSL #n] ; load memory at [Rn+Rm<<n] to Rd
STR{type}{cond} Rt, [Rn,Rm,LSL #n] ; store Rt to memory [Rn+Rm<<n]
Example:
Input LDR R5,=0x400043FC ;R5=0x400043FC, R5 points to PortA
LDR R6,[R5] ;Input from PortA into R
I/O ports
GPIO Ports Pins

PORTA PA0 – PA7
PORTB PB0- PB7
PORTC PC4 – PC7
PORTD PD0 – PD7
PORTE PE0 – PE5
PORTF PF0 - PF7

I/O ports
UART Universal asynchronous receiver/transmitter
SSI Synchronous serial interface
I2C Inter-integrated circuit
Timer Periodic interrupts, input capture, and output compare
PWM Pulse width modulation
ADC Analog to digital converter, measure analog signals
Analog Comparator Compare two analog signals
QEI Quadrature encoder interface
USB Universal serial bus
Ethernet High-speed network
CAN Controller area network

Cortex M4 Systick
System Bus Interface NVIC
GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
PC7 GPIO Port C GPIO Port D PD7
PC6 PD6
PC5 USB 2.0 Twelve PD5
PC4 Timers PD4
PC3/TDO/SWO PD3
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0
GPIO Port E GPIO Port F

PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0
Advanced High Performance Bus Advanced Peripheral Bus

I/O Ports and Control Registers

Read from port address
n n
Processor
n n
DQ Input/Output Port
Write to port address

Direction bits
n 1 means output
DQ 0 means input
Bus Write to port direction register
The input/output direction of a bidirectional port is specified by its direction register.

GPIO_PORTF_DIR_R , specify if corresponding pin is input or output:
0 means input
1 means output

Switches and LED

Switches and LED
Two switches and one 3-color LED
Switches are negative logic and will require activation of the internal pull-up resistors.
Set bits 0 and 4 in GPIO_PORTF_PUR_R register
LED interfaces on PF3 – PF1 are positive logic
To use the LED, make the PF3 – PF1 pins an output
To activate the red color, output a one to PF1, blue color is on PF2, green color is
controlled by PF3

Switches
Pull-down resistor - the digital signal will be low if the switch is not pressed and high if
the switch is pressed - positive logic because the asserted state is a logic high.
Pull-up resistor - the digital signal will be high if the switch is not pressed and low if the
switch is pressed - negative logic because the asserted state is a logic low.

I/O programming
Direction register (e.g., GPIO_PORTF_DIR_R) - specify which pins are input and output
Individual port pins can be general purpose I/O (GPIO) or have an alternate function.
Set bits in the alternate function register (e.g., GPIO_PORTF_AFSEL_R) to activate the alternate functions
For each I/O pin whether GPIO or alternate function - the digital circuits must be enabled by setting the bit in the
enable register (e.g., GPIO_PORTF_DEN_R)
To enable analog input – enable analog mode select register (e.g., GPIO_PORTF_AMSEL_R)
Data register (e.g., GPIO_PORTF_DATA_R) - to perform input/output on the port - read and write the data
register multiple times
Each port has a clock – enabled by writing SYSCTL_RCGCGPIO_R

I/O programming
Initialization (executed once at beginning)
1. Turn on clock in SYSCTL_RCGCGPIO_R, Wait two bus cycles – check using PRGPIO register
2. Unlock PF0 (PD7 also needs unlocking)
3. Disable Analog function – AMSEL
4. Clear bits on PCTL – to select regular digital function
5. Set DIR to 1 for output or 0 for input
6. Clear AFSEL bits to 0 to select regular I/O
7. Set DEN bits to 1 to enable data pins

Address 7 6 5 4 3 2 1 0 Name
400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R
Initialization (executed once at beginning)

1. Turn on clock in SYSCTL_RCGCGPIO_R, Wait
two bus cycles
2. Unlock PF0
3. Disable Analog function – AMSEL
4. Clear bits on PCTL – to select regular digital
function
5. Set DIR to 1 for output or 0 for input
6. Clear AFSEL bits to 0 to select regular I/O
Set PUR bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
I/O programming
#include "inc/tm4c123gh6pm.h"
void PortF_Init(void)
{
SYSCTL_RCGCGPIO_R |= 0x00000020; // 1) activate clock for Port F
while((SYSCTL_PRGPIO_R&0x00000020) == 0){};// ready?
GPIO_PORTF_LOCK_R = 0x4C4F434B; // 2) unlock GPIO Port F
GPIO_PORTF_CR_R = 0x1F; // allow changes to PF4-0
GPIO_PORTF_DIR_R = 0x0E; // 5) PF4,PF0 in, PF3-1 out
GPIO_PORTF_PUR_R = 0x11; // enable pull-up on PF0 and PF4
GPIO_PORTF_DEN_R = 0x1F; // 7) enable digital I/O on PF4-0
}
uint32_t PortF_Input(void)
{
return (GPIO_PORTF_DATA_R&0x11); // read PF4,PF0 inputs
}
void PortF_Output(uint32_t data)
{ // write PF3-PF1 outputs
GPIO_PORTF_DATA_R = data;
}
PortF_Init PortF_Input
LDR R1, =SYSCTL_RCGCGPIO_R ; 1) activate clock for Port F LDR R1, =GPIO_PORTF_DATA_R ; pointer to Port F data
LDR R0, [R1] LDR R0, [R1] ; read all of Port F
ORR R0, R0, #0x20 ; set bit 5 to turn on clock AND R0,R0,#0x11 ; just the input pins, bits 4,0
STR R0, [R1] BX LR ; return R0 with inputs
NOP
NOP ; allow time for clock to finish PortF_Output
LDR R1, =GPIO_PORTF_LOCK_R ; 2) unlock the lock register LDR R1, =GPIO_PORTF_DATA_R ; pointer to Port F data
LDR R0, =0x4C4F434B ; unlock GPIO Port F Commit Register STR R0, [R1] ; write to PF3-1
STR R0, [R1] BX LR
LDR R1, =GPIO_PORTF_CR_R ; enable commit for Port F
MOV R0, #0xFF ; 1 means allow access
STR R0, [R1]
LDR R1, =GPIO_PORTF_DIR_R ; 5) set direction register
MOV R0, #0x0E ; PF0 and PF7-4 input, PF3-1 output
STR R0, [R1]
LDR R1, =GPIO_PORTF_PUR_R ; pull-up resistors for PF4,PF0
MOV R0, #0x11 ; enable weak pull-up on PF0 and PF4
STR R0, [R1]
LDR R1, =GPIO_PORTF_DEN_R ; 7) enable Port F digital port
MOV R0, #0xFF ; 1 means enable digital I/O
STR R0, [R1]
BX LR

I/O programming
If two or more software modules access the same port, a conflict will occur if one
module changes modes or output values set by another module.
Design to write friendly software - only affects the individual pins as needed.
Friendly software does not change the other bits in a shared register.
Unfriendly software modifies more bits of a register than it needs to.
The difficulty of unfriendly code is each module will run properly when tested by itself,
but weird bugs result when two or more modules are combined.

ELE546T
Embedded Systems
Dr. Rohini. P
Department of ECE,
IIITDM Kancheepuram

Bit-specific addressing
TM4C family implements a flexible way to access port pins
Doesn’t work for all the I/O registers, just the parallel port
data registers
Allows collective access to 1 to 8 bits in a data port
Basically, if we are interested in bit b, the constant is 4*2b
Each possible bit combination has a separate address for
accessing that combination
There are 256 possible bit combinations we might be
interested in accessing, from all of them to none of them
The base addresses for the data ports can be in data manual.

Bit-specific addressing
For example, assume we are interested in Port A bits 1, 2, and 3
 The base address for Port A is 0x4000.4000, and the constants are 0x0008, 0x0010, and
0x0020
The sum of 0x4000.4000+0x0008+0x0010 +0x0020 is the address 0x4000.4038
If we read from 0x4000.4038 only bits 1, 2, and 3 will be returned
If we write to this address only bits 1, 2, and 3 will be modified

Switch Interface
Positive logic, external Positive logic, internal
+3.3V +3.3V
TM4C TM4C
in in PA4
PA5
10k PDR=1
Negative logic, external Negative logic, internal

+3.3V
TM4C +3.3V
10k
PUR=1
in in
PA7 PA6
TM4C

LED interfaces
Positive logic, low current Positive logic, high current
high +5V
Out TM4C 7405 R 10mA
R 2mA or 7406
TM4C +5V LED
LED high
Out 0.5V
PF2
Negative logic, low current Negative logic, high current

+5V
3.3 V 10mA
TM4C TM4C
R
R 7407
2mA +5V LED
LED low
Out 0.5V
Out
low

Phase-Lock-Loop
TM4C has different clock sources:
Precision Internal Oscillator (PIOSC) : 16 MHz.
Main Oscillator (MOSC) : It can use an external clock source or an external crystal.
Low-Frequency Internal Oscillator (LFIOSC) : An on-chip internal 30 kHz Oscillator used for
Deep-Sleep power-saving modes.

Phase-Lock-Loop
 Internal oscillator requires minimal power but is imprecise

 External crystal provides stable bus clock
 TM4C123 is equipped with 16.000 MHz crystal and bus clock can be set to a
maximum of 80 MHz

Registers used

To activate a microcontroller with a 16 MHz main oscillator to run at 80 MHz.
Use RCC2 because it provides for more options.
1. Set BYPASS2 (bit 11) - At this point the PLL is bypassed - no system clock divider
2. Specify the crystal frequency in the four XTAL bits using the code - OSCSRC2 bits are cleared to select the main
oscillator as the oscillator clock source
3. Clear PWRDN2 (bit 13) to activate the PLL
4. Configure and enable the clock divider using the 7-bit SYSDIV2 field. If the 7-bit SYSDIV2 is n, then the clock
will be divided by n+1 (To get 80 MHz from 400 MHz PLL - divide by 5 - place a 4 into the SYSDIV2 field)
5. Wait for the PLL to stabilize by waiting for PLLRIS (bit 6) in the SYSCTL_RIS_R to become high.
6. Connect the PLL by clearing the BYPASS2 bit.

SysTick Timer
 Timer/Counter operation
 24-bit counter decrements at bus clock
 With 80 MHz bus clock, decrements every 12.5 ns
 Counting is from n → 0
 Assume RELOAD= n n=0xFFFFFF
 CURRENT is a modulo n+1 counter
 next_value = (current_value-1) mod (n+1)

 Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1…

SysTick Timer
Address 31-24 23-17 16 15-3 2 1 0 Name
$E000E010 0 0 COUNT 0 CLK_SRC INTEN ENABLE NVIC_ST_CTRL_R
$E000E014 0 24-bit RELOAD value NVIC_ST_RELOAD_R
$E000E018 0 24-bit CURRENT value of SysTick counter NVIC_ST_CURRENT_R
Initialization (4 steps)
Step1: Clear ENABLE to stop counter
Step2: Specify the RELOAD value
Step3: Clear the counter via NVIC_ST_CURRENT_R
Step4: Set NVIC_ST_CTRL_R
CLK_SRC = 1 (bus clock is the only option)
INTEN = 0 for no interrupts
ENABLE = 0 to enable

SysTick Timer in C
#define NVIC_ST_CTRL_R(*((volatile uint32_t *)0xE000E010))
#define NVIC_ST_RELOAD_R(*((volatile uint32_t *)0xE000E014))
#define NVIC_ST_CURRENT_R(*((volatile uint32_t *)0xE000E018))
void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup
NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value
NVIC_ST_CURRENT_R = 0; // 3) any write to CURRENT clears it
NVIC_ST_CTRL_R = 0x00000005; // 4) enable SysTick with core clock
}
// The delay parameter is in units of the 80 MHz core clock(12.5 ns)
void SysTick_Wait(uint32_t delay){
NVIC_ST_RELOAD_R = delay-1; // number of counts
NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears
while((NVIC_ST_CTRL_R&0x00010000)==0){ // wait for flag
}
}
// Call this routine to wait for delay1*10ms
void SysTick_Wait10ms(uint32_t delay1){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(800000); // wait 10ms
}t
Finite State Machine (FSM)
 What is a finite state machine?

 Inputs (sensors)
 Outputs (actuators)
 Controller
 State graph ↔ State table

Finite State Machine (FSM)
 Moore FSM
 output value depends only on the current state,
 inputs affect the state transitions
 significance is being in a state
 Input: when to change state
 Output: definition of being in that state

Traffic Light FSM
PE1=0, PE0=0 means no cars exist on either road

PE1=0, PE0=1 means there are cars on the East road
PE1=1, PE0=0 means there are cars on the North road
PE1=1, PE0=1 means there are cars on both roads
• Use Moore when the output is needed to be IN the state

goN, PB5-0 = 100001 makes it green on North and red on East
waitN, PB5-0 = 100010 makes it yellow on North and red on East
goE, PB5-0 = 001100 makes it red on North and green on East
waitE, PB5-0 = 010100 makes it red on North and yellow on East

Traffic Light FSM
State \ Input 00 01 10 11
goN (100001,30) goN waitN goN waitN
waitN (100010,5) goE goE goE goE
goE (001100,30) goE goE waitE waitE
waitE (010100,5) goN goN goN goN

#define SENSOR (*((volatile uint32_t *)0x4002400C)) int main(void){ volatile uint32_t delay;
#define LIGHT (*((volatile uint32_t *)0x400050FC))
PLL_Init(); // 80 MHz,
// Linked data structure
struct State { SysTick_Init();
uint32_t Out; SYSCTL_RCGCGPIO_R |= 0x12; // B E
uint32_t Time; delay = SYSCTL_RCGCGPIO_R; // no need to unlock
uint32_t Next[4];};
GPIO_PORTE_DIR_R &= ~0x03; // inputs on PE1-0
typedef const struct State State_t;
#define goN 0 GPIO_PORTE_DEN_R |= 0x03; // enable digital on PE1-0
#define waitN 1 GPIO_PORTB_DIR_R |= 0x3F; // outputs on PB5-0
#define goE 2 GPIO_PORTB_DEN_R |= 0x3F; // enable digital on PB5-0
#define waitE 3
S = goN;
State_t FSM[4]={
{0x21,3000,{goN,waitN,goN,waitN}}, while(1){
{0x22, 500,{goE,goE,goE,goE}}, LIGHT = FSM[S].Out; // set lights
{0x0C,3000,{goE,goE,waitE,waitE}}, SysTick_Wait10ms(FSM[S].Time);
{0x14, 500,{goN,goN,goN,goN}}};
Input = SENSOR; // read sensors
uint32_t S; // index to the current state
uint32_t Input; S = FSM[S].Next[Input];
}
}
Stepper motor
 A bipolar stepper motor has two coils on the stator
 There is always current flowing through both coils.
 When current flows through both coils, the motor does not spin
 To move a bipolar stepper, we reverse the direction of current through

one (not both) of the coils
 To move it again we reverse the direction of current in the other coil
 To make the current go up, the microcontroller outputs a binary 01 to

the interface.
 To make the current go down, it outputs a binary 10
 Since there are 2 coils, four outputs will be required (e.g.,

01012 means up/up)
I/O Synchronization
 Performance Measure - goodness of the system
 Latency - time between when the I/O device indicated service is required and the time when service is initiated
 Includes hardware delays in the digital hardware plus computer software delays.
 For an input device, software latency - time between new input data ready and the software reading the data
 For an output device, latency - delay from output device idle and the software giving the device new data to output.
 A real-time system is one that can guarantee a worst case latency - the software response time is small and bounded - to satisfy
overall specification of the system, such as no lost data.
 Throughput or bandwidth is the maximum data flow in bytes/second that can be processed by the system
 Priority determines the order of service when two or more requests are made simultaneously
 Priority also determines if a high-priority request should be allowed to suspend a low priority request that is currently being
processed

Synchronization Mechanisms

Synchronization Mechanisms

FIFO
Store or buffer data in a first in first out (FIFO) queue, while passing the data from one
module to another.
Buffer separates the generation of data from the consumption of data-very efficient
Can handle situations where there is an increase or decrease in the rates at which data is
produced or consumed
Other names - bounded buffer, producer-consumer, and buffered I/O
Data are entered into the FIFO as they arrive - call Put to store data in the FIFO
Data are removed as they leave - call Get to remove data from the FIFO
Maintains the order of the data, as it passes through the buffer

Serial Communication
Serial transmission involves sending one bit at a time, such that the data is spread out
over time
The total number of bits transmitted per second is called the baud rate
The reciprocal of the baud rate is the bit time, which is the time to send one bit
frame is the smallest complete unit of serial transmission
bandwidth - the amount of data or useful information transmitted per second
bandwidth of the serial channel (in bytes/second) ?

Asynchronous serial Communication
 Transmitter - 16-element FIFO and a 10-bit shift register
 To output data using the UART, the software will first check to make sure the transmit FIFO is not full (it will wait if TXFF is 1) and then
write to the transmit data register (UART0_DR_R )
 Shifted out in order - start, b0, b1, b2, b3, b4, b5, b6, b7, and then stop
 Transmit data register is write only
 Even though the transmit data register is at the same address as the receive data register, the transmit and receive data registers are two
separate registers.

Asynchronous serial Communication

Initialization steps
 To activate a UART, turn on the UART clock in the RCGCUART register
 Turn on the clock for the digital port in the RCGCGPIO register.
 Enable the transmit and receive pins as digital signals.
 The alternative function for these pins must also be selected. In particular we set bits in both the AFSEL and PCTL registers.
 The OE, BE, PE, and FE are error flags associated with the receiver.
 You can see these flags in two places: associated with each data byte in UART0_DR_R or as a separate error register in UART0_RSR_R.
 The overrun error (OE) is set if data has been lost because the input driver latency is too long.
 BE is a break error, meaning the other device has sent a break.
 PE is a parity error
 The framing error (FE) will get set if the baud rates do not match.
 The software can clear these four error flags by writing any value to UART0_RSR_R.

The status of the two FIFOs can be seen in the UART0_FR_R register.
The UART0_CTL_R control register contains the bits that turn on the UART.
TXE is the Transmitter Enable bit,
RXE is the Receiver Enable bit.
We set TXE, RXE, and UARTEN equal to 1 in order to activate the UART device.
However, we should clear UARTEN during the initialization sequence.

// Wait for new input, then return ASCII code
// Assumes a 80 MHz bus clock, creates 115200 baud rate
char UART_InChar(void){
void UART_Init(void){ // should be called only once
SYSCTL_RCGCUART_R |= 0x00000002; // activate UART1 while((UART0_FR_R&0x0010) != 0); // wait until RXFE is 0
SYSCTL_RCGCGPIO_R |= 0x00000004; // activate port C return((char)(UART0_DR_R&0xFF));
UART1_CTL_R &= ~0x00000001; // disable UART }

UART1_IBRD_R = 43; // IBRD = int(80,000,000/(16*115,200)) = int(43.40278)
// Wait for buffer to be not full, then output
UART1_FBRD_R = 26; // FBRD = round(0.40278 * 64) = 26
void UART_OutChar(char data){
UART1_LCRH_R = 0x00000070; // 8 bit, no parity bits, one stop, FIFOs
while((UART0_FR_R&0x0020) != 0); // wait until TXFF is 0
UART1_CTL_R |= 0x00000001; // enable UART
GPIO_PORTC_AFSEL_R |= 0x30; // enable alt funct on PC5-4 UART0_DR_R = data;
GPIO_PORTC_DEN_R |= 0x30; // configure PC5-4 as UART1 }
GPIO_PORTC_PCTL_R = (GPIO_PORTC_PCTL_R&0xFF00FFFF)+0x00220000;
GPIO_PORTC_AMSEL_R &= ~0x30; // disable analog on PC5-4

Synchronous Serial Interface
SSI – master/ slave
(1 master + 1 slave) or (1 master + multiple slaves)
With multiple slaves – ring or star configuration
Master initiates all data communication
Two devices communicating with synchronous serial interfaces (SSI) operate from the same clock
(synchronized)
With a SSI protocol, the clock signal is included in the interface cable between devices
The master device creates the clock, and the slave device(s) uses the clock to latch the data (in or out.)

Synchronous Serial Interface
The SSI protocol includes four I/O lines
The slave select SSI0Fss - control signal from master to slave signal signifying the channel is active
The second line, SCK, is a 50% duty cycle clock generated by the master
The SSI0Tx (master out slave in, MOSI) is a data line driven by the master and received by the slave
 The SSI0Rx (master in slave out, MISO) is a data line driven by the slave and received by the master
In order to work properly, the transmitting device uses one edge of the clock to change its output, and
the receiving device uses the other edge to accept the data

Interrupts
Automatic transfer of software execution in response to a hardware event
Hardware event – trigger - Busy to ready transition – raise a trigger flag
Thread – path of action of a software as it executes
Interrupt service routine – background thread
Created by Hardware interrupt request – killed when ISR returns from the interrupt
New thread created for each interrupt- local variable and registers used in the ISR are
unique and separate
Multi threaded system – many threads – co-operate, communicate and synchronize with
each other

Interrupts
To Arm/ disarm a device – enable the source of interrupts
Each trigger has a separate arm bit
Arms a trigger – if interested in receiving the interrupt from that source
Enable/ disable interrupts – postponing to a later time
Arm cortex – 1 enable bit for entire interrupt system
Disable if it is not convenient to receive interrupt at that time

Registers
The special-purpose mask register, PRIMASK
BASEPRI = Base Priority Mask Register
Nonzero = defines the base priority for exception processing.

The processor does not process any exception with a priority value greater than or equal to
BASEPRI
Interrupt Program Status Register

Conditions for an interrupt to be generated
Device Arm
NVIC enable
Global enable – I bit must be 0
Level of Priority
Trigger – Hardware trigger flag – RIS register

Context switch
An Interrupt causes the following events
Current instruction execution is completed
Execution of the current program is suspended
Pushes 8 register on stack – R0, R1, R2, R3, R12, LR, PC, PSR --- R0 on top
LR – set with 0xFFFFFFF9
IPSR – set to interrupt number being processed
PC is loaded with the address of the ISR

Interthread Communication and Synchronization



Nested Vectored Interrupt Controller (NVIC)
Hardware unit that coordinates among interrupts from multiple

sources
Define priority level of each interrupt source (NVIC_PRIx_R registers)
Separate enable flag for each interrupt source (NVIC_EN0_R,
NVIC_EN1_R)
Interrupt does not set I bit

Higher priority interrupts can interrupt lower priority ones

NVIC Interrupt Enable Registers
Enable registers –
NVIC_EN0_R to NVIC_EN4_R
Each 32-bit register has a single enable bit for a particular device
NVIC_EN0_R control the IRQ numbers 0 to 31 (interrupt numbers 16 – 47)
NVIC_EN1_R control the IRQ numbers 32 to 47 (interrupt numbers 48 – 63)

NVIC Priority Registers
High order three bits of each byte define priority

Registers
GPIO Register Tivaware Name Each Bit Value (Lowest 8-Bit) and Each Pin Function
Interrupt sense register

Determines level or edge triggered
GPIOIS GPIO_PORTx_IS_R
0: Detect an edge (edge-sensitive) on the pin,
1: Detect a level (level-sensitive) on the pin.
0: Interrupt is controlled by GPIOIEV,

GPIOIBE GPIO_PORTx_IBE_R
1: Both edges on the corresponding pin trigger an interrupt
GPIO Interrupt Event Register

Determines the detecting edges or levels.
GPIOIEV GPIO_PORTx_IEV_R
0: A falling edge or a LOW level,
1: A rising edge or a HIGH level triggers an interrupt
GPIO Interrupt Mask Register

Masks (disables) or unmask (enable) an interrupt.
GPIOIM GPIO_PORTx_IM_R
0: Interrupt is masked (disabled),
1: Interrupt is unmasked (enabled).

GPIOIS GPIOIEV
(interrupt sense) (Interrupt Event)
0 0 Falling edge
0 1 Rising edge
1 0 Low level
1 1 High level
DIR AFSEL PTCL IS IBE IEV IME Port mode
0 0 0000 0 0 0 0 Input, falling edge trigger, busy wait
0 0 0000 0 0 1 0 Input, rising edge trigger, busy wait
0 0 0000 0 1 - 0 Input, both edges trigger, busy wait

0 0 0000 0 0 0 1 Input, falling edge trigger, interrupt
0 0 0000 0 0 1 1 Input, rising edge trigger, interrupt
0 0 0000 0 1 - 1 Input, both edges trigger, interrupt

Registers
GPIO Register Tivaware Name Each Bit Value (Lowest 8-Bit) and Each Pin Function
GPIO Raw Interrupt Status Register

Indicates the raw interrupt status for a pin.
0: No interrupt occurred on the pin,
GPIORIS GPIO_PORTx_RIS_R 1: An interrupt is occurred on the pin.
For the edge-triggered interrupts,
write a 1 to the corresponding pin in ICR_R to clear that interrupt.
For level-triggered interrupt, no action is needed.
GPIO Masked Interrupt Status Register

Indicates the state of the interrupt.
0: An interrupt condition on the corresponding pin is masked or has not
GPIOMIS GPIO_PORTx_MIS_R
occurred.
1: An interrupt condition on the corresponding pin has triggered an interrupt
to the interrupt controller.
GPIO Interrupt Clear Register

Clears an edge-triggered interrupt.
GPIOICR GPIO_PORTx_ICR_R
0: No action,
1: The corresponded edge-triggered interrupt is cleared.

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ELE546T

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

 Components inside a Embedded system

 A series – Cell phones

 R series – Real time

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Ability to make profit

Lower power consumption

Time – Correct answer at correct time

A correct value at a wrong time is a fault.

Embedded system  Intel: 4004, ..8080,.. x86

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

RAM (DRAM, SRAM) Read-only

 I/O Flash memory

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

 Entire CPU fabricated on a chip

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Fast and Effective

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

There is an operating system that handles low level operations

Microcontroller – no disk to read from

Size of the ROM limits the maximum size of program

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

The company founded in 1990

Initially owned by Acorn, Apple and VLSI

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Some Application examples:

Mainly used in battery operated devices

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

A whole family of ARM exist

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Major design features of RISC Architecture:

Pipeline: decode in one stage

Registers: large number of general purpose registers

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

In-line barrel shifter results in more complex instruction

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Significant speedup ( ideally k-folds)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Registers (GPRs, special)

Data Types (char, integer, float)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Opcode field specifies the processor command to execute

Label Opcode Operands Comment

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

MOV R0,#100 ; R0=100, immediate addressing

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)

LDR R0,[R1] ; R0= value pointed to by R1

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: rohinip@iiitdm.ac.in)