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Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box
SOI MOSFETs With Back-Gate Control

Article  in  IEEE Transactions on Electron Devices · October 2015

DOI: 10.1109/TED.2015.2464076

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 10, OCTOBER 2015
Analytical Compact Model for Lightly Doped
Nanoscale Ultrathin-Body and Box SOI
MOSFETs With Back-Gate Control
Theano A. Karatsori, Andreas Tsormpatzoglou, Christoforos G. Theodorou, Eleftherios G. Ioannidis,
Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, Fellow, IEEE,
and Charalabos A. Dimitriadis, Member, IEEE
Abstract— An analytical drain-current compact model for
lightly doped short-channel ultrathin-body and box fully
depleted silicon-on-insulator MOSFETs with back-gate control is
presented. The model includes the effects of drain-induced
barrier lowering, channel-length modulation, saturation velocity,
mobility degradation, quantum confinement, velocity overshoot,
and self-heating. The proposed model has been validated by
comparing with the experimental transfer and output character-
istics of devices with the channel lengths of 30 and 240 nm and
with back bias varying from −3 to +3 V. The good accuracy of the
model makes it suitable for implementation in circuit simulation
tools.
Index Terms— Back-gate control, compact model, fully
depleted silicon-on-insulator (FD-SOI) ultrathin-body and
box (UTBB) MOSFETs.
I. I NTRODUCTION
U LTRATHIN-BODY and box (UTBB) fully depleted
silicon-on-insulator (FD-SOI) MOSFETs are considered,
as one of the best candidates for controlling the short-
channel effects (SCEs) in the future sub-28-nm CMOS
generations [1]–[3]. Compared with the fin-shaped field-effect
transistors, the UTBB FD-SOI technology is a much simpler
process. Furthermore, due to the strong back-to-front gate
coupling effect, the threshold voltage of UTBB FD-SOI
MOSFETs can be controlled with back-gate bias instead of
using different channel doping concentrations and, thus, avoid
variability due to random dopant fluctuations [4]. However,
thin buried oxide (BOX) could trigger strong coupling from
the drain through the lightly doped substrate, resulting in
loss of the gate control over the channel [5]. Incorporation
Manuscript received September 11, 2014; revised June 2, 2015; accepted
July 23, 2015. Date of publication August 20, 2015; date of current version
September 18, 2015. This work was supported by the ARISTEIA II Project
under Grant 4154 through the Greek General Secretariat for Research and
Technology within the European Social Fund and National Funds. The review
of this paper was arranged by Editor J. C. S. Woo.
T. A. Karatsori, A. Tsormpatzoglou, and C. A. Dimitriadis are
with the Department of Physics, Aristotle University of Thessaloniki,
Thessaloniki 54124, Greece (e-mail: tkarat@physics.auth.gr;
atsormpa@auth.gr; cdimitri@physics.auth.gr).
C. G. Theodorou, E. G. Ioannidis, and G. Ghibaudo are with the
Institut de Microelectronique, Electromagnetisme et Photonique-
Laboratoire d’Hyperfrequences et de Caracterisation Laboratory,
Minatec, Grenoble 38016, France (e-mail: theodoch@minatec.inpg.fr;
ioannidis1980@gmail.com; ghibaudo@minatec.inpg.fr).
S. Haendler and N. Planes are with STMicroelectronics, Crolles 38921,
France (e-mail: sebastien.haendler@st.com; nicolas.planes@st.com).
Digital Object Identifier 10.1109/TED.2015.2464076
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
3117
of a highly doped layer underneath the BOX, a so-called
backplane [6], has been proposed to eliminate this drawback of
thin BOX.
To exploit the benefits of UTBB FD-SOI MOSFETs with
back gate consisting of highly doped backplane, an analytical,
accurate, and fast compact model that properly describes
the transistor behavior for a wide range of back biases
is required. In the literature, several compact models for
asymmetric-independent double-gate (DG) MOSFETs have
been reported [7]–[17]. These models are based on the inver-
sion charge [7], [8], surface potential [9]– [15], and threshold
voltage [16], [17]. However, most of them either concern
long-channel devices or are based on numerical techniques,
which are less desirable due to the poor speed of simulation.
Although the surface potential-based models become more
popular, for independent DG MOSFET, they are very complex
because of the three substrate operating modes: inversion,
depletion, and accumulation. Recently, an accurate and
computationally efficient surface-potential-based model for
UTBB SOI MOSFETs has been presented, which provides
accurate results when the interface between body and BOX is
depleted, and the back gate is biased in the reverse and low
forward bias range [14]. Although this model well predicts the
behavior of long-channel and short-channel devices, equations
for short-channel modeling are not discussed. The model
presented in [14] has been extended to capture the substrate
depletion effect in short-channel devices, but without capturing
the backside inversion effect [18]. Recently, a surface potential
compact model has been proposed covering all operating
modes [15]. However, the front surface potential is calculated
from a complicated equation by developing an algorithm
requiring different computation steps and fundamental effects
[such as velocity overshoot (VO) and self-heating (SH)]
in short-channel FD-SOI devices were not considered. The
threshold voltage-based models well predict the behavior of
long-channel devices [16] or short-channel devices in the
substrate accumulation operating mode [17]. In this paper, we
propose a threshold voltage-based compact model, which is
accurate for a wide range of back-gate biases in all oper-
ating modes and for all channel lengths using few model
parameters.
Recently, we developed simple analytical models for the
threshold voltage and the ideality factor of the front interface
for asymmetrical UTBB FD-SOI MOSFETs [19]. In this
3118 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 10, OCTOBER 2015

density N A of the silicon body, that is

ϕ(x c ,ym )
ni e Vth = NA (1)
where ϕ (x c , ym ) is the channel potential at the conductive
path x c and the position ym of the minimum potential, which
shows weak dependence on the gate voltage in the subthresh-
old region [21], Vth is the thermal voltage, and n i is the
intrinsic carrier concentration of silicon. The potential at the
conductive path ϕ(x c , ym ) can be written as [19]
ϕ(x c , ym ) = ϕ1 (x c , ym ) + ϕ2 (x c , ym )Vgf (2a)
where
Fig. 1. Schematic of the UTBB FD-SOI MOSFET cross section. ϕ1 (x c , ym )
 2L−ym (xc ) ym (x c )   L+ym (xc ) L−ym (x c )
paper, we have improved our previous model by defining e λ(xc ) −e λ(xc ) Vbi + e λ(xc ) −e λ(xc ) (Vbi +Vds)
the threshold voltage as the gate voltage when the electron = 2L
e λ(xc ) − 1
density at the effective conductive path reaches the doping  L−ym (xc ) −ym (x c )  L ym (x c )  ym (x c ) 
e λ(xc ) −e λ(xc ) e λ(xc ) −e λ(xc ) e λ(xc ) −1 Vgb  β(x )
density of the silicon body. Based on the analytical models c
for the voltage and the ideality factor, we derive a complete + 2L
analytical charge-based compact model for the drain current e λ(xc ) −1
(2b)
valid in all regions of operation with back-gate control, which  m (x c )
 L ym (x c ) 
− yλ(x
includes the drain-induced barrier lowering, channel-length 1−e c ) e c −e c
λ(x ) λ(x )

modulation (CLM), saturation velocity, mobility degradation, ϕ2 (x c , ym ) = a(x c ) L

(2c)
quantum confinement, VO, and SH effects. The proposed 1 + e λ(xc )
model has been validated by comparing the transfer and output εSi toxb + εox (tSi − x c )
a(x c ) = (2d)
characteristics with the experimental results and for a wide εSi (toxf + toxb ) + εox tSi
range of back-gate bias voltages. εSi toxf + εox x c
β(x c ) = . (2e)
εSi (toxf + toxb ) + εox tSi
II. D ISCUSSION ON THE T HRESHOLD VOLTAGE M ODEL Vgf = Vgf − Vfbf , Vgb
 = V − V , V is the built-in potential
gb fbb bi
A schematic cross section of an asymmetric n-channel across the source/drain-channel junctions, Vfbf(b) = φ f (b)
UTBB FD-SOI MOSFET and the definition of the geometrical is the flat-band voltage of the front (back) gate, φ f (b)
characteristics are shown in Fig. 1. The threshold voltage is the work function difference between metal gate/silicon,
in [19] is defined quantitatively as the gate voltage at which and λ (x c ) is the natural length at the effective conductive
the minimum carrier charge sheet density at the effective path [19]. Thus, the front-gate threshold voltage can be derived
conductive path reaches a value Q th adequate to achieve the from the relation
turn-ON condition. An empirical expression for Q th has been ϕ1 (x c ,ym ) + ϕ2 (x c ,ym )Vtf

derived in terms of the drain-bias Vds , device geometrical ni e Vth = NA (3)

parameters, and effective conductive path parameters to fit
the model with simulated results. In this paper, we derive
an analytical threshold voltage model for FD-SOI MOSFETs,
using a definition from the literature based on the electron
density at the front and back channels simultaneously [20].
In deep submicrometer FD-SOI MOSFETs, it has been
shown that the threshold voltage can be defined analytically
and with good accuracy as the gate voltage at which the sum
of the electron densities at the front and back channels reaches
the doping density of the silicon body [20]. Considering that
the work functions of the front and back metal gates are close,
in the case where the front-gate oxide is much thinner, the
case for the dominance of the front channel is sufficient to
explain the experimental results for a wide range of back-gate
biases. Furthermore, to derive analytical expression for the
threshold voltage, the effective conductive path concept should
be accounted for [19]. Thus, for thinner front-gate oxide, the
threshold voltage is defined as the gate voltage at which the
electron density at the effective conductive path located at a
distance x = x c from the front interface is equal to the doping
from which, we obtain the explicit expression
 
Vth N A − ϕ1 (xVc ,ym )
Vtf = Vfbf + ln e th . (4)
ϕ2 (x c , ym ) ni
In (4), the Vtf dependence on Vgb is captured through the
potential φ1 (x c , ym ), which is described by (2b).
The threshold voltage model has been verified by comparing
the model with the experimental results. The devices measured
in this work are n-MOS transistors with backplane, issued from
the 28-nm FD-SOI CMOS technology with channel width
W = 0.5 μm and channel length L = 30 nm, fabricated by
STM, France [22]. The doping concentration of the channel
is N A ≈ 1015 cm−3 , and the doping concentration of the
source/drain contacts is NSD ≈ 1020 cm−3 . The front-gate
stack consists of TiN/HfO2 -based dielectric with the equivalent
oxide thickness of 1.55 nm, the BOX thickness is 25 nm,
and the silicon film thickness is 7 nm. The change of the
TiN work function from 4.3 to 4.65 eV depending on the
process parameters [23] and the variability of the TiN work
function due to grain-orientation [24] introduce uncertainty
KARATSORI et al.: ANALYTICAL COMPACT MODEL FOR LIGHTLY DOPED NANOSCALE UTBB SOI MOSFETs 3119

charges, in the subthreshold region, the charge sheet density

is defined as [17]
Vgf −Vtf −η f V y
η f Vth
i = η f Coxf Vth e
Q wi (6)

and in the strong inversion region, it becomes

i = Coxf (Vgf − Vtf − η f V y ).

Q si (7)

In (6) and (7), Coxf is the front-gate oxide capacitance per unit
area, η f is the ideality factor of the front-gate interface, and
Fig. 2. Front-gate threshold voltage Vtg versus back-gate voltage Vgb of a
UTBB FD-SOI MOSFET with W = 0.5 μm, L = 30 nm, toxf = 1.55 nm,
Vy is the quasi-Fermi potential in the channel (Vy = 0 at the
toxb = 25 nm, tSi = 7 nm, and N A = 1015 cm−3 . source and Vy = Vds at the drain). The SCEs and the coupling
of the front and back gates are included in (6) and (7) through
the parameters Vtf and η f [19].
for determining φ f . The substrate is standard p-type lightly
doped silicon, implanted with In to form a thin localized In order to obtain a single expression for the inversion
charge density denoted by Q i , valid from the subthreshold
highly doped (∼1018 cm−3 ) p-type layer underneath the BOX.
to the strong inversion region, we have used an interpolating
Taking the value of 4.05 eV for the electron affinity of
the silicon, the determined work function difference for the function of the form
 
back gate is φb = 0.17 V. Considering a decrease in the V −V −η V
gf tf f y
η f Vth
silicon work function by ∼0.13 V due to quantum confinement Q i = η f Coxf Vth ln 1 + e . (8)
(Section IV), it is φb = 0.3 V.
Fig. 2 shows the dependence of the front-gate threshold The normalized inversion sheet charge density
voltage Vtf on the back-gate bias Vgb . The values of Vtf qi = Q i /Coxf Vth valid in all regions of operation is
calculated from the model are compared with the experimental  V −V −η V

gf tf f y
values extracted from the transconductance linear extrapola- η f Vth
qi = η f ln 1 + e . (9)
tion method [21], as both values are determined at the onset
of inversion. The impact of the back-gate bias on the location
of the effective conductive path x c has been modeled with the The expression for the drain current is derived considering
empirical relations the charge distribution in the entire channel instead of the
  charge sheet approximation, which introduces some error in
xc Vgb
= Ac exp for Vgb ≤ 0 (5a) the moderate inversion region. Based on the drift–diffusion
tSi Bc transport, the drain current at any point y in the channel is
xc
= Ac + 0.04 × Vgb for Vgb > 0 (5b) given by [14]
tSi
which are in qualitative agreement with the simulation d Vy
Ids = W μCoxf Vth qi (10)
results of the mean channel position in UTBB FD-SOI dy
MOSFETs [25]. The model values of Vtf were obtained using where μ is the electron mobility, W is the gate width, and L is
φ f = 0.37 V, Ac = 0.2, and Bc = 3.1 V for the the gate length. With including the carrier saturation velocity
devices of the investigated SOI technology. It is noticed that effect, the mobility can be approximated as follows [26]:
φ f = 0.37 V is primarily an adjustment to the real
Vtf values, which includes the Vtf shift due to quantum μeff μeff
μ=  = (11)
 dϕs 
μeff μeff Vth dqi
1 + υsat d y
confinement [14] and interface traps [19], in addition to the 1+  dy 
υsat
work function difference between metal gate and silicon. The
results of Fig. 2 demonstrate the validity of the modified where ϕs is the surface potential, υsat is the saturation velocity
threshold voltage model. The parameters φ f , Ac , and Bc , with best value in MOS transistors ≈2 × 107 cm/s [27], and
extracted from the experimental data of Vtf versus Vgb , are μeff is the effective carrier mobility, which includes the effect
used in the drain-current model. of the transversal field. From (9), we obtain
 qi 
dqi ηf − d Vy
III. C OMPACT M ODEL D ESCRIPTION = e ηf − 1 . (12)
dy Vth dy
In charge-based models, the drain-current calculation is
usually based on the linear or exponential dependence of the Using (11) and (12), integration from the source to the drain
channel charge density in the strong or in the subthreshold results in the following drain-current equation in terms of
regions of operation, respectively. In an independent asymmet- the normalized charges at the source (qs ) and drain (qd )
ric DG device operation, the front interface charge becomes electrodes
relevant to compute the drain current by defining the threshold
W μeff Coxf Vth Vth qd qi
voltage and the ideality factor at an effective conductive path Ids = μeff Vth
dqi . (13)
L + υsat (qs − qd ) η f qs e− η f − 1
qi
controlled by the back-gate bias [19]. Starting from the channel
3120 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 10, OCTOBER 2015

Considering the effect of the series resistance Rsd , the mobility

attenuation factor θ1 becomes
θ1 = θ1,0 + W μo Rsd Coxf /L (19)
where θ1,0 is the linear mobility attenuation coefficient.
In the saturation region, based on [31] and [32], the channel
length shortening L due to the CLM effect can be
modeled as
 
(Vds − Vdsat + 0.05) tanh(Vds /Vdsat )3
L = λ f ln 1 +
Fig. 3. Dilogarithm function of (15) and analytical function of the right-hand VE
side of (15) as a function of qi /η f showing large error in the strong inversion (20)
region. The error is minimized using the optimized analytical function of (16).
where λ f is the natural length at the conductive path and
VE is a fitting parameter. It should be noted that (17) will lead
The integral in (13) can be written in terms of a dilogarithm to an implicit expression for the saturation drain voltage Vdsat .
function Considering that the second charge term in the brackets of (17)

 qi  q
W μeff Coxf Vth2 η f ηf π 2  d is dominant in the above-threshold region, an explicit expres-
Ids = poly log 2, 1 − e − . sion for Vdsat can be obtained from the relation dIds /d Vds = 0
L + μeff Vth
(q s −q d ) 6 q s
υsat yielding
(14) 
 
υsat L 2 2qs Vth υsat L υsat L qs Vth
In order to express the drain-current equation explicitly in Vdsat = + − + −qs Vth .
terms of the charge densities qs and qd in (14), the dilogarithm μeff μeff μeff ηf
function is replaced by the first two terms of the Taylor series (21)
expansion as Including the CLM effect, the drain-current equation
 qi   
qi qi 2 becomes
poly log 2, 1 − e η f = − − . (15)

ηf 2η f W μeff Coxf Vth2 1  2

Ids = (qs − qd ) + q − qd
2
In (15), the error between the exact value of the dilogarithm L eff + μeff Vth
υsat (qs − qd )
2η f s
function of the left-hand side and the analytical function of the (22)
right-hand side is up to ∼60% in the strong inversion region,
as shown in Fig. 3. This error is minimized with the analytical where L eff = L − L. The first charge term in the brackets
function (16) for the dilogarithm function (Fig. 3) of (22) dominates in weak inversion, while the second charge
 qi 
term in the brackets and the charge term in the denominator
qi q2 dominate in the strong inversion region. As the threshold
poly log 2, 1 − e η f = − − i2 (16)
ηf 2η f voltage Vtf is determined at the onset of inversion [19],
we found that, for a smooth transition from weak to strong
which is used in (14) for compact modeling purpose.
inversion, the charge of weak inversion should be obtained
From (14) and (16), we obtain the following analytical expres-
from (9) with increasing Vtf by 2.5 × Vth and the charge terms
sion for Ids in terms of the normalized charges qs and qd :

 of strong inversion with increasing Vtf by 5 × Vth .
W μeff Coxf Vth2 1  2

Ids = (qs − qd ) + q − qd .
2
L + μeff Vth
υsat (qs − qd )
2η f s IV. I MPROVEMENT OF THE C OMPACT M ODEL
(17) The SCEs, mobility degradation, saturation velocity, and
coupling of front-back gates were already considered in the
We note that (17) constitutes the basic structure of com-
model through the threshold voltage, subthreshold swing coef-
pact drain-current models like Berkeley Short-channel IGFET
ficient, and carrier mobility. In order to improve the accuracy
Model (BSIM) [26], [28].
of the model, we include some other important effects, namely
The effective mobility μeff degradation due to the vertical
the quantum-mechanical effects (QMEs), VO effects, and
gate field is expressed in terms of the charge at the source
SH effects.
side qs as [29]
As the silicon body thickness tSi is scaled down <10 nm,
μo
μeff = (18) the splitting of the energy bands has to be considered in the
1 + θ1 Vth qs + θ2 (Vth qs )2 model. Due to this splitting, the lowest energy band rises and
where μo is the low-field mobility, and θ1 and θ2 are the the carriers need more energy to occupy it, resulting in an
mobility attenuation factors of the first and second order, increase in the threshold voltage. For compact modeling, the
which can be extracted from the experimental data at low drain quantum confinement effect has been considered in the model
voltage using a modified Y-function method [30]. The para- with decreasing the semiconductor work function ϕs by the
meter θ2 is correlated with the surface roughness scattering, minimum energy of the lowest conduction subband to a new
while θ1 includes phonon scattering and Coulomb scattering. work function φsnew [26]. Thus, the shift in Vtf due to quantum
KARATSORI et al.: ANALYTICAL COMPACT MODEL FOR LIGHTLY DOPED NANOSCALE UTBB SOI MOSFETs
confinement is included in the model considering the work
function difference as [26]
φ = φm − φsnew (23)
where φm is the gate metal work function. The shift in the
threshold voltage due to the quantum confinement is Vtf =
0.085 + 2.178/tSi 2 proposed in Berkeley Short-channel IGFET
Model-Independent Multi-Gate [14], where tSi is expressed in
nanometer. Thus, for tSi = 7 nm, the contribution of quantum
confinement in φ is ∼0.129 V. The application of compact
models in ultrathin symmetric common DG and asymmetric-
independent DG MOSFETs demonstrates that the threshold
voltage shift due to structural confinement is sufficient to
predict, with good accuracy, the current–voltage characteris-
tics, without considering the quantum degradation of the gate
capacitance [14], [26].
In UTBB FD-SOI MOSFETs, positive Vgb moves the mean
channel position deeper away from the front-gate interface
into the silicon film [25]. Thus, in addition to the threshold
voltage described by (4) in terms of the mean channel position,
this effect is also considered in modifying the ideality factor
prior to the drain-current calculation. The following back-gate
bias-dependent equivalent thicknesses for the front-gate oxide
and the silicon body are applied to η f in (22) to refine the
drain-current calculation [25]
εox
toxf,eq = toxf + xc (24)
εSi
εox
tSi,eq = tSi − xc . (25)
εSi
In short-channel transistors, in contrast to the classical
drift–diffusion models, the saturated velocity in the saturation
region can achieve higher values than υsat due to nonstationary
effects. This phenomenon is known as VO [33]. Considering
the VO effect for nanoscale devices, the contribution of the
VO in (22) is introduced in a simple way by adding a term in
the saturation velocity as [33]
 
2λw
υsat,vo = υsat 1 + (26)
L by
where λw is the energy-relaxation length defined as
λw ≈ 2υsat τw , with τw being the energy-relaxation time
constant.
Due to the thin silicon thickness in short-UTBB FD-SOI
devices, the SH effect is expected to be significant [34].
Experimental evidence for the presence of SH effects in the
investigated UTBB FD-SOI transistors has been presented
in [35]. Due to the ultrathin body, very small channel length,
and thin BOX of the fully depleted device, heat conduction
from the channel to the substrate is very quick. Therefore, the
rise of the lattice temperature can be assumed to be uniform
throughout the channel, and, in turn, linearly related to the
power dissipated in the device as [16], [34]
T − To = Rth Vds Ids (27)
where T is the lattice temperature, To is the ambient
temperature, and Rth is the thermal resistance
 device under study, extracted from the transfer characteristics
1 tox,b
Rth = (28)
2W K ox K Si tSi
3121
with K ox = 1.4 W/m · K and K Si = 63 W/m · K, the
thermal conductivities of SiO2 and silicon, respectively. Once
the lattice temperature T is obtained, the saturation velocity,
threshold voltage, and mobility have to be recalculated to
obtain the drain current at that temperature. For typical
temperature rise by 80 K, the saturation velocity υsat = 2.4 ×
107 /(1 + 0.8 × exp(T /600)) decreases from 1.03 × 107 cm/s
at 300 K to 0.96 × 107 cm/s at 380 K. Thus, υsat has weak
temperature dependence, and it can be considered constant
in our model. Furthermore, it has been demonstrated that, in
lightly doped UTBB SOI MOSFETs, the effect of temperature
on the threshold voltage is negligible [36].
In addition to the mobility reduction due to the vertical
gate-oxide field as described by (18), the carrier mobility is
degraded with increasing the temperature by the SH effect due
to different scattering mechanisms. Whereas in Technology
Computer Aided Design simulations, the local temperature
is considered; in compact modeling, the mobility cannot be
explicitly derived considering local temperature variations.
For compact modeling, taking uniform the lattice temperature
throughout the channel of nanoscale UTBB FD-SOI devices
[16], [34] and considering as is usual a power law for the
temperature dependence of the mobility, the effective mobility
μeff,sh at temperature T is expressed in terms of the effective
mobility μeff at the ambient temperature To as
 r
To μeff
μef,sh = μeff =  r (29)
T 1 + Rth TVod Ids
where r is a fitting parameter. Note that, for typical UTBB
SOI devices, the term Rth Vd Ids /To is of the order of 10−2 ,
which makes possible the first-order expansion of the power
term in (29) as
μeff
μef,sh ≈ . (30)
1 + r RthTVod Ids
In (22), substituting μeff with μeff,sh , we get a quadratic
expression in terms of Ids , and the solution of which is given

−A2 + A22 + 4 A1 A0
Ids = (31)
2 A1  
W q 2 − qd2
A0 = μeff Coxf Vth2 (qs − qd ) + s (32a)
L eff 2η f
r Rth Vds Vth μeff
A1 = , A2 = 1 + (qs − qd ) . (32b)
To υsat,vo L eff
V. M ODEL VALIDATION
The drain-current compact model has been verified by
comparing the model with the experimental results. The
devices measured in this work are n-MOS transistors with
backplane, issued from the 28-nm FD-SOI CMOS technology
with channel width W = 0.5 μm and channel length L = 30
and 240 nm, as described in Section II. The parameters of the
measured at Vds = 30 mV at different back-gate voltages
using the Y-function method [30], are listed in Table I. It is
3122 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 10, OCTOBER 2015

TABLE I
E XTRACTED M OBILITY PARAMETERS FOR UTBB FD-SOI
MOSFET W ITH L = 30 nm

Fig. 5. (a) and (b) Experimental (symbols) and modeled (solid lines) output
characteristics and (c) and (d) output conductance of a silicon UTBB FD-SOI
MOSFET with W = 0.5 μm, L = 30 nm, tSi = 7 nm, and tox = 1.55 nm,
measured at back-gate voltages Vgb = +3 and −3 V.

Fig. 4. (a) and (b) Experimental (symbols) and modeled (solid lines) transfer
and (c) and (d) transconductance characteristics of silicon UTBB FD-SOI
MOSFET with W = 0.5 μm, L = 30 nm, tSi = 7 nm, and tox = 1.55 nm,
measured at drain voltages 0.1 and 1 V and different back-gate voltages Vgb .

noted that the mobility is close to 93.5 cm2 /Vs, while the
parameters θ1 and θ2 are increased with negative Vgb due to
stronger surface roughness and phonon scattering mechanisms
at the front interface. This is consistent with the finding that
the effective carrier mobility is degraded by the proximity with
the HfO2 -based front-gate dielectric [37].
Fig. 4(a) and (b) presents the measured transfer character-
istics for Vds = 0.1 and 1 V, with back-bias voltages Vgb
varying from −3 to +3 V, and Fig. 5(a) and (b) presents
the output characteristics with the parameters: the front-gate
bias Vgf and different Vgb values. Good agreement between Fig. 6. Dependence of the electron mobility on the effective electric
model results and experimental measurements in all operation field E eff (a) and the temperature T due to the SH effect (b) used to reproduce
regimes and for a wide range of back biases is obtained, using the transfer and output characteristics of Figs. 4 and 5.
fixed values for the parameters: φ f = 0.37 V for the front
gate, φb = 0.3 V for the back gate, VE = 0.5 V, λw = 100 shows the dependence of the electron mobility on the effective
and 70 nm for Vgb ≤ 0 and Vgb > 0, respectively, and r = 0.5, electric field E eff = (q N A tSi /εSi )+Coxf (Vgf −Vtf )/2εSi and the
which is close to the value of r = 0.6 found for nanoscale temperature T for different back-gate voltages, used to obtain
(L = 22 nm) DG MOSFETs [38]. The low value of the the results of Figs. 4 and 5, justifying the proposed mobility
temperature exponent r in nanoscale FD-SOI devices has been model.
confirmed from the experimental measurements of the electron In order to check further the accuracy of the model, the
mobility with temperature [39], [40]. It has been found that the small-signal parameters of transconductance gm and output
mobility temperature exponent decreases as the gate length is conductance gds have been examined. Fig. 4(c) and (d)
reduced, which is attributed to the attenuation of the phonon shows the plots of gm versus Vgf and gds versus Vds ,
scattering mechanism with respect to the source/drain process- respectively, derived from the experimental data of
induced defect scattering mechanism [40]. Fig. 6(a) and (b) Figs. 4(a) and (b) and 5(a) and (b). The agreement between
KARATSORI et al.: ANALYTICAL COMPACT MODEL FOR LIGHTLY DOPED NANOSCALE UTBB SOI MOSFETs
Fig. 7. Experimental (symbols) and modeled (solid lines) transfer character-
istics in the linear representation of a silicon UTBB FD-SOI MOSFET with
W = 0.5 μm, L = 30 nm, tSi = 7 nm, and tox = 1.55 nm, measured at
drain voltage 1 V and different back-gate voltages Vgb with considering the
SH and VO effects (solid lines), without considering the SH and VO effects
(dashed lines), and without considering the SH effect (dashed-dotted lines).
Fig. 8. (a) and (b) Experimental (symbols) and modeled (solid lines) transfer
characteristics and (c) and (d) output characteristics of the UTBB FD-SOI
MOSFET with L = 240 nm, measured at different back-gate voltages Vgb .
Extracted mobility parameters: μo = 193 cm2 /Vs, θ1 = −0.2 V −1 , and
θ2 = 0.65 V −2 for Vgb = −2 V, μo = 200 cm2 /Vs, θ1 = −0.3 V−1 , and
θ2 = 0.55 V−2 for Vgb = 0 V, and μo = 225 cm2 /Vs, θ1 = −0.05 V−1 ,
and θ2 = 0.3 V−2 for Vgb = +2 V.
the experimental and modeled results is very good for
back-gate bias varying in the range of −3 to +3 V,
supporting the good accuracy of the compact model.
As shown in Fig. 7, for two typical back-gate voltages Vgb ,
the drain is significantly underestimated without considering
both the VO and SH effects or overestimated without con-
sidering the SH effect. These results indicate the necessity to
include both the SH and VO effects for good model accuracy.
The model has also been evaluated for the device with a
larger gate length (L = 240 nm). Comparison between the
model and experimental Ids –Vgf and the Ids –Vds characteristics
is shown in Fig. 8 for the typical values of Vgb = −2,
0, and +2 V, which demonstrate good model accuracy. The
model parameters are the same as for L = 30 nm, except for
φ f = 0.27 V. The lower value of φ f in the long-channel
device can be attributed either to the process-induced traps
near the source/drain regions or to the work function variability
of TiN caused by the different grain-orientation, the effect of
which becomes more pronounced in the short-channel device.
3123
The extracted mobility parameters are reported in Fig. 8. The
unified expressions for the charge and current (9) and (17),
respectively, can be used to derive analytical expressions for
the total charges and capacitances at the source, drain, and
gate terminals. This will be the subject of our future work.
VI. C ONCLUSION
In this paper, we present an analytical compact
drain-current model for lightly doped short-channel
UTBB FD-SOI MOSFETs with back-gate control, accounting
for small geometry effects, saturation velocity effects,
mobility degradation effects, QMEs, VO effects, and
SH effects. In summary, in addition to the mobility
parameters (μo , θ1 , and θ2 ) and threshold-voltage parameters
(φ f , Ac , and Bc ) extracted from the experimental data,
a limited number of fitting parameters (VE , λw , and r ) are
needed in the proposed drain-current compact model. Using
these parameters, the transfer and output characteristics
of UTBB FD-SOI MOSFETs can be predicted with good
accuracy for a wide range of back-gate biases covering the
inversion, depletion, and accumulation operation regimes. The
good level of accuracy makes the compact model suitable for
implementation in circuit simulation tools.
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Authors’ photographs and biographies not available at the time of publication.