 MOSFET physics (W1)

 Short channel effect (W2)

 Advanced Devices module:(W2-W5)
 Multi-Gate device structure
 FinFet and Gate all-around
 High-k materials + metal gate
 Strained technology
 Silicide process and RSD
 High mobility Channel
 Process integration (W6)
 Future device candidates (W6)
Gate

Si

Planar FinFET Gate-all-around

1
 Device Improvement
Ion=W/LG * Cox * (Vdd-Vtgm))2 * F(Rsd, )
 Cox
– High-k materials + metal gate
– Metal gate – gate depletion
 Gate Control (Vtgm, DIBL)
– Short channel control
– Minimize off-state D/S leakage
– Multi-gate
 Mobility enhancement
– Strained technology
 S/D parasitic resistance
– Abrupt-Raise LDD, Raise S/D, advanced anneal
– Metal Schottky S/D

2
2007 : 45 nm, First Product of High-k
 Power Consumption Issue
 Power consumption for the internet of things (IoTs) is very
crucial.
 Lowering the VDD ➔ Reduce the power consumption

 Vt : bounded to 0.3V
 Subthreshold leakage current
 Circuit noise immunity
 tolerable Leakage Current @ VG = 0
 Oxide Thickness :
 Short channel effect control
 Good subthreshold turn-off slope
 Solution: S.S. should be improved.
How to break through the physical limitation?
➲➲ Subthreshold Swing < 60 mV/decade
 High Tunneling Gate Current of
Ultra-Thin Oxide
 Gate leakage increases exponentially with decreasing thickness;
spec. for typical chip : 1A/cm2, loss of inversion charges

electrostatic integrity :

Ig
W m
I ds  Coxe s (Vgs  Vt  Vds )Vds
L 2

S. H. Lo, 1997 Sym. On VLSI

1997 Sym. On VLSI (technology node 0.25 mm, ~50Å )

5
 Off-State Leakage

 3 components limit
off-current in ultimate
device
Thermionic Emission
QM Tunneling
BTB Tunneling

Gate Length Scaling

6
C. Hu, IEDM-00,p.719
 Oxide Thinning
Density and performance are always the driving
forces of VLSI technology evolution
I D ~ Cox (VG  Vth ) 2

where Cox=(oxA)/tox; ox= 0 ;  =dielectric constant

Maximizing Cox max ID

Two approaches:
 Oxide thinning  Replace SiO2 with
 Direct tunneling leakage new material
 Defect sensitivity  High-
 Reliability Issue

7
Effective Oxide Thickness (EOT) requirement

k  k  k 𝐴
Cox  ox 0  hk 0 EOT  tox  ox thk 𝐶𝑜𝑥 = 𝑘ε𝑜
tox thk k hk 𝑡𝑜𝑥
For HfO 2 , k hk  20, kox  3.9, thk  5nm  EOT  1nm

8
 Gate Stack Scaling
 Gate leakage increases with SiO2 scaling -> running out
of atoms
 Alternate Gate Stack enables EOT scaling while
maintaining low gate leakage (orders of magnitude)

1000X
More difficult tunneling
through a thicker layer
of high-k oxide

9
 Tox_inv (or EOT) reduction by HK dielectric
SiON (tox= 7-10A) ꞉ called  SiON ꞉ Nitridized SiO2 . [N] usually < 10%,
Interfacial Layer IL Its physical properties are roughly the same
High K dielectric
(tHK = 20-30A） as SiO2, e.g. dielectric constant, barrier
n-Metal gate height.
Si substrate
(nWF)  Industry started to use SiON as gate
dielectric from ~90nm to 28nm LP.
 Ctotal ≡ εox/ Tox_inv (Ctotal is the measured
capacitance of the HK gate stack)
 Tox_inv is also known as EOT (equivalent oxide (SiO2) thickness), or
CET (capacitance equivalent thickness)
 Tox_inv= tox+ tHK(εox/ εHK) ,
for example ꞉ tox (for IL) = 9Å , tHK =25Å , εHK = 19.5 (=5εox)
Tox_inv = 9 + (25 * 1/5) =14Å
 HK material :
 High εHK, Reasonable tHK
 Interfacial SiON(IL) thickness 
 EOT (or Tox_inv) can be reduced to below ≈
18-20Å – the lower limit of SiON due to DT
leakage.
 IL must be scaled to continue the EOT scaling.
10
 DT leakage current reduce by HK gate stack
SiON(tox1= 14A)
SiON (tox= 9A) High K HK = 19.5 = 5ox

B (tHK = 25A）
p-Si sub n-Metal gate
 HK n-Metal gate (nWF)
(nWF)
p-Si substrate
For example ꞉
These two gate
Eox1
stacks have the
Eox
same Tox_inv
 B
 - Vox (EOT) of 14Å
HK
Si substrate
n-Metal gate
n-Metal gate (nWF)
(nWF)

VOX1 = EOX1 ∙ tOX1

 To compare the DT leakage currents, need to
calculate the integrals for the shaded regions:

11
 Poly-gate Depletion Effect
Poly-depletion effect & inversion layer quantization
lead to higher capacitance equivalent thickness
No solution!
Can be solved channel
electrons
by metal gate poly-Si
gate
poly
depletion
length 1.5nm (15A) gate
Tox total oxide
Ef

Si
substrate
highly doped p-type Si Source : Wong, IBM(2002)
poly-Si gate
metal Oxide
1 1 1 1
= + +
C Cox Cgate CSi

12
 Poly Depletion decrease Cinv and increases
Tox_inv (Toxe)

physical Inversion charge

thickness thickness (~ fixed)
Effective oxide
thickness Toxe = Tox + Wdpoly/3 + Tinv/3
εs/ εox=11.7/3.9=3 depletion width in poly

 Poly depletion is due to the limited dopant

concentration (≤ 1E20 cm-3) in the n+ or p+ poly.
 Cinv/Cacc , Toxe 
 It’s a serious performance/scaling issue.
 P+ poly is generally worse, as doping
concentration is less in p+ poly (due to B
segregation /penetration problem).

13
 Poly-depletion suppression with
Metal Gate
 Replacing poly-Si by Metal for electrode
– Suppresses the gate depletion effect
– Tinv scaling.

CPD Si Gate/SiO2
4A
Cox,eq.
11A ~18A
Csi
3A
Metal/HfO2
0A
2~3+6A ~11 -12A Poly-Si

3A High-K+ Interfacial layer

Si

14
14
 Why did we switch to metal gate (MG) ?
Because MG does not deplete!

Cmax= Caccumulation

 Coxe (= C_inv) ↑  ION ↑

 Poly gate has depletion effect, while metal gate has no
depletion.
 For metal gate, Coxe = Cmax = Cacc . Adopting metal
gate from 28nm and onward.
15
 Mobility Degradation
 All experimental values are significantly reduced from the
universal mobility, irrespective of the dielectric materials and
gate electrodes
 Peak mobility shifts dependent on the substrate concentration

Metal Poly-Si
gate gate

16
JJAP, 2002,p.4521
 Possible Causes

17
 High-K material options
K Gap(eV) CB offset(eV)
 Band gap ꞉ related to dielectric
Si 11.7 1.1
breakdown field, generally the
SiO2 3.9 9 3.2
higher the better.
Si3N4 7 5.3 2.4  CB offset = barrier height, directly
AI2O3 low 9 8.8 2.8(not ALD) related to tunneling leakage.
Ta2O5 22 4.4 0.35 low
SiON
TiO2 80 3.5 0 low
SrTiO3 2000 3.2 0 low High-K
ZrO2 25 5.8 1.5
HfO2 25 5.8 1.4
Si n-Metal gate
HfSiO4 low 11 6.5 1.8 (nWF)
La2O3 30 6 2.3
Y2O3 low 15 6 2.3
a-LaAIO3 30 5.6 1.8

 K value ꞉ dielectric constant, barrier height (or CB offset), Eg (band-gap), thermal

stability, compatibility with Si (without undesirable metal energy states close to the Si
mid-gap, or called “deep levels”) , reliability (dielectric wear out and charge trapping).
 HfO2 is widely chosen as the gate-last HK dielectric from 28nm to 5nm and likely to
3nm too).
 IBM camp chose La2O3 as the HK for 28nm gate-first. But there is no etching chemistry
to remove it, need ion sputtering. It was abandoned for gate-last process from 20nm.
18
 High-K Dielectrics Choices

 A trade-off between K-value (dielectric constant)

and band gap energy.
 HfO2, La2O3 (IBM 28nm gate-first), ZrO2(some
people used it together with HfO2), and Ta2O5 are
all reasonable choices in terms of K and band
gap energy.
 The gate leakage vs. EOT (Tox_inv) trade-off
plots are in qualitative agreement. (La2O3 has
lower leakage and is better than HfO2, but
process complexity ruled it out. )
19
 Leakage Current: Barrier Height
EC 1eV for low
tunneling
EC
EC
M
e- EF
EC Gate Dielectric Si
EV
h+ HfO2 :
 Higher Band gap
 EC 1eV

20
Wong, IBM J. R&D, Vol.46, 2002
 Stable Metal Oxides

21
Mrs-2002, p.198
Microstructure: crystalline vs. amorphous
Amorphous Crystalline

M Ig
Poly-SiO2 interface
O Gate Dielectric
Si-SiO2 interface
S
Interfacial
dangling bonds

 Enhanced leakage or diffusion through grain

boundaries

22
 HK Dielectric Ta2O5: Thermal Stability

 Thermal stability of Ta2O5 is not good (anneal temp. need < 650-700°C).
 the abnormal increase in capacitance and leakage
 Ta2O5 property change (i.e. dielectric integrity degradation).
 Gate-last HKMG process can help to reduce the thermal budget for the
HK material.
 HK with higher thermal stability is
better/desired. HfO2 can withstand
RTA at about 1100°C for <1 sec.

23
 HK Dielectric HfO2: Thermal Stability
Annealed at T for 30s

 Leakage current of HfO2 does not increase after 800-900°C annealing

 Good thermal stability.
 HfO2 is thermally stable enough for HK-first gate-last process
 CET increase after RTA anneal may be due to IL (7-10A of SiON) thickness
increase.
 HK-last gate-last (current baseline for all sub-10nm technologies) is less
24 demanding in terms of thermal stability.
Considerations for High-k Gate Dielectrics
 EOT<1 nm
 Barrier height and permittivity (k value)
– Leakage
 Thermal Stability in direct contact with Si
– Stable up to 1000°C
 Microstructure and interfacial defects (Qf, Dit)
– Amorphous with low Dit is preferred
 Available deposition tools
– MOCVD, ALD
 Integration process
 Acceptable reliability

25
 TEM Pictures
 Dark Region :
HfO2
 Bright Region :
HfO2 SiOx or Silicate
SiO2  EDS :
53Å composition
27Å Diffraction Pattern
Si

HfO2 by PVD + 600C Annealing

26
 I-V Characteristic

BD
Ig

FN
DT

Vg
27 E.P.Gusev, IEDM-01
 Interfacial Layer
600C O2 annealing Total capacitance of two
45.5Å capacitors in series

Poly-Si CT1  Chigh

1
k  C 1
int

equivalent oxide thickness

 ox
EOT  tox  thigh k
 high k
Interfacial layer will limit the
Si minimum achievable gate
dielectric thickness

28
 C-V Characteristics
 EOT can be determined by capacitance at AC
 Dit , Qf can be also determined by C-V
 Hysteresis (two-way sweep) should be smaller than 10 mV

29 IEDM-01
 Threshold Voltage Shift
Vt shift is strongly believed to be related to the
charge in high-k material

Negative
charge
Positive for nFET
charge
for pFET

30 IEDM-01,p.451
 Mobility Degradation
compared to that with SiO2, a transistor with high-k gate
dielectrics suffers from carrier mobility degradation

Id
Process improved

31 IEDM-01,p.451 vg
 Why do we still need a thin SiON(IL)?
SiON(tox= 7-10A)

High K dielectric
(tHK = 20-30A)
Si substrate
n-Metal
Dit

High K dielectric
(tHK = 20-30A)
Si substrate n-Metal
Dit

 HK directly deposited on Si (w/o IL) has high interface trap Dit which acts
as Coulombic scattering center and thus degrade mobility.
 IL is a key barrier for EOT scaling꞉
 Keep the Si/SiON interface for maintain the
surface mobility.
 IL limits the Tox_inv (EOT) scaling, need much efforts
32 to reduce its thickness.
 Why different WF for n-and p-FET ?

n+ poly

p+ poly

 Need both low VT values (for high

ION) and reasonably high Na(to
control SCE).
 For bulk CMOS, it is desirable to
have nWF as n+ poly (4.05eV), and
pWF as p+ poly (5.15eV).
 Vt= Vfb+ 2 ϕFB + QSUB/ Cox For nFET
with n+ poly on p-sub

33
Suitable metal-gate WF for n-and p-FET
“Target window” 0.3V < Vt < 0.5V, when Tox ≈ 2nm and the
high NSUB (>1018) is good for SCE control.
If nFET with P+ poly on p-sub, Vt > 1V is too high!
nFET need n+ metal-gate with “n+ poly WF”.(i.e. 4.05eV)
pFET need p+ metal-gate with “p+ poly WF”. (i.e. 5.15eV).

34
 Workfunction of metals
Bulk CMOS Target:
N-WF from CB = 4.05eV
P-WF from VB = 5.15eV

Match of WF value is the

first step
Mo: 5.0eV

 Free of contamination concern, compatibility with HK dielectric/ SiON, temperature

stability, reliability... are also very critical.
 Though the WF of some metals are close to target (e.g. Al n-quarter-gap, Ni, Mo
p+ poly), they are too chemically reactive to be used as gate electrode.
 Metal alloys and metal nitride (e.g. TiN or TaN). Chemically stable and compatible
with CMOS flows.
 For metal nitride, the amount of [N] and annealing condition can affect the WF (by as
35 much as 100-200mV).
 TiN as Work Function Metal
–thickness and [N] dependencies

 TiN can achieve_pWF of 4.71 to 4.82eV, not far from

the p-quarter-gap target of 4.87eV for p-FinFET.
 TiN is thermally stable and commonly used in CMOS
flows.
 The processing details (thickness, [N], and deposition
method) can vary the work function values.
36
 Review and Summary
 Why HK dielectrics and
metal gate pWF Metal gate

 Reduce Tox_inv High K dielectric

(20-30A）
 Gate leakage
SiON IL (7-10A)
 Gate depletion effect
 HK material choose?
 Dielectric constant, barrier height (or CB
offset), Eg (band-gap), thermal stability
 Why still keep a thin SiON interface layer (IL) ?
 Why dual-WF metal gates ?
 nFET need n+ metal-gate
 pFET need p+ metal-gate
37