VLSI Design I

The MOSFET model

Wow !
Are device models as
nice as Cindy ?

Today’s handouts:
(1) Lecture Slides

MicroLab, VLSI-2 (1/24)

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 Let’s build a MOSFET
There are lots of different recipes to choose from.
Like most things in life, you get what you pay for:
the ability to have good bipolar devices, radiation
hardness, reduced latch-up and substrate noise, …
are all extra cost options. We’ll consider a general
process: bulk CMOS with a p-type substrate:

500um slice of a silicon ingot that has been

doped with an acceptor (typically boron) to
Use <100> surface increase the concentration of holes to 1014/cm3
to minimize surface - 1018 /cm3.
charge

p-type

Back is metallized to provide

a good ground connection.
Good for n-channel fets, but p-channel
fets will need a n-type “well” (or tub) to
live in!
MicroLab, VLSI-2 (2/24)

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 Next, a “thick” (0.4um) layer of silicon dioxide, called
field oxide, is formed on the surface by oxidation in wet
oxygen. This is then etched to expose surface where we
want to make a mosfet:

Now grow a “thin” (0.01um = 100 Å) layer of silicon

dioxide, called gate oxide, on the surface by exposing the
wafer to dry oxygen.

The gate oxide needs to be of high quality: uniform

thickness, no defects! The thinner the gate oxide, the
more oomph the fet will have (we’ll see why soon) but the
harder it is to make it defect free.

MicroLab, VLSI-2 (3/24)

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 On top of the thin oxide a 0.7um thick layer of
polycrystalline silicon, called polysilicon or poly for
short, is deposited by CVD. The poly layer is patterned
and plasma etched (thin ox not covered by poly is etched
away too!) exposing the surface where the source and
drain junctions will be formed:

gate oxide poly wires field oxide

(only under poly)

exposed surface for source

and drain junctions p

Poly has a high sheet resistance (25 ohms/square) which

can be reduced by adding a layer of a silicided refractory
metal such titanium (TiSi2), tantalum (TaSi2) or
molybdenum (MoSi2). These have sheet resistances of 1,
3 or 5 ohms per square, respectively. This is great for
memory structures that have lots of poly wiring.

MicroLab, VLSI-2 (4/24)

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 The entire surface is doped, either by diffusion or ion
implantation, with phosphorus (an electron donor) which
creates two n-type regions in the substrate. The
phosphorus also penetrates the poly reducing its resistance
and affecting the nfet’s threshold.

diffusions are “self-aligned”

with poly

n+ n+

n+ wires: 20-30 ohms/sq. p

Finally an intermediate oxide layer is grown and then

reflowed to flatten its surface. Holes are etched in the
oxide (where contacts to poly/diff are wanted) and
alumimum deposited, patterned and etched.

metal wires (0.08 ohms/square)

???

diff contact (0.25 - 10 ohms) n- channel MOS

field effect transistor!
MicroLab, VLSI-2 (5/24)

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 NFET Operation
Picture shows configuration when Vgs < Vto
S G D

Ids = 0

n+ n+

mobile holes, mobile electrons,

fixed negative ions B fixed positive ions
(n+ means heavily
depletion layer doped with donors,
no mobile carriers, doesn’t imply
but fixed negative ions positive charge!)
(slight intrusion into n+,
but mostly in p area) Terminal with higher
G voltage is labelled D,
Other symbols: the other is labelled S
so Ids >= 0.

S D

B almost always ground

MicroLab, VLSI-2 (6/24)

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 FET = field effect transistor
The four terminals of a fet (gate, source, drain and bulk)
connect to conducting surfaces that generate a complicated
set of electric fields in the channel region which depend on
the relative voltages of each terminal.
Picture shows configuration
when Vgb > Vto gate

inversion
happens here

Eh Ev
source drain

bulk

INVERSION: CONDUCTION:
A sufficiently stong vertical If a channel exists, a
field will attract enough horizontal field will cause
electrons to the surface to a drift current from the
create a conducting n-type channel drain to the source.
between the source and drain. Expect Ids proportional
to Vds*(W/L)?

MicroLab, VLSI-2 (7/24)

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 Threshold voltage
The gate voltage required to form the channel is called the
threshold voltage. Many factors affect the gate-source
voltage at which the channel becomes conductive. Threshold
voltage for source-bulk voltage zero:

VTO = V t − ms + Vfb

6474 8 6 474 8
Q Q ε ox
VTO = 2 φ b + b + φ ms − fc
{ C C ox
ox t ox

kT  NDN A 
0.7V for n-channel 2 kT ln NA  ln 2 
-0.7V for p-channel q  n i  q  ni 
2 ε si qN A 2 φ b

MicroLab, VLSI-2 (8/24)

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 Body effect (second order)
As Vsb increases, the depth of the depletion region
increases, exposing more of the fixed acceptor (i.e.
negative) ions in the substrate.
Thus the second term in the threshold voltage equation on
the previous slide increases from

2 ε siqNA 2 Φ b
to
2 ε siqNA (Vsb + 2 Φ b )

the threshold voltage of the n-channel transistor is now:

Vtn = Vtn0 + γ ( Vsb + 2 Φ b − 2 Φb )

2ε siqN A
γ=
C ox

As we’ll see, this effect

T2
comes into play in
series-connected fets Vsb>0
where only one of the T1
fets will have Vsb = 0
and the other fets will Vt2> Vt1 Vsb=0
have Vsb > 0 and a
higher threshold voltage.
MicroLab, VLSI-2 (9/24)

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 Basic DC equations

MOS transistors have 3 regions of operation:

w cutoff region (subthreshold)
w linear region (triode region)
w saturated region (active region)
polysilicon gate
SiO2
source diffusion
drain diffusion

Cutoff or subthreshold region:

Vgs <=Vt
Ids = 0
There is still a small current described in the
second order effects (weak inversion). Important to
model for analog circuits: I ds ∝ Vds
MicroLab, VLSI-2 (10/24)

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 “Linear” operating region
Vs Vgs > Vt 0 < Vds < Vdsat

Ids

Larger Vgs creates Larger Vds increases drift current but

deeper channel which also reduces vertical field component
increases Ids which in turn makes channel less deep.
Channel will pinch-off, when
channel length is mobility Vds = Vgs - Vt = Vdsat
almost always min (un > up)
allowable intrinsic transconductance k=µCox

2 
W µ ε ox 
I ds =
L t ox 
(
 Vgs − V t Vds − ) Vds
2 


max value at Vds = Vdsat,

but then channel is only linear when Vds is small,
pinched off (see next slide) otherwise parabolic
MicroLab, VLSI-2 (11/24)

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 Saturated operating region
Vs Vgs > Vt Vdsat < Vds

Ids

Voltage at channel end Electrons arriving from source are

remains essentially injected into drain depletion region and
constant at Vdsat so accelerated towards drain by field
drift current also remains proportional to Vds - Vdsat usually
constant: device is in reaching the drift velocity limit.
saturation .

W µ ε ox
( )
2
I ds ( sat ) = Vgs − Vt
2 L t ox

this is just Ids from previous slide

evaluated at Vds = Vdsat

MicroLab, VLSI-2 (12/24)

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 Channel-length modulation
(second order)
Vs Vgs > Vt Vdsat < Vds

Ids

L’ = L - dL
dL

This looks just like a As Vds increases,

fet with a channel length dL get larger
of L’ < L. Shorter L’ implies
greater Ids...

As Vds increases the effective channel length gets

shorter so Ids(sat) increases. dL is proportional to
Vds − Vdsat but most people approximate channel
length modulation as a linear effect:
W µ ε ox
( ) ( 1 + λV
2
I ds ( sat ) = Vgs − Vt ds )
2 L t ox
MicroLab, VLSI-2 (13/24)

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 NFET Ids curves
“Put it together and what have you got?”

plot of Ids vs. Vds for Vgs = 0 ,1, 2, 3, 4 and 5V

Can you find the following in the plot?

Ids vs. Vds when Vgs = 0V
Ids vs. Vds when Vgs = 5V
value of Vt
value of Vdsat
evidence of body effect
evidence of channel length modulation

MicroLab, VLSI-2 (14/24)

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 SPICE Models
There are different models used in circuit simulators:
w level 1 is our simple model including the most
important second order effects described
w level 2 model is based on device physics
w level 3 is a semi-empirical model allowing to match
equations to the real circuit

w summary of the main SPICE DC parameters used in

all three models at the end of this chapter

.
M1 4 3 5 0 nfet W=1u L=0.5u AS=1p AD=1p PS=3u PD=3u
.
.
.MODEL nfet NMOS
+TOX=1E-8
+CGB0=345p CGS0=138p CGD0=138p
+CJ=775u CJSW=344p MJ=0.35 MJSW=0.26 PB=0.75
+. . . .
.
.
MicroLab, VLSI-2 (15/24)

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 MOSFET Capacitance Estimation
the dynamic response of MOS systems strongly
depends on the parasitic capacitances associated with
the MOS device. The total load capacitance on the
output of a CMOS gate is the sum of:
w gate capacitance (of other inputs connected to out)
w diffusion capacitance (of drain/source regions)
w routing capacitances (output to other inputs)

Cgd drain
Cdb
gate substrate

Cgs Csb
source
gate
Cgb

Cgs Cgb Cgd tox

channel
source drain
depletion
layer
Csb Cdb

substrate
MicroLab, VLSI-2 (16/24)

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 MOSFET gate capacitances
Cg = Cgd + Cgs + Cgb
Oxide-related capacitances come in two forms:

w overlap capacitance (extrinsic) since gate slightly

overhangs diffusions and bulk:
for both Cgs and Cgd amount of overlap

C(overlap) = W LD Cox for SPICE

for Cgb Cgs = W CGS0

Cgd = W CGD0
C(overlap) = 2L CGB0 Cgb = 2L CGB0

w channel-charge related capacitances (intrinsic):

cut-off: Cgb = Cox W L

Cgs = Cgd = 0
shielded by channel
linear: Cgb = 0
Cgs = Cgd = 0.5 Cox W L
equally shared between S and D
note capacitive coupling of gate and drain/source
saturation: Cgb = 0 channel pinched off
Cgd = 0 channel shortened
Cgs = 0.67 Cox W L
MicroLab, VLSI-2 (17/24)

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 MOSFET diffusion capacitances
Junction capacitances Cdb and Csb are a function of the
applied terminal voltages and diffusion dimensions:

source/drain diffusion
xj

channel

sidewall faces bottom junction faces sidewalls face p+

channel p-type substrate channel stop
zero-bias C/unit area of bottom junction zero-bias C/unit length of
area of diffusion sidewall junction
perimeter of diffusion
CjA C jswP
C diff = Mj + Mjsw
negative for  Vj   Vj 
reverse biased  1 −   1 −  grading coeff.
 Vb   Vb 
built-in junction
potential junction voltage
grading coeff.

MicroLab, VLSI-2 (18/24)

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 P-channel MOSFETs
S G D

p+ p+

threshold voltage is
negative since we need
attract holes to form
inversion layer
n
p
PFET is built inside its
B own “substrate”: a n-type
well or tub diffused into
p-type bulk substrate.
Don’t forget well contacts!

Other symbols:
G Terminal with lower
voltage is labelled D,
the other is labelled S

S D

off: Vgs > Vt B n-well always connected

lin: Vgs>Vt, Vds>Vgs-Vt to Vdd to keep pn
sat: Vgs>Vt, Vds<Vgs-Vt junction back-biased
MicroLab, VLSI-2 (19/24)

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 Depletion-mode MOSFETs
S G D

n+ n+

channel doped with donors

B to give negative threshold
voltage, i.e., depletion fets
are always on.

This mosfet is always conducting but, like ordinary

enhancement fets, it will conduct more current as Vgs
increases. One can build logic circuits with only n-channel
devices (NMOS): enhancement fets for pulldowns and
depletion fets as static pullups. Since NMOS logic
dissipates DC power it’s been largely replaced by CMOS.

MicroLab, VLSI-2 (20/24)

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 Coming Up...
Next topic…
Static characteristics of MOS inverters: input
and output voltages, noise margins, power
dissipation.

Readings for next time…

Weste:
u 5.3.9 thru 5.4.1
u sections 2 thru 2.23 except 2.2.2.4 - 2.2.2.7 (fet
models),
u 3 thru 3.2.2 (process technology) and

u 4.3 through 4.3.4 (capacitances)

CBT:
Study the chip fabrication text of the university of
Manchester at the MicroLab VLSI course web link.

MicroLab, VLSI-2 (21/24)

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 Useful Constants

sym value units description

ε0 8.8542E-12 F/m permittivity
εox 3.9 ε0 F/m permittivity of SiO2
εSi 11.7 ε0 F/m permittivity of silicon
VT 25.8 mV kT/q (@300°K)
q 1.6022E-19 C charge of electron
k 1.381E-23 J/°K Boltzmann‘s constant
ni 1.45E10 cm-3 intrinsic carrier concentration

MicroLab, VLSI-2 (22/24)

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 Alcatel 0,5um Process Parameters
sym param nmos pmos units description
Vt0 VTO 0.69 -0.61 V threshold voltage
tox TOX 1E-8 1E-8 m thin oxide thickness
NA NSUB 4E16 4E16 cm-3 substrate doping density
µ U0 588,4 148.6 cm2/Vs charge mobility
LD LD 2.35E-7 3E-7 m lateral diffusion
k KP A/V2 intrinsic transconduct.
γ GAMMA V0.5 bulk threshold param.
Cox COX F/m2 oxide capacitance
λ V-1 channel length modulat.
sym param nmos pmos units description
Cgb0 CGB0 3.45E-10 F/m overlapping cap per 2L
Cgs0 CGS0 1.38E-10 F/m overlapping cap per W
Cgd0 CGD0 1.38E-10 F/m overlapping cap per W
Cj CJ 7.75E-4 8.15E-4 F/m2 zero-bias cap / unit A
Cjsw CJSW 3.44E-10 3.54E-10 F/m zero-bias cap per unit P
Mj MJ 0.35 0.36 grading coeff for bottom
Mjsw MJSW 0.26 0.27 grading coeff sidewall
Vb PB 0.75 0.78 V built-in voltage
MicroLab, VLSI-2 (23/24)

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 Exercises: VLSI-2
Ex vlsi2.1 (difficulty: easy): Calculate the missing
parameters on the previous transparency like intrinsic
transcunductance k, bulk threshold parameter γ and
oxide capacitance Cox of an nfet (Alatel 0.5µm process)
Result: kn=203µA/V2, kp=51.3µA/V2, γ=0.193V0.5,
Cox=3.45E-7 F/cm2 (see Weste pp48ff)
Ex vlsi2.2 (difficulty: easy): Calculate the threshold
voltage shift due to the body effect of an nfet at Vsb =
2.5V (Alcatel 0.5µm process)
Result: dVtn = 0.311V (see Weste pp55)
Ex vlsi2.3 (difficulty: easy): Calculate the
transconductance βn of an nfet (Alatel 0.5µm process),
W=1 µm, L= 0.5 µm
Result: βn=406 µΑ/V2 (see Weste pp53)
Ex vlsi2.4 (difficulty: easy): Calculate the capacitances of
an nfet with Vsb=Vdb=3V, W=1µm, L=0.5µm,
A=1µm2, P=3µm (Alatel 0.5µm process)
Result: Cgate=2.35fF, Cdrain=Csource=1.12fF (see Weste
pp183-191)

Weste pp99: 2.10: Have a look at ex 8, 9

MicroLab, VLSI-2 (24/24)

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