VLSI Systems Design

Microelectronic Technologies

Overview

microelectronic technologies, ASIC, FPGA, µC

Goal: You are familiar with the microelectronic

technologies, and know their advantages and features.

MicroLab, VLSI-8 (1/20)

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 Microelectronic Technologies

What is microelectronic ?

Has a microelectronic design engineer only to have
good knowledge about silicon, layout, etc. ?

application specific
integrated circuit
macro cell full custon
standard cell
gate array microprocessors
PIC, COP
FPGA RISC
uController
PAL CPLD signal processor

field programmable logic

MicroLab, VLSI-8 (2/20)

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 #11
Gate Array Technology #

prefabricated wafers

I/O stages predefined

regular array of fets and interconnection channels

interconnection defines functionality

features

size: 100 - 1M gates

short turn around time

cheap at medium quantities

unsuitable for regular structures like RAM, PLA, ALU

MicroLab, VLSI-8 (3/20)

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 Gate Array Technology #2

3 cells of a gate array are illustrated

1 cell corresponds to a 2 input nand gate

MicroLab, VLSI-8 (4/20)

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 Sea--of
Sea of--Gate Technology

prefabricated wafers

I/O stages predefined

regular array of fets,
fets, no reserved interconnection
channels

interconnection defines functionality

features

size: 100 - 1M gates

short turn around time

cheap at medium quantities

regular structures like RAM, PLA, ALU can be used

MicroLab, VLSI-8 (5/20)

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 SOG Example
nwell contacts
INV NOR2

GND

3 nfets
2 small, 1 large horizontal
mosfets with wiring tracks
common gate in metal-
metal-1
3 pfets

gate isolation VDD

mosfets
unused horizontal
and vertical tracks
used for wiring
gates together.
Better granularity
if main routing
channels run
vertically.

GND
substrate
contacts
vertical wiring tracks
in metal-
metal-1 or metal-
metal-2
MicroLab, VLSI-8 (6/20)

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 Standard Cell Technology

complete fabrication process

predefined library of base functions

modular similar to TTL families

features

chip size limits complexity

long turn around time

cheap at high quantities

standardized cell height

unsuitable for regular structures

more flexible and compact (1:4) than gate array

MicroLab, VLSI-8 (7/20)

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 Standard Cell Example
Create a library of pre-
pre-layed-
layed-out cells, e.g,, boolean gates,
registers, muxes,
muxes, adders, I/O pads, … A data sheet for
each cell describes the cell’s function, area, power,
propagation delay, output rise/fall time as function of
load, etc.

Quiz: what‘s the

cells function

It’s just like designing with board-

board-level components.
CAD tools help with placing the cells to minimize area
and to meet timing constraints (perhaps directed by a
floorplan created by the user); routers make the
appropriate connections between the cells.
MicroLab, VLSI-8 (8/20)

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 Full Custom Technology

complete fabrication process

total flexibility, only limited by layout rules

manual design

features

chip size limits complexity

long design and fabrication time

efficient use of silicon area

cheap only at highest quantities (ex. uP,
uP, memories, ...)

MicroLab, VLSI-8 (9/20)

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 Macrocell Technology #1

complete fabrication process

combines semi-
semi- and full custom technologies

predefined library of base functions

generators for regular structures

features

chip size limits complexity

short design, long fabrication time

cheap at high quantities

high flexibility,
compact layouts
PLA
macro cell
RAM

MicroLab, VLSI-8 (10/20)

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 Macrocell Technology #2
2-dim array of standard cell block
full custom block

full custom block

MicroLab, VLSI-8 (11/20)

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 FPGA Technology #1

field programmable device

no fabrication needed for customizing

predefined logic blocks

unsuitable for regular structures

features

size: up to 1‘000’000 logic gates (see Virtex from Xilinx)
Xilinx)

large silicon area necessary (72 million fets,
fets, 10x Pentium2)

short design and customize time

cheap for small quantities

compared to ASICs,
ASICs, FPGAs have a reduced clock speed

circuit configuration downloadable (RAM or PROM)

MicroLab, VLSI-8 (12/20)

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 FPGA Technology #2
configurable
logic block (CLB)
I/O buffers
switching
matrix
I/O buffers

I/O buffers
routing
channels
I/O buffers

configuration
- mask programmable
- one time programmable
- downloading of configuration from host into internal RAM
- downloading of configuration from on board serial ROM

MicroLab, VLSI-8 (13/20)

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JMM v1.2
CLB from Xilinx serie XC5200

C1...C4

H1 Din/H2 SR/H0 EC

G4
Din Bypass
G3 Logic F’ S/R
Function Control SD YQ
G’
G2 of D Q
G1...G4 H’

G1

Logic
Function
G’ EC
of
F’,G’ H’ H’ RD
1
and H1 Y
F4
Din
Bypass
F3 Logic F’ S/R
Function G’ Control SD XQ
F2 of H’ D Q
G1...G4

F1

K (Clock)
EC
FPGA Technology #3

RD
1
H’ X

MicroLab, VLSI-8 (14/20)

F’
 FPGA Technology #4

Switching matrix with CLBs

CLB CLB CLB

PSM PSM

CLB CLB CLB

PSM PSM

CLB CLB CLB

MicroLab, VLSI-8 (15/20)

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 uC Technology

field programmable device

no fabrication needed for customizing

simple C software compilers

software vs.
vs. hardware solutions

features

4 or 8 bit CPU, size: 512 bytes or more

down to 8 pins

AD, usart,
usart, timer, etc. included

very slow compared to hardware solutions

cheap (<$2)

PIC

36 mm
MicroLab, VLSI-8 (16/20)

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 How to select a technology

Selection arguments
- cost
- speed
- size
- time to market

cost

units ASIC
FPGA
NRE
units
design
design

break even quantity

MicroLab, VLSI-8 (17/20)

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 Coming Up...
Next topic…
Hardware description language VHDL, top-
top-down
design.

Readings for next time…

Weste: Chapter 6.3 - 6.3.7 (recommended)
Xilinx article: The total cost of ownership

MicroLab, VLSI-8 (18/20)

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 VLSI--8
Exercises: VLSI #1

Ex vlsi08.1 (difficulty: easy): Calculate the breakeven

point between an FPGA and ASIC design. Assume a
design time of 6 months and an additional back-
back-end
design time of 1 month for the ASIC. The NRE
costs of the ASIC are 75kEuro, the cost per unit
are 150Euro for the FPGA and 3 Euro for the ASIC.
The cost of 1 engineer per month are 10kEuro.
Result: breakeven at 578

MicroLab, VLSI-8 (19/20)

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 VLSI--8
Exercises: VLSI #2

Ex vlsi08.2 (difficulty: medium): Calculate the

breakeven point between an FPGA and ASIC design.
Assume the design costs from exercise vlsi08.2
and a fabrication time of 3 months for the ASIC.
The revenue per sold system at a product lifetime
of 4 years is 600Euro without taking into account
the FPGA/ASIC chip costs. Use the triangular
time-
time-to-
to-market model from Synopsys (see Xilinx
article “The total cost of ownership).
Result: breakeven at 14068 FPGA solutions
maximum available
units/time revenue

time
delayed market d
introduction L
product life

MicroLab, VLSI-8 (20/20)

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