MOSFET – Scaling, Short Channel

Effects, Leakage, Reliability

Dr. Rajan Pandey
Associate Professor, SENSE
A schematic view of two categories of tunneling problems

A particle (e-) starts from the unbound

state on the left in region I where it is
free to move classically (i.e., E ≥ V(r))
and tunnels through a classically
“forbidden” region (II) into a classically
allowed region (III).

Example: tunneling through gate oxide or direct tunneling in a MOSFET

The particle is initially in “bound region” and

tunnels through a “forbidden” region (II) into
a classically allowed region (III).

Example: band-to-band tunneling or

gate induced drain leakage (GIDL) in
a MOSFET.
A generic description of the tunneling problem

Particles are incident from the left

with an energy E. A certain fraction
of the particle current is reflected
and the rest is transmitted.

A wave-packet localized in space is

incident on the barrier. The time-
evolution of the wave-packet is
shown.
 Tunneling through a Rectangular Potential Barrier

The solution in region II represents a decaying exponential if E ≤ V0, and an oscillatory function otherwise.

We now use the fact that the

wave function and its derivative
are continuous at the boundaries.
This gives us the following conditions:

Eliminating C and D from these equations,

we obtain the following results:
 Tunneling through a Rectangular Potential Barrier
This gives us the following values for the
tunneling probability and reflection probability:

and the reflection coefficient is

In a classical case, there should be no reflection when

E > V0. However, in the quantum problem, even
particles with E > V0 can be reflected back with a non-
zero probability. If E = V0, we have

we see that the barrier becomes completely transparent

(R = 0, T = 1) when

This behavior represents a resonance phenomenon which

does not occur in classical physics for particles but does
occur in wave optics.
Tunneling through a Rectangular Potential Barrier
Let us now consider the case where E < V0 and where the
particle cannot transmit through region II classically. In
region II the wave-vector a is purely imaginary. We define
a variable

The reflection coefficient

The tunneling coefficient

The tunneling probability does not go to zero when E becomes less than Vo. Note that as
the barrier height or width increases the tunneling probability decreases.
 Tunneling through a Rectangular Potential Barrier
The analytical expressions developed for the tunneling probability are possible only
for simple square barriers. For barriers with arbitrary spatial dependence, one has
to use approximation schemes or numerical techniques. One such scheme is the
WKB (Wentzel-Kramers-Brillouin) method, which provides a useful analytical result.

Consider the tunneling probability through a barrier of

width a when the penetration distance d is small
compared to a. This gives a value

The pre-factor to the exponential term is

close to unity (it ranges in value from 1 to 4)
and the tunneling is dominated by the
exponential factor.
 Tunneling through an arbitrary shaped Potential Barrier
Consider the tunneling through a smoothly varying
potential We can divide the potential into hatched
regions. The total tunneling probability through the
barrier can be taken as the product of the tunneling
probability T, through each hatched region. This is valid
only if the potential is smoothly varying, (with the
prefactor taken as unity) we have

Now increasing the number of subdivisions while ensuring

di << xi, (note that when E > V(xi),Ti ~ 1), we get

where x1 and x2 are points where E = V(x).

 Tunneling through Potential Barrier: special cases
Two special cases of barriers are the triangular and trapezoidal barriers. We can consider these
barriers to be formed when an electric field is applied across the square barrier. If the applied
electric field is E, the tunneling probability becomes

Barrier thickness
dependence
Gate Tunneling in a MOSFET

e  ik i n x
T e  ik o u t x

Transmission coefficient T is
determined by outgoing plane wave
magnitude
 Gate Tunneling Currents

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 7, JULY 2001

 Need of High k Materials Electrode
• Significantly Lowers Gate Leakage  Chips consume less power.
• Allows Equivalent Oxide Thickness (EOT) Scaling < 1nm
• Shrinking of Transistor Dimensions can continue…

Electrode Tunneling from gate to channel High k

is high because Gate oxide is
only four mono layers thick!
SiO2
 HK A
silicon C HK 
d HK
silicon
 Ox A
C Ox 
d Ox

It is convenient to define an ‘electrical thickness’ of the new

gate oxide in terms of its equivalent silicon dioxide
thickness or ‘equivalent oxide thickness’ (EOT).
 High-k dielectric on Si

High-K oxide materials with dielectric constants and

silicon substrate compatibility

Gate oxide tunneling currents for three

oxide types at different oxide thicknesses.
 Gate Tunneling Leakage Current

• For SiO2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor.
• HfO2 has several orders lower leakage for the same EOT.
 Replacing SiO2 with HfO2---High-k Dielectric

(W. Tsai et al., IEDM’03)

• HfO2 has a relative dielectric constant (k) of 24, six times larger than that of SiO2. A 6 nm thick HfO2
film is equivalent to 1 nm thick SiO2 in the sense that both films produce the same Cox.

• We say that this HfO2 film has an equivalent oxide thickness or EOT of 1 nm. However, the HfO2 film
presents a much thicker (albeit lower) tunneling barrier to the electrons and holes. The consequence
is that the leakage current through HfO2 is several orders of magnitude smaller than that through SiO2.
• Besides Toxe or EOT, the poly-Si gate depletion layer thickness also needs to be minimized. Metal is a
much better gate material in this respect. NFET and PFET gates may require two different metals (with
metal work functions close to those of N+ and P+ poly-Si) in order to achieve the optimal Vt.
Work Function Engineering through defects at HK/M interface
|| means interface
Ov means O vacancy
Oi means O interstitial

O vacancy at the interface gives nFET-like WF, O interstitial in interior TiN gives pFET-like WF.

Pandey et al., J. Appl. Phys. 114, 034505 (2013)

Work Function Engineering through HK/M Interface Stoichiometry
The vacuum work function of (100) TiN = 3.70 eV. Interface Engineering
(111) TiN vacuum work functions of Ti-terminated surface = 3.60 eV, and N-terminated surface = 4.46 eV.
The process conditions, such
as pressure, nitrogen flow, and
bias power during deposition,
can modulate the stoichiometry
of TiN film at the HK interface.

~ 800 mV ‘+’
Vt shift for
p-FET with
N-rich HK/TiN

The theoretical prediction was

confirmed by the experiments,
demonstrating over 700 meV
Ti-rich interface  nFET-like WF, N-rich interface  pFET-like WF
Pandey et al., J. Appl. Phys. 114, 034505 (2013)
modulation in the EWF!
 Challenges of High-K Technology
No High-k degradation
High-k dielectric: Fixed IL
y charge
Gate tunneling Good news  Better control over channel
HK
with larger equivalent oxide thickness.
+
Substrate

 Significantly lower gate leakage

High-k degradation model
 Devices consume less power.
Oxide

Poly  Allows to continue scaling! Metal + hardware

Channel Bad news  Large number of bulk & interface

+
-
Channel Remote Coulomb Scattering
Increased gate tunneling traps  mobility degradation &
as oxide became only four reliability challenges (Vt shifts).
mono layers thick (10 - 12Å).

• The difficulties of high-k dielectrics:

• Chemical reactions between HK and the silicon substrate and gate.
• Lower surface mobility than the Si/SiO2 system and more oxide charge.
• Too low a Vt for P-MOSFET (as if there is positive charge in the high-k dielectric).
• Long-term reliability.
• These problems are minimized by inserting a thin SiO2 interfacial layer between
Si-substrate and high-k film. 18
 Reliability

Positive Bias Temperature

Instability (PBTI) causes Vt shift in
N-MOSFETs.
Root cause: Oxygen vacancies in
high-k oxide.

Negative Bias Temperature

Instability (NBTI) causes Vt
shift in P-MOSFETs.
Stress Induced
Root cause: Defects in interfacial
Leakage Current
SiO2 layer and at Si/SiO2 interface.
(SILC)
These could be Si-Si dimer (Ov) or
Si dangling bond at the interface,
Direct Current IV (DCIV) or N in IL, IL/HK interface, HK.
PBTI improvement  N doping in HK, NBTI improvement  H passivation in Si/SiO2
Reliability
Trap Energies of Different Types of Oxygen Vacancies
Positive Bias Temperature Instability (PBTI) for nMOSFET

22 pages 5A.2.1 - 5A.2.7, 2013

IEEE International Reliability Physics Symposium (IRPS),
Memory element based on HK traps C. Kothandaraman et al. IRPS 2015, pages MY.2.1 – MY.2.4

Band diagram
representation

Programming characteristics
of a group of devices

• The device is programmed by the application of a +2Vgs, 1ms pulse, t0->

t1, with Vds =1.5V, resulting in positive Vt shift, Δvt, in excess of 100mV,
due to electron trapping.
• The device is erased by the reversal of Vgs to -2V, t1->t2, resulting in the
de-trapping of the carriers thus returning the FET close to its native state.
• Left: band diagram representing the capture of carriers into the oxygen
vacancy traps with the application of a positive gate and drain voltages.
• Middle panel represents the de-trapping of the carriers with the reversal
of voltage. Right: The programming characteristics of a group of devices
was studied the relationship between Vt shift, ΔVt, and variability, σVt; ΔVt
> σVt, thus showing the ability to construct arrays.