Solid-State Electronics 47 (2003) 1045–1053

www.elsevier.com/locate/sse

A model for tunneling current in multi-layer tunnel dielectrics

Bogdan Govoreanu a,b,*, Pieter Blomme a,b, Maarten Rosmeulen a,b
,
Jan Van Houdt a, Kristin De Meyer a,b
a
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
b
KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Received 16 September 2002; received in revised form 29 November 2002; accepted 9 December 2002

Abstract
In this paper, we present a model for the tunneling currents through multi-layer stacks based on the independent
electron approximation and using an Airy functions based transfer matrix formalism. The transmission coefficient of a
tunneling electron is exactly calculated using a simple compact quasi-analytical formula. Comparison with the tradi-
tional WKB models reveals differences for particular stack structures. This model is applied to the analysis of multi-
layer tunnel dielectrics that aim at replacing the conventional tunnel oxide in non-volatile memory devices. Analysis of
the tunneling current for dual-layer stacks shows possibilities for higher speed and/or lower voltage programming,
which can be achieved with high-k materials considered for SiO2 replacement as gate dielectric.
Ó 2003 Elsevier Science Ltd. All rights reserved.

Keywords: Tunneling current; Multi-layer tunnel dielectrics; Airy functions; Non-volatile memory devices

1. Introduction order to maintain the 10 year retention requirements [3].

The emerging opportunities for Flash memory appli-
cations demand for both higher densities and lower
voltage operation. With the continuing downscaling of
MOS technologies, Flash memory faces tough chal-
lenges. Most of todayÕs Flash memory devices are
floating gate structures, which are programmed/erased
with either hot carriers or tunneling mechanisms [1]. The
former has the advantage of a higher speed but suffers
from a higher power consumption (which is critical in
several applications), although solutions have been
proposed to reduce it [2]. Tunneling based structures do
not have this drawback and offer low power operation.
However, due to the severe reliability specifications, the
tunnel oxide thickness is practically limited to 8–9 nm, in
*
Corresponding author. Address: IMEC, Kapeldreef 75, B-
3001 Leuven, Belgium.
E-mail address: govorean@imec.be (B. Govoreanu).
0038-1101/03/$ - see front matter Ó 2003 Elsevier Science Ltd. All rights reserved.
doi:10.1016/S0038-1101(02)00514-2
Consequently, high voltages are required for triggering
the tunneling mechanism, in order to avoid too large
programming times.
Recently, new concepts [4,5] have been proposed that
try to overcome these limitations and change the focus
of the research to the tunnel barrier engineering [3]. It
is demonstrated that either a profiled or a crested bar-
rier can be very beneficial in improving the memory
operation conditions. However, implementation of a
crested barrier in a CMOS process is not straightfor-
ward.
In this paper we develop a model suitable for ana-
lyzing the tunneling currents through multi-layer stacks
and we perform an analysis with respect to materials
that have a good chance to be integrated in future
CMOS technology as gate dielectrics. It is shown that
the presence of a SiO2 interfacial layer in a two-layer
stack is not detrimental and with a suitable material and
layer thickness combination it is possible to obtain a
higher programming speed and/or lower programming
voltages.
1046 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053

2. Tunneling current model

Rigorous quantum-mechanical calculation of the

leakage currents in deep submicron MOS devices re-
quires self-consistent solution of the Schr€ odinger and
Poisson equations, e.g. [6,7,16]. However, these ap-
proaches are either computationally intensive or their
implementation requires numerical techniques and ac-
curacy that virtually limit them to the analysis of ul-
trathin layers only. Simplified approaches [9] have been
demonstrated to work remarkably well if carefully ap-
plied. In this work, we propose a tunneling current
model based on the independent electron approximation Fig. 1. Illustration of the potential barrier of a stack of N di-
[8,9], which is particularly suitable for the analysis of electric materials under applied bias. Each dielectric layer is
Flash memory tunnel dielectrics. Assuming that electron characterized by a barrier height (UB0;i ), dielectric constant (ei ),
tunneling is an energy conserving process and the effective mass (mi ) and has a thickness di ¼ Xiþ1  Xi . Vd is the
total voltage drop across the dielectric stack.
transverse component of the momentum is also con-
served, the tunnel current density is given by:
Z 1 Z E
emc
J¼ 2 3 dE dE? TðE; E? Þ½f1 ðE; E? Þ  f2 ðE; E? Þ where HðxÞ is the step function and
2p h 0 0
ð1Þ X
i1
x  Xi
Wi ðxÞ ¼ UB0;i  eVj  eVi
W0;i  ci ðx  Xi Þ
where T is the transmission coefficient, E, E? are the j¼1
di
total energy and the transverse energy of a tunneling ð4Þ
electron, respectively, mc is the transverse electron ef-
fective mass (parabolic dispersion assumed for E? ) and with UB0;i being the barrier height measured from the
f1 , f2 are the equilibrium Fermi–Dirac distribution energy reference level at flatbands and di –– the thickness
functions in the electrodes. of the ith layer (situated between the coordinates Xi and
In order to calculate the transmission coefficient, the Xiþ1 ). Vi is the potential drop across the ith dielectric
voltage drop across the dielectric stack is determined by layer and is given by:
numerically solving the Poisson and MOS charge bal-
ance equations [10]. The voltage across the dielectric di =ei
Vi ¼ PN dj Vd ð5Þ
stack is then given by: j¼1 ej
Qid
Vd ¼ VG  VFB  ws  ð2Þ
Cd The transmission coefficient T is calculated by as-
where Qid is the equivalent interface charge sheet den- suming a one-band parabolic dispersion model for all
sity, Cd is the dielectric capacitance and the other sym- the dielectric layers and employing a transfer matrix
bols have their usual meaning. Surface potential formalism [16]. Plane waves are associated to the in-
enhancement due to the formation of the subbands at coming and outgoing electrons and the usual matching
the Si–insulator interface is taken into account using van conditions are applied at any interface to the 1D time-
DortÕs correction [11] extended to accumulation layers independent form of Schr€ odingerÕs equation, whose
[12]. Wavefunction penetration effects [13] have been corresponding solution is:
shown to affect ultrathin oxide layers below 1 nm, and
may have an impact on the MOS potential distribution. wðxÞ
However, for the range of thicknesses common to tunnel 8
> wL ðxÞ; x 6 X1 ;
dielectrics, which we consider in this paper, this effect is >
>
>
> w1 ð~x1 Þ; X1 < x 6 X2 or a1 > ~x1 P a1  d1 k1 ;
negligible, as the equivalent oxide thickness is at least a >
>
>
>
few nanometers. >
> ...
>
>
Assuming N ideal dielectrics and taking the bottom of < w ð~x Þ; Xi < x 6 Xiþ1 or ai > ~xi P ai  di ki ;
i i
the Si conduction band as energy reference, the potential ¼
>
> . . .
barrier of the stack has a piecewise linear shape (Fig. 1) >
>
>
>
and is given by: > wN ð~xN Þ;
>
>
XN < x 6 XN þ1 or aN > ~xN P aN  dN kN ;
>
> w ðxÞ; x > XN þ1
>
>
X
N : R
W ðxÞ ¼ Wi ðxÞ½Hðx  Xi Þ  Hðx  Xiþ1 Þ ð3Þ
i¼1 ð6Þ
 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053 1047

The plane waves wL , wR correspond to the left (L) and kR =mR jAR j2 mL kR 1
h
right (R) electrodes, respectively and linear combina- T¼ ¼ ð12Þ
hkL =mL jAL j2 mR kL jT11 j2

tions of Airy functions, wi , to each dielectric layer. ~xi Õs
represent transformed distances for each dielectric layer which can be used to calculate the tunneling current (1).
(see Appendix). The matching conditions require conti-
nuity of the wavefunction and of its effective mass
demultiplied spatial derivative at any point, particularly 3. Results and discussion
at any material interface where the individual wave-
functions have to be joined together: 3.1. Transmission coefficient

8 The key quantity in the tunneling current (1) is given

< wðxÞjx¼Xj ¼ wðxÞjx¼Xjþ
  ð7Þ by the transmission coefficient T for which several cal-
 
: m1 dwðxÞ
dx 
¼ m1þ dwðxÞ
dx  culation methods have been developed, the most com-
j  x¼Xj j x¼Xjþ
mon being the WKB approximation [17]. One of the
drawbacks of the WKB approach is that it is not able to
with the ‘‘’’ and ‘‘þ’’ symbols used for the left and the include quantum mechanical interferences of the inci-
right sides of a specific interface Xj . Applying the dent and reflected waves at the material interfaces. Re-
boundary conditions for each electrode/dielectric and cently, the WKB transmission coefficient through a
dielectric/dielectric interface, with corresponding wave- trapezoidal barrier has been corrected using a multipli-
functions as given by (A.2) and (A.7) (see Appendix), the cative factor [14,15] to include reflections at the dielec-
following formula can be derived, relating the coeffi- tric/electrode interface, but this correction is limited to
cients of the incoming and outgoing waves: the direct tunneling regime. Moreover, its use in ultra-




thin gate stacks with an extremely thin interfacial oxide
AL T11 T12 AR AR layer, having a thickness in the order of the equivalent of
¼
T ð8Þ
BL T21 T22 BR BR the de Broglie wavelength of the tunneling electrons [15]
is questionable. These complications can be avoided
where when using an approach based on Airy functions, at
least under the assumption of ideal dielectrics with sharp
1
! transition boundaries, since this gives the exact solution
pN 1 ikL
Y
N
T¼ fPi ðai ; ki ; hi;i1 ÞQi ðai ; di ; ki Þg of Schr€ odingerÕs equation associated to a microparticle
2 1  ik1L i¼1 in a constant field. For comparison, the Airy transmis-
!
1 1 sion coefficient is shown in Fig. 2a as a function of the
 ikR ikR : ð9Þ energy of the incident electron, for the case of a trape-
hN þ1;N
 hNþ1;N
zoidal and triangular barrier, respectively, for a SiO2
layer of 4 nm thickness. In the case of a 5 MV/cm electric
Pi and Qi are matrices associated to the ith layer and
field, depending on the energy of the incident particle,
given by:
the barrier is either trapezoidal or triangular, whereas

for a field of 10 MV/cm the barrier is triangular for any
Aiðai Þ Biðai Þ
Pi ðai ; ki ; hi;i1 Þ ¼  1 k Ai0 ða Þ  1 k Bi0 ða Þ energy value of an incident electron. A very good
hi;i1 i i hi;i1 i i
agreement is observed between the corrected WKB and
ð10Þ Airy transmissions at energies corresponding to the di-
rect tunneling case, whereas at higher energies the cor-
and
rected WKB is not able any longer to follow the fine
! grain shape of the Airy transmission. The oscillations of
Bi0 ðai  di ki Þ 1
ki
Biðai  di ki Þ
Qi ðai ; di ; ki Þ ¼ 0 1 the transmission coefficient correspond to the case of the
Ai ðai  di ki Þ  ki Aiðai  di ki Þ
triangular barrier and are associated to the electron
ð11Þ wave interference in the SiO2 conduction band. The
dependence of the transmission coefficient on the oxide
where hi;i1 ¼ mi =mi1 is the ratio of the effective masses voltage (Fig. 2b) confirms the very good agreement be-
of consecutive layers and by convention h1;0 ¼ m1 =mL , tween corrected WKB and Airy methods for low volt-
hN þ1;N ¼ mR =mN . ages down to the flatbands condition, corresponding to
Assuming that there is no reflected wave from infinity, the direct tunneling case, whereas for high voltages the
we can set BR ¼ 0 in (8). By further assuming AL ¼ 1 and corrected WKB overestimates the transmission coeffi-
BL ¼ R in order to avoid normalization, it follows that cient. Eventually, for ultrathin oxide layers, this may not
AR ¼ 1=T11 from which the transmission coefficient can be relevant, since MOS devices are never operated at
be readily expressed as: such voltages, which would breakdown the oxide.
1048 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053

0
10

Transmission Coefficient, T [-]

-2
10
Vg = 3 V
-4
10

-6
10

-8 WKB
10
WKB (corrected)
Airy
-10
10 Vg = 1 V

-12
10
0 0.5 1 1.5 2 2.5 3
(a) Energy, E [eV]

Potential energy, W [ev] 2

-1 Vg = 1V
Vg = 3 V
-2

-3
0 1 2 3
(b) Position, x [nm]

Fig. 2. (a) Comparison of the transmission coefficient for a 4
nm thick SiO2 barrier calculated with the WKB, corrected
WKB and Airy approaches respectively, as a function of energy
of the incident electron, at constant electric field. (b) Trans-
mission coefficient for thin SiO2 barriers calculated with the
WKB, corrected WKB and Airy approaches respectively, as a
function of oxide voltage drop.
When the oxide layer is replaced with a gate stack, the
situation changes: the differences become more pro-
nounced when the potential barrier has discontinuities,
as shown in Fig. 3a for a stack consisting of SiO2 and
Si3 N4 . The region of agreement reduces to the range (in
energy or voltage) corresponding to direct tunneling
through the whole stack (Fig. 3b). In all other situations,
the corrected WKB transmission deviates from the exact
value obtained with Airy functions. The small kinks in
the corrected WKB transmission correspond to the
transition of the right side turning point from the abrupt
to the linear region of the barrier, which makes the
WKB approximation invalid [15,17]. Hence, the differ-
ences between the corrected WKB and Airy transmis-
Fig. 3. (a) Transmission coefficients for a stack of SiO2 /Si3 N4
with 2 nm equivalent oxide thickness, with equal oxide and
nitride layers, as function of energy. (b) The corresponding
barrier profiles, at the same gate voltage drops.
sions are important for the case of gate stacks where
tunneling electrons enter the conduction band of a di-
electric layer, which is the case of the alternative tunnel
dielectrics we consider in this study and directly affect
the tunneling current.
Early calculations of the transmission coefficient with
Airy functions [18] predicted oscillations in the Fowler–
Nordheim tunnel current through triangular metal–
insulator–metal barriers. This result was experimentally
confirmed later on [19] and could not be explained by the
semiclassical WKB theory. More recent computationally
demanding approaches numerically calculated the
transmission coefficient through arbitrary shape poten-
tial barriers [20] or MOS structures [21]. These used a
discretisation technique solving Schr€ odinger equation
for each individual imaginary slice with a linearized po-
tential barrier resulted from gridding. By contrast, our
 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053
Fig. 4. Tunnel currents for 4 and 7 nm SiO2 and for a two-layer
stack, as functions of the oxide voltage using WKB, corrected
WKB and Airy methods for calculating the transmission coef-
ficient. The stack consists of 2.5 nm SiO2 and a 12.5 nm high-k
material with a dielectric constant of 15 and a barrier height of
2 eV.
method is a quasi-analytical approach that can handle
multi-layer dielectric barriers, being computationally in-
expensive. A single pair of Airy functions is associated
to a whole physical dielectric layer. A stack of N ¼ 2
dielectric layers merely requires four 2  2 matrix mul-
tiplications and incorporates the essential features of the
transmission coefficient dependence on the energy of the
incident electron.
Fig. 4 shows the differences between the tunneling
current calculated by using the standard and corrected
WKB approaches and the Airy approach, for layers of
SiO2 of 4 and 7 nm, and for a two-layer stack, respec-
tively. The difference attenuates when the oxide thick-
ness increases. However, for dielectric layers as thin as
4–6 nm the difference becomes visible. The small peaks
in the IV curves are due to the oscillations of the trans-
mission coefficient. However, these peaks would even-
tually not being observed in oxides thicker than a few
nanometers, since the distance travelled by an electron in
the conduction band of the insulator is considerably
larger than the mean free path, and the scattering events
destroy the phase coherence of the tunneling [22]. In the
case of stacks consisting of two or more layers the dif-
ferences are more pronounced as shown for a stack of
2.5 nm SiO2 and 12.5 nm high-k dielectric. These dif-
Table 1
Material parameters of some high-k dielectric materials, according to [17] (indicative values only)
Material Si3 N4 Al2 O3
Dielectric constant (e [–]) 7.5 10
Barrier height (UB0 [eV]) 2.0 2.8
1049
ferences are particularly important when one of the
layers shows a triangular barrier, which is the case for
voltage drops across the stack between 2 and 4 V in Fig.
4. The high steepness of the IV curve of the stack leads
to 2–3 orders of magnitude difference in current density,
and this is crucial in assessing correctly the performance
of such stacks at retention conditions.
3.2. Material issues
There are several candidate high-k dielectrics to re-
place the conventional SiO2 gate dielectric, of which the
most common are summarized in Table 1 [23] (the ma-
terial parameters have indicative values only, and actual
values may depend on the deposition method and pro-
cessing history and may differ from those indicated in this
table and considered in this study). Appropriate depo-
sition techniques have been developed and working de-
vices were demonstrated. However, it is often the case
that the high-k dielectric deposition requires an interfa-
cial SiO2 layer. In consequence, we assumed that SiO2 is
part of the stack, and performed an analysis of the tunnel
currents through asymmetric layers consisting of one
layer of SiO2 and one layer of an high-k dielectric. The
effective electron mass in SiO2 was subject to many
studies. Several values are reported in literature, gener-
ally ranging between 0.32m0 and 0.61m0 . However, this is
a complex problem and depends on the assumptions
made; different E–k dispersion relationships can be con-
sidered, although the simplified parabolic bands model
has been successfully used together with the effective
potential conduction band assumption for amorphous
SiO2 layers [24]. In this work, we considered an effective
mass for SiO2 of 0.5m0 , as reported by Weinberg [24] and
which fitted our experimental data of 7 nm tunnel oxide.
By contrast, little is known about the effective mass in the
high-k dielectrics. In this study, we assumed the same
effective mass for all the high-k dielectrics. We checked
that effective mass values (0.3–0.5)m0 do not qualitatively
alter the conclusions we will derive further.
3.3. Tunneling current analysis
Analysis of the tunneling current in high-k gate stacks
is subject to many recent studies, e.g. [25,26] report-
ing requirements for meeting the ITRS specifications
and scalability limits. However, little is known about
the potential performance of high-k stacks as tunnel
Y2 O3 ZrO2 HfO2 Ta2 O5
15 22 28 26
2.3 1.5 1.5 1.1
1050 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053
dielectrics. In the remainder of this paper we address this
issue, investigating the influence of the geometrical and
material stack parameters on the tunneling current and
discuss these results from a non-volatile memory (NVM)
point of view.
First, the influence of the layer thicknesses for two-
layer stacks is analyzed. Fig. 5a shows current density
dependence on the voltage drop across the stack Vd . The
thickness of the SiO2 layer is fixed at 3 nm and its barrier
height is 3.15 eV. The high-k dielectric was assumed to
have a dielectric constant of 15 and a barrier height of 2
eV as compared to the bottom of the Si conduction
band. These values are typical ‘‘averages’’ for the high-k
materials that are considered for SiO2 replacement [23].
The physical thicknesses of the stacks considered here
correspond to equivalent oxide thicknesses between 5
and 8 nm. The tunnel current in Fig. 5a shows that there
is a region where the slope of the current density changes
Fig. 5. Tunnel currents for stacks of two layers, one of which is
SiO2 . (a) The second layer has the following parameters:
UB02 ¼ 2 eV, e2 ¼ 15 and variable thickness. (b) The second
layer has a thickness of 12 nm (similar parameters) and the
oxide layer has a variable thickness.
significantly. This is due to the transition from tunneling
through two-layer barrier to tunneling through a single-
layer barrier. The transition voltage can be derived from
Eq. (5), for N ¼ 2:
d2 e1 UB02
Vtr ¼ 1 þ ð13Þ
d1 e2 e
and essentially gives the stack voltage drop beyond
which the tunneling is dominated by the first layer of the
stack. According to this relation, the shoulder in the J –V
curves shifts to higher voltage values when increasing
the thickness of the second layer, and to lower values
when increasing the thickness of the first layer, which is
also shown in Fig. 5b, where the thickness of the SiO2
layer was considered as a free parameter. However, the
shift to lower values is less pronounced for these stacks,
and this is due to the dominancy of the dielectric con-
stants ratio e2 =e1 as compared to the aspect ratio d2 =d1 in
(13). The slope of the tunnel current density is very high
for voltages below Vtr since both dielectric layers effec-
tively exhibit a barrier for the tunneling electrons.
When decreasing the barrier height of the second
layer, the transition voltage also moves to lower values
(Fig. 6a), as expected from (13). More interesting is the
nearly identical tunneling current for voltages above Vtr ,
which is due to the fact that the potential profile of the
first dielectric layer does not depend on the variable
barrier height of the second layer. The situation is dif-
ferent when the dielectric constant of the second layer is
considered as a parameter (Fig. 6b): this results not only
in a change of the transition voltage but also of the slope
of the current, which becomes higher with higher di-
electric constant. The transition voltage decreases when
the dielectric constant of the high-k layer increases, thus
lowering the voltage range suitable for programming.
In order to obtain higher programming speed with
such structures, the tunneling current at high bias must
be as high as possible, which requires that the thickness
of the first layer should be small, yet its presence is crucial
to modulate the shape of the barrier. To reduce the
programming voltage, a large fraction of the applied
voltage should drop over the first dielectric layer, for
which a small e1 =e2 ratio is needed. Since the SiO2 /high-k
stack acts as a capacitive divider, in the limiting case of
an electrically very thin high-k layer, the transition
voltage is determined mostly by the voltage drop over the
SiO2 layer, that merely must exceed UB0;hk =e. The barrier
height is mainly important in controlling the position of
the transition point. If the barrier height of the second
layer is too low, this would lead to too large currents at
low biases, hence compromising the retention.
Given the limited choice of alternative gate dielectrics,
it turns out that in order to get higher speed or lower
voltage programming, a second tunnel dielectric should
have a moderate barrier height as compared to that of a
 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053 1051

0
10

Gate current density, Jtunn [A/cm2]

-2
10
-4
10
-6
10
-8
10
- 10
10
- 12
10
SiO2 /Si3 N4
- 14
10 SiO2 /Al2 O3
- 16
SiO2 /Y2 O3
10 SiO2 /ZrO2
-18 SiO2 /HfO2
10 SiO2 /Ta2O5
-20
10
0 1 2 3 4 5 6 7 8
(a) Gate voltage, Vg [V]

0
10

Gate current density, Jtunn [A/cm2]

-2
10
-4
10
-6
10
-8
10
-10 SiO2 only
10 SiO2 /Si3 N4
- 12 SiO2 /Al2 O3
10
-14
SiO2 /Y2 O3
10 SiO2 /ZrO2
- 16 SiO2 /HfO2
10
SiO2 /Ta2O5
-18
10
- 20
10
0 1 2 3 4 5 6 7 8
Fig. 6. Tunnel currents for stacks of two layers, one of which is (b) Gate voltage, Vg [V]
SiO2 with a constant stack geometry, d1 ¼ 3 nm, d2 ¼ 12 nm:
(a) UB02 is a variable parameter and e2 ¼ 15. (b) e2 is a variable Fig. 7. (a) Tunnel currents through stacks of two layers with
parameter and UB02 ¼ 2 eV. the same physical thickness, with 2.5 nm SiO2 and 12.5 nm
high-k material. (b) Tunnel currents through stacks of equal
electrical thickness of 5 nm. The high-k material parameters are
taken as averages from Table 1. The n-type substrate doping is
SiO2 layer and a high dielectric constant, whereas the 1017 cm3 .
barrier thickness can be used to control the voltage
operation range. It must also be noticed that in order to
allow for bidirectional operation of the stack while barrier height, which is beneficial for retention whereas
maintaining the benefits, a symmetric three-layer version the relatively high dielectric constant determines the in-
of the barrier, with the high-k material in the middle crease of the current density at high biases.
would be required. The tunneling currents through the stacks are also
Calculations of the tunnel currents for stacks of iden- compared to that of an SiO2 layer of equal electrical
tical thickness as a function of applied gate bias VG (Fig. thickness––EOT (Fig. 7b). The thickness of the high-k
7a) shows that a higher tunneling current needs a lower layer corresponds to 3 nm EOT and the SiO2 thickness
UB0 of the high-k layer, e.g. stacks with Ta2 O5 , HfO2 and is 2 nm. The comparison is performed for the same
ZrO2 . However, a too low barrier as in the case of Ta2 O5 EOT since, in an NVM structure, the EOT would ul-
has to be avoided since it causes relatively high currents at timately determine what fraction of the external bias
low biases. This effect is more pronounced when the high- effectively drops over the barrier. The transition voltage
k dielectric constant increases. Al2 O3 stacks are more is now entirely determined by the high-k barrier only,
effective in retention due to the higher barrier height since the prefactor in Eq. (13) is constant. The tunnel-
combined with a moderate dielectric constant. Stacks ing current is nearly identical for high voltages, being
with Y2 O3 have low current at low bias and relatively mainly determined by the SiO2 field. Hence, program-
high current at high bias. This is due to the relatively high ming through such stacks would bring the same benefits
1052 B. Govoreanu et al. / Solid-State Electronics 47 (2003) 1045–1053

as programming through the 5 nm EOT. Moreover, at 2 d2

h
 wðxÞ þ W ðxÞwðxÞ ¼ EwðxÞ ðA:1Þ
low biases, the tunneling current through the stack 2m dx2
would eventually become smaller due to the larger
physical thickness (tunneling through the stack is then Analytical solutions exist for some particular cases.
mainly controlled by the second, thicker dielectric lay- Below, the solutions for a constant potential and a
er), allowing for better retention. The tunnel current constant field are described.
enhancement with respect to the EOT is obtained in the
moderate voltage range. Therefore, higher barrier ma- A.1. Constant potential
terials are more effective in offering better retention at
identical speed, whereas lower barrier materials are If the potential energy is constant, (W ðxÞ
W0 for
more effective in lowering the programming voltage as a given spatial region), then the general solution of
compared to the conventional devices with the same Schr€
odingerÕs equation is given by:
EOT. wðxÞ ¼ A expðikðx  X ÞÞ þ B expðikðx  X ÞÞ ðA:2Þ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4. Conclusion with k ¼ 2mðE  W0 Þ= h, for a classically allowed re-
gion (i.e. E P W0 ). For a classically forbidden region (i.e.
We presented a model for the description of the tun- E < W0 ) the general solution can be formally obtained
neling current through multi-layer dielectric stacks, by setting k ¼ ij:
which has been used to analyze the conduction through wðxÞ ¼ A expðjðx  X ÞÞ þ B expðjðx  X ÞÞ ðA:3Þ
double-layer stacks. This model calculates exactly the pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
transmission coefficient through multi-layer stacks ex- with j ¼ 2mjE  W0 j= h. The phase factor ikX has
pressed in a compact form using Airy functions. The been introduced for convenience.
influence of material parameters and of the aspect ratio
has been considered and requirements to enhance tun- A.2. Constant field
neling for achieving higher speed or lower voltage op-
eration were discussed. The most promising two-layer Considering a potential profile given by:
combination with SiO2 as one of the layers points to a W ðxÞ
W ðxÞ ¼ W0  cðx  X Þ ðA:4Þ
material with moderate barrier height and a significantly
higher dielectric constant as compared to SiO2 . These where c ¼ eF , with e the electron charge and F the
requirements are compatible with the parameters of the electric field. W0 represents the potential energy at x ¼ X .
high-k materials considered for the SiO2 replacement as A linear space transformation of the type
gate dielectric in future CMOS technologies. Moreover,
1=3  
it has been recently demonstrated that mixed oxides 2mc W0  E
~x ¼  ðx  X Þ
a  kðx  X Þ
such as (HfO2 )x (Al2 O3 )ð1xÞ [28] allows for obtaining h2
 c
gate dielectrics with variable bandgap and band offsets, ðA:5Þ
on top of improved thermal stability. This enlarges the
design window and allows for a more flexible choice of transforms the original equation (A.1) into:
the high-k dielectric suited for increased tunneling cur- d2
rent. If successfully integrated, these materials may be- wð~xÞ  ~xwð~xÞ ¼ 0 ðA:6Þ
d~x2
come very attractive for Flash memory devices as well,
allowing to further scale down the conventional floating This equation has as general solution a linear com-
gate structures for decananometric technology nodes. bination of independent Airy functions [27], namely
Aið~xÞ and Bið~xÞ:
Acknowledgements wð~xÞ ¼ C  Aið~xÞ þ D  Bið~xÞ ðA:7Þ

Wim Magnus and Wim Schoenmaker are acknowl-

edged for useful discussions and comments and for
critical reading of the manuscript.
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