Journal of the Korean Physical Society, Vol. 41, No. 5, November 2002, pp.

805∼808

Polysilicon Stepped Shallow Trench Isolation Technology

for 0.14 µm and Beyond

Choong Hun Lee∗

Division of Electric & Electronic Engineering, Wonkwang University, Iksan 570-749

Seung-joon Kim
Semiconductor Etch Process R&D Department, Advanced Technology Line, Gwangju 464-862

Jin Jang
Department of Physics & TFT-LCD National Laboratory, Kyung Hee University, Seoul 130-701

(Received 4 October 2002)

Polysilicon stepped shallow trench isolation (PS-STI) using a Si3 N4 /Poly-Si/SiO2 stacked mask
has been proposed for 0.14 µm and beyond. The PS-STI profile has a poly-Si step length and
a protrusion in the trench sidewall after PS-STI etching. The poly-Si is oxidized to form a thin
liner oxide, and then a small bird’s beak is grown. The PS-STI process has some advantages for
ULSI processing. Firstly, the oxide recess at the trench edge is prevented because of partial poly-Si
oxidation during the liner oxidation; hence, the subthreshold kink of the shallow trench isolated
metal oxide semiconductor field effect transistor (MOSFET) is successfully suppressed. Secondly,
because of the increased active area due to the step length oxidation, the reduced contact resistance
results in an increased drain current. Also, the PS-STI process successfully suppresses the inverse
narrow-width effects and shows excellent time-dependent dielectric breakdown results for the gate
oxide integrity.

PACS numbers: 85.30.Tv, 85.40.Ls

Keywords: Shallow trench isolation, Inverse narrow-width effect, Time-dependent dielectric breakdown

As devices scale down, the shallow trench isolation
(STI) technique is becoming indispensable for achieving
higher packing densities and performances [1]. Also, the
current driving capability of active transistors based on
STI can be improved since the effective channel width
is not reduced by STI. However, the subthreshold kink
effect of MOSFET is still an inherent issue for the con-
ventional STI process. The kink effect due to gate
wrap-around leads to an undesirable double hump in the
subthreshold ID -VG characteristics [2–5]. The inverse
narrow-width effect (INWE) also should be minimized
to control the threshold voltage of a MOSFET. One of
the solutions to prevent the INWE is corner implanta-
tion [5], but the shadowing effect by the SiN mask is not
negligible for small-pitch isolation.
There have been many efforts to eliminate theses issues
[3–11]. Most of the reports on eliminating the INWE are
focused on the narrow-width devices with long channels,
but for higher density devices, a stable small-device fab-
rication technology both for short-channel devices and
for narrow-width devices is needed. In this paper, we
∗ E-mail: chlee@wonkwang.ac.kr; Fax : +82-63-843-2116
propose a novel STI technology which uses a Si3 N4 /Poly-
Si/SiO2 stacked mask and introduce a new robust kink-
free way with a better margin in contact patterning and
more drain current flow. The technology uses quite sim-
ple and highly reliable processes. Some authors have
reported using a poly-Si buffered-mask STI (PB-STI),
but the shrinkage of the active area due to oxidation of
the buffered poly-Si can cause the severe problems dur-
ing the contact opening process [8]. We propose new
methods to prevent the active shrinkage and to get bet-
ter process margins. The electrical parameters of our
PS-STI are compared with those of conventional shallow
trench isolation processes.
Figure 1(a) compares the process sequences for con-
ventional STI with that for the PS-STI proposed in this
work. A 450 Å poly-Si layer and a 1500 Å nitride layer
are deposited on a 150 Å pad oxide, and the shallow
trench isolation pattern is defined. These layers are
etched in sequence to form 4000 Å deep shallow trenches
in the substrate, and the profile has a step in the poly-Si
layer as shown in Fig. 1(b). The step is intentionally
formed during nitride and poly-Si etching by using the
polymer layer formed due to the high etch selectivity of

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-806- Journal of the Korean Physical Society, Vol. 41, No. 5, November 2002

Fig. 2. SEM image of the PS-STI process after gate poly-Si

deposition. A small bead’s beak is formed around the trench
corner.

of an n-channel MOSFET with W/L = 0.20 µm/0.14

µm for (a) conventional STI and (b) PS-STI. With in-
creasing back gate bias(Vb = 0∼−4 V), no apparent ID -
VG double-hump problem is seen in these figures. How-
Fig. 1. (a) Process sequences and (b) schematic diagrams ever, the subthreshold slope distributions in the conven-
of the PS-STI process. tional case were wider than those in the PS-STI case
(not shown) [4]. Also, the PS-STI process shows less
off-leakage current. These values of the channel length
the nitride and the poly-Si. After photo resist strip, the and the channel width are applicable at higher density
trench sidewall is re-oxidized at 900 ◦ C for 20 min to devices. The gate poly-Si wrap-around and the fringing
form a thin thermal liner oxide. During the oxidation, of electric field are believed to be significantly reduced
the trench corner is rounded, and a small bead’s beak is around the active edge. This suppression electric-field
formed by sidewall oxidation of the poly-Si without any crowding at the trench edge is responsible for the elimi-
additional process. Without this step, the small bead’s nation of the anomalous subthreshold kinks and leakages.
beak will penetrate into the active area, reducing the ac- Figure 5 shows the drain currents for the conventional
tive area and giving worse process margins. Chemical STI and the PS-STI processes as functions of the gate
vapor deposition (CVD) is then used to refill the trench length in n-channel MOSFET. The PS-STI shows a large
with oxide followed by a densification annealing. Chem- current flow, which is believed to be due to the enlarged
ical mechanical polishing (CMP) is subsequently carried
out to planarize the CVD oxide to the nitride that serves
as the polish stopping layer. After the remaining nitride
layer is stripped, the poly-Si is etched. In sequence, the
pad oxide is removed by using a diluted HF solution. For
standard trench isolation, the oxide at the isolation edge
is recessed during the pad-oxide removal step whereas the
oxide from the poly-Si and the oxide from the self-aligned
sidewall still remained in the case of PS-STI. The rest of
the processes are the same as they are in conventional se-
quence. Only two process steps (poly-Si deposition and
stripping) are added to the conventional STI to achieve
the new PS-STI.
Figure 2 shows a cross-sectional scanning electron mi-
croscope (SEM) image after gate poly-Si deposition. For
PS-STI, no oxide recess is observed at the trench cor-
ner and a small bird’s beak is formed around the corner.
Figure 3 shows the threshold voltage behavior as a func-
tion of the gate width at a fixed channel length L = 0.18
µm. The INWE was suppressed successfully for widths Fig. 3. Behavior of the threshold voltage in an n-MOSFET
as small as W = 0.16 µm. as a function of the channel width. The channel length was
Figure 4 shows the typical ID -VG characteristic curves fixed at 0.18 µm.
Polysilicon Stepped Shallow Trench Isolation Technology for 0.14 µm and Beyond – Choong Hun Lee et al. -807-

Fig. 4. ID -VG characteristic curves of an n-channel MOS-

FET with W/L = 0.20 µm/0.14 µm for (a) conventional STI
and (b) PS-STI. The curves are measured for a back gate bias
Vb =0, −1, −2, −3, or −4 V.

area resulting from the suppression of penetration of the

small bead’s beak into the active area. Fig. 6. Constant current TDDB result for conventional
STI and PS-STI (NMOS capacitor with a 2.0-mm2 area and
Figure 6 shows the constant current time dependent
400-mm length, Tox = 32 Å).
dielectric breakdown (TDDB) results for the conven-
tional STI and PS-STI processes. The structure of the
gate oxide integrity is a finger-type structure with a long
off-leakage current is achieved. Because of the increased
peripheral length (NMOS capacitor with a 2.0-mm2 area
active area due to the step length oxidation, the contact
and a 400-mm length). Failure of the oxide integrity with
resistance is reduced, resulting in a larger drain current
the conventional STI process is clearly observed whereas
flow. Also, the PS-STI process successfully suppresses
failure is markedly suppressed with the PS-STI process.
the inverse narrow width effects and shows excellent time
In summary, we have proposed a novel PS-STI tech-
dependent dielectric breakdown (TDDB) results in the
nology which uses a Si3 N4 /Poly-Si/SiO2 stacked mask,
gate oxide integrity.
and introduces a new, robust, kink-free way with a bet-
ter margin in contact patterning and more drain current
flow. The technology uses quite simple and highly re-
liable processes. The new process is conventional PB- ACKNOWLEDGMENTS
STI with a step added, and that step prevents shrink-
age of the active area and gives better process margins. This work was supported by the Korea Research Foun-
The oxide recess at the trench edge is prevented because dation (Project No. KRF-97-016-E00137 E5200).
of poly-Si partial oxidation during the liner oxidation;
hence, the subthreshold kink of the shallow trench iso-
lated MOSFET is successfully suppressed and a lower
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