METALS AND MATERIALS International, Vol. 9, No. 5 (2003), pp.

503~506

Fabrication of SOI Structures with Buried Cavities Using Si Wafer Direct

Bonding and Electrochemical Etch-stop

Gwiy-Sang Chung*

School of Information System Engineering, Dongseo University

San 69-1 Jurye-dong, Sasang-gu, Busan 617-716, Korea

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical
etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity,
and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle
Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate
with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until
electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB
SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension
of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with
buried cavities is a powerful and versatile technology for new MEMS applications.
Keywords: SOI structure, buried cavity, SDB, electrochemical etch-stop, free standing structure

1. INTRODUCTION wafers. Meanwhile, using Si-wafer direct bonding (SDB) tech-

Recently, with the development of the ability to fabricate
microstructures more easily by using Si micromachining
technology, there has been active research on microelctro-
mechanical systems (MEMS) intergrated with devices on an
identical substrate. In general, Si micromachining technol-
ogy can be categorized into bulk and surface micromachin-
ing [1,2]. MEMS devices fabricated by bulk micromachining
are large and of relatively high-cost. Fabricated by anisotro-
pic wet etching in KOH, EDP or TMAH solutions, the struc-
tural shapes are restricted by the limitations of the Si crystal
face [3]. Also, because surface micromachining technology
utilized the growth of multi-layers or deposited thin-films on
Si wafers, the vertical dimension of the microstructures is
defined by the thickness of the deposited or thin-films, which
is currently limited to less than 10 to 20 μm. Even with care-
ful processing, residual stresses and stress gradians in the
thin-film place limitations on the lateral dimensions.
Fabrication of a Si-on-insulator (SOI) wafer with free stand-
ing Si membranes was previously reported by Graff and
Schubert [4]. This SOI structure was formed by the chemical
vapor deposition (CVD) method, which produces a polysili-
con active layer with a 1.5 μm thickness for optical-MEMS.
However, polysilicon membranes have some problems, such
as residual stress and weak bond strength with the handling
nology, a thin Si layer with a single-crystal can be fabricated.
In addition, the fabricated SOI substrate has a large area and
perfect insulator property with thermal oxide. Moreover, it
can simply create a thick membrane for Si bulk microma-
chining with buried cavities. Also, thin or thick Si membranes,
cantilevers, and bridges can be accurately fabricated [5]. In
particular, these fabricated SDB SOI structures are applica-
ble to the development of bio-MEMS and micro-fluidic
devices, such as pressure sensors for medical use, micro-tun-
nel probe arrays, microvalves and micropumps, and drug
delivery systems.
In terms of thinning and accurate thickness control of the
SOI active layer, it is important to use the SDB SOI technol-
ogy in MEMS applications. The electrochemical etch-stop is
the safest of the thickness control technologies. It can also
control dozens of Å final surface roughness and thickness
within 0.2 μm [6].
In this paper, we have fabricated SDB SOI structures with
buried cavities and have investigated the flatness of the etch-
stopped surface, applying electro-chemical etch-stop in the
thinning of the SDB SOI substrate. The fabricated free-stand-
ing structures are analyzed by atomic force microscopy (AFM)
and scanning electron microscopy (SEM), respectively.
2. EXPERIMENTAL PROCEDURE

*Corresponding author: gschung@gdsu.dongseo.ac.kr In this work, we used two boron doped 4 inch diameter

 Gwiy-Sang Chung

Fig. 1. Fabrication process seqenences of SDB SOI structures with

buried cavities by using SDB technology and electrochemical etch-


  
Fig. 2. Configuration for electrochemical etch-stop. Working elec-
stop: (a) formation of buried cavity; (b) formation of a feedthrough
   
hole; (c) Si direct bonding; and (d) fabrication of SDB SOI structures trode, Reference electrode, Counter electrode, Potentiostat,


with buried cavities by using electrochemical etch-stop. Plotter, Ag/AgCl, Pt mesh, Teflon holder, PC. Sam-


ple, Magnetic stir-bar, Hot plate, Reflux condenser, Bur-
ied cavity
(100) Si wafers, which have a size of 3.0×3.0 cm2 with a
resistivity of 12.23 Ω·cm and a thickness of 505 μm. The 3. RESULTS AND DISCUSSION
handling wafer was p-type and the active wafer consisted of
a 15 μm thick n-type epitaxial layer grown on a p-type sub- To prevent early etch-stop during the Si membrane fabri-
strate. The oxide layer was thermally grown to about 5000 Å. cation process, we compared the leakage current-voltage
The fabrication process of SOI structures with buried cav- characteristics curves of the p-type and the n-epitaxial layer
ities is shown in Fig. 1. The Si substrates used underwent a grown p-type Si wafers. Fig. 3 shows the leakage current-
standard semiconductor cleaning process to remove organic/ voltage characteristic curve of p-type in a 20 wt.%. TMAH
inorganic particles on the Si surfaces. Before SDB process- solution at 80 oC. The boron doping concentration of the
ing, we also carried out anisotropic etching on the backside used p-type substrate is 1014 ~ 1015 cm−3, and the scan rate is
of the p-type handle wafer to define an array of vias to serve 5 mV/sec and the supplied voltage is −2 V~2 V. At an open
as contact holes for the electrochemical etchback. Also, circuit potential (OCP) point of −1.4 V, the leakage current
complete etching of the sample and n-epitaxial wafer were continually increased until arriving at the passivation point
carried out pre-bonding after pre-treatment in the dilute HF (PP). At the passivation point of 1.2 V, the leakage current on
(2.0 %) for an minute [7]. The bonded Si wafer with buried
cavities was given a controlled thickness of an n-epitaxial
layer using electrochemical etch-stop after annealing to
1000 oC for 60 min [8,9]. The completely bonded samples
with buried cavities were used in the fabrication of SDB SOI
structures for bulk micromachining.
Fig. 2. shows the configuration for the electrochemical
etch-stop process in fabricating SDB SOI structures with
buried cavities. At a temperature of 80 oC, TMAH solutions
with 20 wt.% were chosen for the etching experiments. Dur-
ing the handling wafer etching, constant voltage was sup-
plied between a working electrode and a reference electrode,
using a scanning potentiostat. A magnetic stirrer was used to
maintain the 20 wt.% TMAH solution throughout the bea-
ker. Finally, an SOI structure with a single-crystal Si active
layer and buried cavities was completely fabricated. Fig. 3. Leakage current-voltage characteristic curve of p-type Si wafer.
 Fabrication of SOI Structures with Buried Cavities Using Si Wafer Direct Bonding and Electrochemical Etch-stop


Fig. 4. (a) Leakage current-time characteristic curve and (b) etch-stop step at electro-chemical etch-stop, respectively.

the Si wafer increased spirally, and then suddenly decreased.

The highest current density was measured at about 1.35 mA/cm2,
and the leakage current density maintained at 0.035~
0.046 mA/cm2 after having been etch-stopped.
The leakage current-time characteristic curve for the elec-
trochemical etch-stop is shown in Fig. 4(a). Using the refer-
ence electrode (Ag/AgCl) in a three-electrode system, the
leakage current was maintained regularly in the Si etching
time. After the p-type Si was etched, the leakage current sud-
denly increased when n-epitaxial Si was exposed to the
etched solutions. When the n-epitaxial Si was completely
exposed, the etching was stopped by the passivation of the

chemical reaction with the etched solutions. Fig. 4(b) shows
the etch-stop steps. In step the p-type Si has appeared


because of oxidation-restoration in the etched solutions. Step
shows that the surface of the p-type Si wafer was partly
removed in the TMAH solutions and then the leakage cur-
rent of the pn junction rapidly increased to 2 mA/cm2 at a
supplied voltage of 1.2 V. Step 
shows that the p-type Si
has been completely etched and the etching has been stopped
by passivation in the n-epitaxial Si layer.
Figs. 5(a) and (b) show AFM images of n-epitaxial layers Fig. 5. AFM images of (a) Si polishing surface and (b) SDB SOI sub-
grown on a p-substrate (100) mirror surface and SDB SOI strates with buried cavities etch-stopped by electrochemical etch stop
substrates with buried cavities etch-stopped using electro- in TMAH (20 wt.%) solution.
chemical etch-stop in a 20 wt.% TMAH solution. The aver-
age roughness of the n-epitaxial layer surfaces and etch- etch-stop, the flatness of the etch-stopped SOI substrates is
stopped SOI substrates is 5.12 nm and 5.4 nm, respectively. superior to that of other methods such as lapping and chem-
In the case of SDB SOI structures made by electrochemical ical-mechanical polishing (CMP), and corresponds to that of

 Gwiy-Sang Chung

4. CONCLUSIONS

Applying electochemical etch-stop to the method for thin-

ning SDB SOI structures, we have fabricated an SOI struc-
ture with buried cavities and subsequently investigated the
flatness of the etch-stopped surface and the variation of the
SOI thickness. After making buried cavities, the SDB SOI
structure was fabricated using electrochemical etchback. The
fabricated SDB SOI substrate with buried cavities can utilize
the electronic and mechanical characteristics of high-quality
single-crystal Si. The combination of these two powerful
micromachining techniques constitutes a versatile new tech-
nology for the fabrication of MEMS devices. As such, these
fabricated 3-D microstructures could be used in microsen-
sors and microactuators, such as pressure sensors, flow sen-
sors, and micro fluidic devices.

ACKNOWLEDGMENT

This work was supported by Dongseo University, “Dong-

seo Frontier Project” Research Fund of 2002.

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