MR-11632; No of Pages 5

Microelectronics Reliability xxx (2015) xxx–xxx

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Microelectronics Reliability

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Analysis of neutron-induced single-event burnout in SiC power MOSFETs

Tomoyuki Shoji a,c,⁎, Shuichi Nishida b, Kimimori Hamada b, Hiroshi Tadano c
a
Toyota Central R&D Labs., Inc., Nagakute, Aichi, Japan
b
Toyota Motor Corporation, Toyota, Aichi, Japan
c
Graduate School of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki, Japan

a r t i c l e i n f o a b s t r a c t

Article history: The triggering mechanism of single-event burnout (SEB) in SiC power MOSFETs was studied by white neutron
Received 25 May 2015 irradiation experiments and device simulations. Electron–hole pairs generated along a recoil ion trajectory
Received in revised form 18 June 2015 resulted in a highly localized SEB current. This dynamic current led to an increase in the electron density in the
Accepted 18 June 2015
vicinity of the n−/n+ interface, which resulted in a shift in the peak electric field strength. Finally, a local
Available online xxxx
short-circuit occurred between the drain and source electrodes by punch-through of the electric field in
Keywords:
the n+ source diffusion region.
Single-event burnout A cross-sectional view of the SEB damage showed that melting of the SiC occurred and cracks were formed in
SiC power MOSFETs the n− drift region due to the highly localized SEB current. This indicates that the maximum lattice temperature
Reliability reached the sublimation temperature of SiC. The location of the simulated peak lattice temperature agreed closely
with the position of the observed SEB damage. This demonstrated that the main mechanism triggering SEB in SiC
power MOSFETs is not parasitic npn-transistor action, but a shift in the peak electric field and the punch-through
in the n+ source diffusion region, similar to the case for SiC power diodes.
© 2015 Elsevier Ltd. All rights reserved.

1. Introduction
Cosmic ray neutrons cause probabilistic failure of power semiconduc-
tor devices. Recoil ions created by nuclear spallation reactions between
incident neutrons and the constituent nuclei of the device lose kinetic
energy while traveling through the device. The lost energy is used up in
generating electron–hole pairs along the recoil ion trajectory, which
results in a highly localized current. When a high voltage is applied to
the device, the lattice temperature increases locally due to Joule heating.
The SEB failure rate increases sharply at a certain bias voltage, which is
defined as the SEB threshold voltage. The SEB threshold voltage is a crucial
factor for high-reliability device design. Therefore, it is important to clarify
the mechanism of neutron-induced SEB in power devices.
Various experimental and simulation studies have been conducted to
analyze the triggering process in SEBs [1–14]. For insulated-gate bipolar
transistors (IGBTs) with a voltage rating of 1200 V, electron–hole pairs
generated along the recoil ion trajectory lead to a shift in the peak electric
field from the junction between the n− drift region and the p− body
region to the interface between the n− drift region and the n+ buffer
region. Impact ionization occurs at the n−/n+ interface, and the generated
electrons are subsequently injected into the neutral base region.
Consequently, a parasitic pnp transistor (p− body region/n− drift
region/p+ collector region) is switched on locally. Finally, parasitic
thyristor action results in SEB. For power diodes that do not have an
⁎ Corresponding author at: Toyota Central R&D Labs., Inc., Nagakute, Aichi, Japan.
E-mail address: shoji@mosk.tytlabs.co.jp (T. Shoji).
inherent parasitic transistor, the SEB failure mechanism is closely related
to diode secondary breakdown due to a hammock-like electric field
distribution.
Moreover, annular microvoids formed by neutron-induced SEBs were
observed in Si power diodes [14]. The diameters of the microvoids were
observed in two pieces of the samples, the value were 1 μm and
0.34 μm, respectively. These values were estimated by using the proposed
analytical formulas and the energy associated with Joule heating, which
was calculated by device simulations. Without carrier generation by
impact ionization, the current associated with electron–hole pairs along
the recoil ion track would be low, Joule heating would be negligible, and
no SEB would occur. Therefore, SEB can be viewed as local thermal failure
caused mainly by current-induced avalanche (CIA).
In contrast, there are few studies on neutron-induced SEBs in SiC
power devices [15–18], and the mechanism triggering SEB is still
unknown. In this study, white neutron irradiation experiments with
SiC power MOSFETs were performed to analyze the SEB damage
due to the highly localized current. Moreover, transient device
simulations were carried out to determine the mechanism triggering
neutron-induced SEBs.
2. Analysis of neutron-induced SEB damage in SiC power MOSFETs
White neutron irradiation experiments were performed on 20
samples to analyze SEBs in commercially available SiC power MOSFETs
with a voltage rating of 1200 V. The experimental SEB cross section vs.
biased voltage has been reported [18]. The white neutron beam was

http://dx.doi.org/10.1016/j.microrel.2015.06.081
0026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: T. Shoji, et al., Analysis of neutron-induced single-event burnout in SiC power MOSFETs, Microelectronics Reliability
(2015), http://dx.doi.org/10.1016/j.microrel.2015.06.081
2 T. Shoji et al. / Microelectronics Reliability xxx (2015) xxx–xxx

Fig. 1. Schematic of experimental test circuit.

provided by the Research Center for Nuclear Physics (RCNP) at Osaka

University. The maximum energy of the beam was 400 MeV [18,19].
Fig. 1 illustrates the experimental test circuit. The device was kept in the
off state and a DC voltage was applied during white neutron irradiation.
An oscilloscope measured the difference in potential between the two
ends of the 10 Ω resistor to detect the SEB current of the device under Fig. 3. Cross-sectional SEM image of SEB damage.

test (DUT). A 10 kΩ current-limiting resistor was attached between the

drain electrode and DC power supply.
Fig. 2 shows scanning electron microscopy (SEM) images of the SEB
damage after unsealing the package resin. The shell-shaped region of
damage in the polyimide passivation occurred due to expansion stress
from within the device during SEB. The diameter of the damage region
was 29 μm, and a void with a radius of 2.9 μm was observed at the
center.
Fig. 3 shows a cross-sectional SEM image of the SEB damage. The
cracks observed inside the n− drift region were formed as a result of
the expansion stress due to the sublimation of SiC. The maximum
crack size was 92 μm. Fig. 4 is a magnified image of Fig. 3 showing the
device structure. Molten SiC was formed in the n− drift region. These re-
sults indicate that the lattice temperature reached the sublimation
temperature of SiC and that the polyimide passivation was pushed up
owing to the expansion stress generated during SEB.
Fig. 5(a-1) and (a-2) show SEM images of the device surface after
unsealing of the package resin. SEB damage was observed at different
depths using the slice-and-view technique in the focused ion beam
(FIB) system. The stereomicroscopy (left side) and SEM (right side)
images in Figs. 5 and 6 show areas within and below the n− drift region,
respectively. The stereomicroscopy images show the interference of
light reflected from different crack planes; the area of observation has
a radius of about 80 μm. Cracks reflecting the hexagonal crystal structure
of SiC can be observed, and the damage is axisymmetric with respect to
the central void, owing to the highly localized SEB current. In addition,
Joule heat was generated in the n− drift region where an electric field

Fig. 2. SEM views of SEB damage after unsealing of the packaging resin: (a) shell-shaped SEB damage with 45° tilt angle, diameter: 29 μm; (b) 90° rotation with respect to (a); and
(c) magnified view of (a), void radius: 2.9 μm.

Please cite this article as: T. Shoji, et al., Analysis of neutron-induced single-event burnout in SiC power MOSFETs, Microelectronics Reliability
(2015), http://dx.doi.org/10.1016/j.microrel.2015.06.081
 T. Shoji et al. / Microelectronics Reliability xxx (2015) xxx–xxx
Fig. 4. Magnified view of Fig. 3 and device structure.
Fig. 5. Slice-and-view observations from the surface of a SiC MOSFET using FIB with 3-μm
steps (inside n− drift region): (a-1) SEM image of device surface and (a-2) magnified
view, (b-1) stereomicroscopy and (b-2) SEM images at 3-μm depth from device surface,
(c-1) stereomicroscopy and (c-2) SEM micrographs at 6-μm depth from device surface,
and (d-1) stereomicroscopy and (d-2) SEM images at 9-μm depth from device surface.
Please cite this article as: T. Shoji, et al., Analysis of neutron-induced single-event burnout in SiC power MOSFETs, Microelectronics Reliability
(2015), http://dx.doi.org/10.1016/j.microrel.2015.06.081
3
was applied. These results indicate that the sublimation temperature was
rapidly reached as a result of the SEB current.
The results for SEB damage in SiC power MOSFETs are similar to
those for SiC power diodes with the same voltage rating [13].
3. Simulation study of SEB triggering mechanism for SiC
power MOSFETs
Technology computer aided design (TCAD) simulations were carried
out to determine the mechanisms triggering SEBs in SiC power MOSFETs.
The transient device simulations described the electron–hole pairs
generated along the track of recoil ions from the n+ source diffusion
region at the device surface to a depth of 8 μm. A voltage of 1000 V,
which is close to the SEB threshold, was applied between the drain and
source during transient electro-thermal simulations. The self-heating
effect was modeled by incorporating a thermal diffusion equation.
Fig. 7 shows simulated results for the time evolution of the SEB
current in SiC power MOSFETs, the maximum lattice temperature, the
SiC surface temperature, and the aluminium (Al) surface temperature.
Finally, the maximum lattice temperature reaches the sublimation
temperature of SiC. On the other hand, the Al surface remains at room
Fig. 6. Slice-and-view observations from the surface of a SiC MOSFET using FIB with 3-μm
steps (at depths lower than the n− drift region): (e-1) stereomicroscopy and (e-2) SEM
images at 12-μm depth from device surface, (f-1) stereomicroscopy and (f-2) SEM
images at 15-μm depth from device surface, (g-1) stereomicroscopy and (g-2) SEM images
at 18-μm depth from device surface, and (h-1) stereomicroscopy and (h-2) SEM images at
21-μm depth from device surface.
4 T. Shoji et al. / Microelectronics Reliability xxx (2015) xxx–xxx

t4
tf
t3
t1
t2

Fig. 7. Time evolution of simulated SEB current, maximum lattice temperature, SiC surface
temperature, and Al surface temperature. Fig. 9. Electron density along ion track at times indicated in Fig. 7.

temperature because the heat cannot be conducted to the Al surface in

the short period of time available. Therefore, the SEBs in SiC power
MOSFETs originate within the semiconductor, and are not caused by
thermal expansion of the electrode at the device surface, similar to the
case for SiC power diodes [13].
Fig. 8 shows the electric field distribution along the recoil ion track
at the times indicated in Fig. 7. The electric field at time t1 peaks at the
p− body/n− drift junction located at a depth of 1.5 μm from the device
surface. The peak electric field at time t3 shifts to a depth of 8 μm,
which is where the recoil ions come to rest, and to the n− drift/n+
interface located at a depth of 10 μm from the device surface. In
addition, punch-through of the electric field occurs at the n+ source
diffusion region. This is due to the distribution of generated carriers
[20–24], caused by an increase in electron density in the vicinity of
the n− drift/n+ interface shown in Fig. 9.
The displacement current starts to flow by the movement of electrons
into the n− drift/n+ interface, at time t4 (see Fig. 7). Then, the dynamic
current induced by the impact ionization leads to and increase in the
lattice temperature. Fig. 10 compares the simulated lattice temperature
distribution at the time tf shown in Fig. 7 and a cross-sectional SEM
image of the SEB damage. The location of the peak lattice temperature
corresponds to the position of SEB damage.

Fig. 8. Electric field distribution along ion track at times indicated in Fig. 7: (a) overall view Fig. 10. Comparison between simulated lattice temperature distribution at times (tf)
and (b) near surface. indicated in Fig. 7 and cross-sectional SEM image of SEB damage.

Please cite this article as: T. Shoji, et al., Analysis of neutron-induced single-event burnout in SiC power MOSFETs, Microelectronics Reliability
(2015), http://dx.doi.org/10.1016/j.microrel.2015.06.081
 T. Shoji et al. / Microelectronics Reliability xxx (2015) xxx–xxx
Fig. 11. Simulated SEB currents and maximum lattice temperatures with and without n+
source diffusion region in SiC power MOSFET.
In order to determine the effect of parasitic npn transistor action on
SEB, device simulations were carried out for a SiC diode structure that
eliminated the n+ source diffusion region from the SiC MOSFET. Fig. 11
shows the simulated SEB currents and maximum lattice temperatures
with and without the n+ source diffusion region. An SEB current due to
CIA also flows in this diode structure. In addition, the SEB currents do
not differ much between the SiC diode and the MOSFET.
Finally, the maximum lattice temperature reaches the sublimation
temperature of SiC. An SEB can occur in the SiC diode without a
parasitic npn-transistor, through a shift in the peak electric field into
the n− drift/n+ interface and punch-through of the electric field to the
cathode at the device surface. The results in Fig. 11 indicate that parasitic
npn-transistor action contributes little to the SEB in SiC power MOSFETs.
Reducing the peak electric field and the density of heat generated reduces
the maximum lattice temperature. Therefore, an increase in the drift
thickness of SiC power MOSFETs is regarded as an effective way to
increase the SEB threshold voltage.
4. Conclusion
The triggering mechanism of single-event burnouts (SEBs) in SiC
power MOSFETs was studied by white neutron irradiation experiments
and device simulations. The location of the simulated peak lattice
temperature agreed closely with the position of the observed SEB
damage. It was found that the main mechanism triggering SEB in SiC
power MOSFETs is not parasitic npn-transistor action, but a shift in the
peak electric field and the punch-through at the n+ source diffusion
region, similar to the case for SiC power diodes.
Please cite this article as: T. Shoji, et al., Analysis of neutron-induced single-event burnout in SiC power MOSFETs, Microelectronics Reliability
(2015), http://dx.doi.org/10.1016/j.microrel.2015.06.081
5
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