Microelectronics Reliability 122 (2021) 114163

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Investigations of short-circuit failure in double trench SiC MOSFETs

through three-dimensional electro-thermal-mechanical stress analysis
Kailun Yao *, Hiroshi Yano, Noriyuki Iwamuro
Graduate School of Pure and Applied Sciences, University of Tsukuba, Tsukuba 305-8573, Japan

A R T I C L E I N F O A B S T R A C T

Keywords: In this study, the short-circuit failure mechanisms of 1.2 kV double trench SiC MOSFETs were investigated by
Mechanical stress experiment and three-dimensional numerical TCAD simulation. Damage at the gate interlayer dielectric was
Short-circuit failure mechanism confirmed as the cause of failure in the case of 400 V drain-source bias short-circuit transient. The three-
Trench SiC power MOSFETs
dimensional TCAD simulation results showed that the high level of mechanical stress could cause the struc­
Thermal runaway
Three-dimensional TCAD simulation
tural damage observed in the interlayer dielectric. Stress component analysis showed that tensile stress and shear
stress were the principal stresses that caused the damage. The typical thermal runaway failure caused by acti­
vation of bipolar characteristics at extremely high temperature was confirmed, by experiment and simulation, in
the case of the 800 V drain-source bias short-circuit transient. The three-dimensional simulation results indicated
that activation of the bipolar junction transistor initially occurred near the gate cross-corner, and then spread
throughout the entire cell.

1. Introduction
Owing to their excellent electrical and thermal properties, silicon
carbide (SiC) metal-oxide field-effect transistors (MOSFETs) have been
widely utilized in power electronic systems to replace their silicon
counterparts. SiC MOSFET features such as rapid switching speed, high
block voltage, low conductive resistance, and high thermal conductivity
can significantly reduce the power loss and systems volume. Therefore,
the performance of power systems can be greatly improved through the
utilization of SiC MOSFETs [1].
Applications such as electric vehicle motors and power trans­
formation systems require long-term trouble-free operation. As a
consequence, stringent requirements are proposed with regard to SiC
MOSFETs' reliability. Among the many fault mechanisms, the short-
circuit event is one of the harsh operating modes that can cause the
permanent failure of switching devices. SiC MOSFETs must endure high
electro-thermal stress during a short-circuit transient, without failure,
before the activation of the protection circuit. Various studies have re­
ported on the short-circuit characteristics of SiC MOSFETs. Most have
focused on electrical failure and degradation [2–8]. Recently, gate
shorting failure due to mechanical stress has been investigated. [9]
investigated SiO2 dielectric degradation in planar SiC MOSFETs after a
short-circuit transient, under varying temperature, drain-source voltage,
and gate-source bias; and revealed that structural damage at the gate
interlayer dielectric caused an increase in the gate-leakage and drain-
leakage current. In [10–13], the short-circuit failure modes at
different drain-source voltages, as well as the corresponding electro-
thermal analytical models, were summarized. It was found that at low
or medium drain-source voltage, gate shorting after the short-circuit
transient is a common failure mode. In [14,15], mechanical stress
analysis was performed for gate shorting failure in planar and asym­
metric trench SiC MOSFETs after a short-circuit transient. The results
indicated that the cause of failure was the filling of cracks with melted
source aluminum, due to the high mechanical stress at the gate inter­
layer dielectric. Gate shorting failure also occurred in double trench SiC
MOSFETs after a short-circuit transient [16].
In the aforementioned mechanical stress analysis cases [14,15], the
planar and asymmetric trench SiC MOSFETs had a stripe cell design,
which enables three-dimensional stress to be simplified to two-
dimensional stress in simulations. In contrast, the present study inves­
tigated the mechanical stress failure in double trench SiC MOSFETs, and
since these have a square unit cell design, three-dimensional electro-
thermal-mechanical simulation was here performed, for the first time, to
investigate short-circuit failure in SiC MOSFETs. A wide range of visu­
alized three-dimensional mechanical stress analysis, as well as failure
current analysis of the thermal runaway conditions, are presented.

* Corresponding author.
E-mail addresses: s2030060@s.tsukuba.ac.jp (K. Yao), yano.hiroshi.fn@u.tsukuba.ac.jp (H. Yano), iwamuro.noriyuki.fb@u.tsukuba.ac.jp (N. Iwamuro).

https://doi.org/10.1016/j.microrel.2021.114163
Received 21 November 2020; Received in revised form 7 April 2021; Accepted 11 May 2021
Available online 25 May 2021
0026-2714/© 2021 Elsevier Ltd. All rights reserved.
K. Yao et al. Microelectronics Reliability 122 (2021) 114163

Fig. 2. Short-circuit characteristics of the double trench SiC MOSFET at 400 V

DC bias: (a) drain voltage and drain current, (b) gate voltage.

Fig. 1. (a) short-circuit measurement equipment, (b) schematic of the equiv­

alent circuit; the gate resistance Rg was set at 47 Ω.

2. Short-circuit tests

2.1. Short-circuit characteristics at 400 V DC bias

The device under test (DUT) was a double trench SiC power MOSFET
(SCT3030AL; rated current, 70 A). The breakdown voltage of the DUT
was 1300 V, with a drain current (Id) of 1 mA, and can be used as 1.2 kV
class MOSFET. The specific on-resistance (Ron⋅A) was 2.8 mΩ⋅cm2 at Vgs
of 20 V. The gate threshold voltage was 4.1 V at Vds of 10 V and Id of 1
mA. The active area of the DUT was roughly 9.2 mm2.
Fig. 1 shows the test equipment setup and a schematic of the
equivalent circuit. The short-circuit characteristics of the DUT were first
investigated at 400 V. In order to avoid a turn-off surge current that may
result in an avalanche, the gate resistance Rg was set high, at 47 Ω, and
the gate bias was set at +15/− 4 V. The turn-on pulse width was
extended 0.1 μs per trial, until short-circuit failure occurred. Fig. 2(a)
shows the drain-source voltage Vds and drain current Id, and Fig. 2(b)
shows the gate-source voltage Vgs, during the short-circuit transient. Due
to the carrier mobility degradation at channel region and drift region
Fig. 3. Short-circuit characteristics of the double trench SiC MOSFET at 800 V
DC bias: (a) drain voltage and drain current, (b) gate voltage.
which was caused by the dominant thermally enhanced phonon scat­
tering at high temperature, the short-circuit current decreased contin­
uously after reached its peak, before the turn-off of the gate. Short-
circuit failure occurred when the short-circuit time TSC reached 20.4
μs. Initially, the gate voltage was biased to − 4 V, and the current was
successfully turned off. However, 4.2 μs after the turn-off, there was an
obvious voltage lift of ΔV = 1.3 V in the waveform of Vgs, which indi­
cated damage between the gate and source electrodes. An impedance
test was carried out after device failure, and the values of Rgs, Rgd and Rds

2
K. Yao et al.
Fig. 4. Top view of post failure chips surface [Active area: 9.18 mm2]: (a) after 400 V short-circuit test, (b) after 800 V short-circuit test.
Fig. 5. (a) OBIRCH illumination spot. (b) Top view of SEM image at the gate-
source shorting area, aluminum electrode was removed. The damage region is
marked by red arrows. Four Cutlines from (1) to (4) are selected to cut the FIB-
SEM cross-sectional images.
were 619 Ω, 0.8 MΩ and 3.7 MΩ, respectively. This indicated that the
shorting of Rgs caused the voltage lift in Vgs after the turn-off. Mean­
while, as shown in Fig. 2(a) the blocking capability of Vds and Id
remained.
2.2. Short-circuit characteristics at 800 V DC bias
The same type of device was then tested at 800 V drain-source DC
bias. For consistency with the 400 V short-circuit test, the gate resistance
Rg was set at 47 Ω and the gate bias at +15/− 4 V. Fig. 3(a) shows the
tested drain current Id and drain voltage Vds. The current reached a
maximum of 270 A during the short-circuit transient, and the appear­
ance of the current tail after the gate turn-off indicated bipolar charac­
teristics at a very high temperature. The failure of the device occurred
when the short-circuit time TSC reached 5.7 μs; at which point, the DUT
failed to turn off the drain current. The increase in uncontrollable short-
circuit current indicated thermal runaway failure. In the impedance test,
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Microelectronics Reliability 122 (2021) 114163
Rgs, Rgd, and Rds were 12.5 Ω, 13.1 Ω, and 0.8 Ω, respectively, indicating
that all three terminals were shorted to each other after the 800 V bias
short-circuit transient.
3. Short-circuit failure analyses
3.1. Post-failure chips examination
In order to further investigate the short-circuit failure mechanisms,
the post-failure MOSFETs were decapped by chemical etching. Fig. 4(a)
and (b) respectively show the surface of the chips after the 400 V and
800 V short-circuit tests. No obvious damage can be observed on the
chip surface after the 400 V short-circuit test (Fig. 4(a)); however, after
the 800 V short-circuit transient, burn-out marks are observable on the
source pad near the bonding wire (Fig. 4(b)). These marks indicate
extremely high temperature and sudden amplification of the drain
current, which are typical evidence of thermal runaway [16].
3.2. Failure detection in gate shorting MOSFET
As noted in Section 2.1, shorting of the gate-source electrodes caused
the failure in the 400 V short-circuit test. Optical beam induced resis­
tance change (OBIRCH) analysis was performed to detect the shorting
location. Then, focused ion beam-scanning electron microscope (FIB-
SEM) analysis was used to investigate the failure location based on cross-
sectional images of the damage region [15]. Fig. 5(a) shows the OBIRCH
illumination spot, and Fig. 5(b) shows a top-view SEM image of the
detected failure location, revealing the double trench SiC MOSFET's
square unit cell design, with the gate interlayer dielectric stripes cross to
each other. The damaged area (marked by the red arrows) is identified
as the gate-source shorting location. In comparison with the intact cells
shown on the right, a rough surface with protrusions can be observed in
the damaged area. In order to further investigate the failure area, Cut­
lines (1) to (4) (green dashed lines in Fig. 5(b)) were selected for FIB-
SEM cross-sectional images (shown in Fig. 6). Fig. 6(a) shows two in­
dividual cells. In the right cell, a conductive path exists in the valley
region of the gate interlayer dielectric, between the gate polycrystalline
silicon (poly-Si) and the source aluminum. Fig. 6(b) shows the obvious
damage to the gate interlayer dielectric at Cutline (2). Fig. 6(c) shows
that, at the gate side-wall of the left gate structure, a conductive path
directly connects the gate poly-Si to the source aluminum. Fig. 6(d)
further reveals the structural damage at the gate interlayer and gate
side-walls. The conductive paths between the gate poly-Si and the source
aluminum are the cause of the small Rgs value and lift in Vgs after the
gate turn-off in the 400 V short-circuit test.
K. Yao et al.
Fig. 6. FIB-SEM cross-sectional images from Cutline (1) to (4) at the damage region in Fig. 5. Two individual cells are shown in (a).
Fig. 7. Single cell MOSFET structure built in TCAD. (a) with source aluminum:
(A) source aluminum, (B) n- drift region, (C) n + substrate; (b) without source
aluminum to show the square unit cell structure: (D) crossed gate interlayer
dielectric, (E) gate poly-Si, (F) n + source, (G) protection trench and deep p
+ region.
4. Electro-thermal-mechanical TCAD simulation
Sentaurus TCAD simulation with coupled electro-thermal conditions
is used to investigate the short-circuit failure mechanism [17]. As
aforementioned, the double trench SiC MOSFET has a square unit (vs.
stripe) cell design; thus, simplifying the volume stress to 2D plane stress
may not reflect the mechanical stress distribution accurately. Therefore,
in the present study, a 3D device structure was used in the TCAD (Fig. 7).
The thickness and doping concentration of the drift region were set at 10
μm and 1.2×1016 cm− 3, respectively. The thickness of the gate oxide at
the trench side-walls and trench bottom was set at 60 nm and 70 nm,
respectively. The doping of the substrate was set at 1.0×1019 cm− 3, with
4
Microelectronics Reliability 122 (2021) 114163
Fig. 8. Top view of simulation structure as shown in Fig. 7(b). The cutlines
from (1) to (4) correspond to the cutlines marked in Fig. 5.
a thickness of 200 μm. The thickness of the source aluminum at the top is
set at 6 μm. The depth and doping concentration of the protection trench
were set at 1.5 μm and 1.0×1018 cm− 3, respectively. The channel length
was set at 0.3 μm. Figs. 8 and 9 show further geometric details of the
simulation structure. The positions of the cutlines in Fig. 8 correspond to
those in Fig. 5, and the cross-sectional structures in Fig. 9 correspond to
the FIB-SEM images in Fig. 6. The surface thermal contact at the drain
electrode was set at 0.04 K⋅cm2/W, based on the thermal resistance in
the datasheet. It is worth noting that the doping profile and geometric
settings in this study refer to previous simulation reports, and may not
match the actual structure perfectly, but can nonetheless reflect the
device characteristics. Physical models, including Shockley-Read-Hall
(SRH) recombination, temperature and high electric field-dependent
carrier mobility, incomplete ionization, thermodynamics model and
temperature-dependent intrinsic carrier density are considered in the
simulation.
4.1. 400 V short-circuit TCAD simulation
The simulated short-circuit current is compared with the measured
current in Fig. 10. Due to some approximations and assumptions in
K. Yao et al.
Fig. 9. Internal device simulation structure at Cutlines (1) to (4), as marked in Fig. 8, corresponding to the FIB-SEM cross-sectional images in Fig. 6.
Fig. 10. Simulated short-circuit current in comparison with the measured
current at 400 V DC bias. The respective maximum temperatures of SiC in the
drift region and Al in the source region are shown on the same time scale.
simulation, the simulated short-circuit current is not perfectly consist
with the measured results, but can still reflect the short-circuit charac­
teristic in a real MOSFET. The respective simulated maximum temper­
atures of SiC in the drift region and aluminum in the source region are
shown on the same time scale. The maximum temperature of the SiC and
aluminum reaches 1477 K and 1378 K, respectively. It is worth noting
that the simulated temperature in the source region is far beyond the
melting point of aluminum (933 K). Fig. 11(a) and (b) show the current
and temperature distribution, respectively, at time T1, as marked in
Fig. 10. The current path shows that the parasitic bipolar junction
transistors were still inactive, and the high-temperature region was
under the gate trench.
4.2. Mechanical stress simulation for 400 V short-circuit
The simulated temperature distribution profiles are imported to
Sentaurus Interconnect, and the mechanical stress is simulated. In Sen­
taurus Interconnect, the bottom edge of the structure is fixed, as the chip
is fixed on solder under actual conditions, but the other edges are set to
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Microelectronics Reliability 122 (2021) 114163
be free. The volume of the simulation structure at 300 K is set as the
reference volume. Then, the temperature is ramped up to the target
temperature, which corresponds to the calculated temperature distri­
bution in Sentaurus Device. As the temperature is ramped up, the vol­
ume mismatch is calculated by using the different temperature-
dependent coefficients of thermal expansion of SiC, poly-Si, silicon di­
oxide (SiO2), and aluminum. The mechanical properties of the different
materials used in the stress simulation shown in Table 1 were taken from
previous studies [18–21]. Fig. 12(a) shows the simulated von Mises
stress distribution at 8 μs, 12 μs, 16 μs, and 20 μs, during the short-circuit
transient (see Fig. 10) and Fig. 12(b) shows the comparison between the
original structure and the structure deformation by 30 times at 20 μs.
High-level mechanical stress and displacement are found to be concen­
trated at the gate interlayer dielectric. At the end of the short-circuit
transient, the von Mises stress value reaches as high as 2 GPa, which
excessed the fracture strength of SiO2 film [21]. Fig. 13(a) shows the
vertical stress along the X-axis, with positive values indicating tensile
stress, and negative values indicating compressive stress. It shows that
the concentration of high-value tensile stress occurs on the left and right
sides of each gate interlayer stripe. Fig. 13(b) shows the 2D vertical
stress distribution at Cutline (4) (see Fig. 8). High-level tensile stress
could cause damage in the interlayer dielectric in those regions (see
Fig. 6(d)). Fig. 14(a) shows the simulated horizontal stress along as the
Y-axis, with the same positive and negative value indications as for
vertical stress. Fig. 14(b) shows the 2D horizontal stress distribution at
Cutline (1) (see Fig. 8). The results show that tensile stress occurs in the
valley region of the gate interlayer dielectric, and high-level compres­
sive stress occurs at the sides of the gate interlayer dielectric. The
maximum tensile stress (over 500 MPa), which excesses the tensile
strength of SiO2 film [21], is concentrated in the valley. The damage
shown in Fig. 6(a) could be caused by this tensile stress in the valley
region.
Fig. 15(a) shows the shear stress distribution on the XY face, with the
positive values indicating shear stress acting in the + Y of the plane
normal to the X-axis, and negative values indicating shear stress acting
in the – Y direction. Fig. 15(b) shows the 2D shear stress distribution at
Cutline (3) (see Fig. 8). We can see that high-value shear stress of
K. Yao et al.
Fig. 11. Simulation results at T1, as marked in Fig. 10: (a) simulated current distribution, (b) simulated temperature distribution.
Table 1
Thermal expansion coefficients in the mechanical simulation.
Unit SiC [18] SiO2 Poly-Si [19]
− 6
(× 10 /K) 2.2–4.9 0.5 2.6–4.6
roughly 300 MPa occurs on the left and right side of the gate side-walls,
suggesting that the damage shown in Fig. 6(c) could be caused by shear
stress acting on the gate side-walls.
The structural damage to the gate interlayer dielectric (see Fig. 6)
was caused by mechanical stress, due to the thermal volume mismatch of
different materials at high temperature. Also, it seems like the damages
need time to form, as the time delay of failure shown in Fig. 2(b). The
specific causes of multiple forms of damage due to different stress
components in different regions remain to be investigated in further
studies.
4.3. 800 V short-circuit TCAD simulation
The simulated and measured short-circuit characteristics at 800 V DC
bias are shown in Fig. 16. The respective simulated maximum temper­
atures of SiC in the drift region and aluminum in the source region are
shown on the same time scale. Due to approximations and assumptions
Microelectronics Reliability 122 (2021) 114163
in the device modeling, the simulated short-circuit current is not
perfectly consistent with the measured results at extremely high tem­
Al [20] perature. However, the overall pattern of the simulated current reflects
the measured results. Therefore, the simulation results can basically
23.8–31.1
reflect the actual situation inside the devices during the short-circuit
transient. As shown in Fig. 4(b), the chip surface was completely
burned out after the 800 V short-circuit test. The simulated maximum
temperature in the drift region is over 1800 K, which could reach the
intrinsic temperature of SiC [22]. After the increase in the uncontrol­
lable current, the temperature of the SiC and aluminum rapidly reaches
over 2000 K due to the huge power dissipation. Fig. 17(a) shows the
current distribution at time T2 (as in Fig. 16), when the npn bipolar
junction transistors of the SiC MOSFET are triggered. Cut-face C1 (at a
depth of 0.25 μm from the SiC-Al interface) near the n + region along the
YZ face was used to determine where the parasitic BJT was initially
triggered. Fig. 17(b), which shows the current density on the C1 face,
reveals that the current density is higher near the corner of the gate
region than in other regions, indicating that the parasitic BJT is initially
activated at the cross-corner near the gate. Fig. 17(c), which shows the
temperature distribution on the C1 face, reveals that the higher tem­
perature is concentrated at the center of the cell, with the logical
consequence that such higher temperatures are more likely to be the
cause of the parasitic BJT activation. Figs. 18(a) and 18(b) respectively
show the temperature and current distribution at time T3, as marked in
Fig. 16. Complete activation of the parasitic BJT can be confirmed. In
6
K. Yao et al. Microelectronics Reliability 122 (2021) 114163

Fig. 14. Simulated horizontal stress component along the Y-axis during the
400 V short-circuit transient: (a) 3D horizontal stress distribution, (b) 2D hor­
izontal stress distribution at 20 μs, and the actual damage to the gate structure
of the right cell in Fig. 6(a).

Fig. 12. (a) Simulated von Mises stress during 400 V short-circuit transient, (b)
deformation 30 times at 20 μs.

Fig. 15. Simulated shear stress component along the XY face during the 400 V
short-circuit transient: (a) 3D shear stress distribution, (b) 2D shear stress dis­
tribution at 20 μs, and the actual damage to the gate structure of the right cell in
Fig. 6(c).
Fig. 13. Simulated vertical stress component along the X-axis during the 400 V
short-circuit transient: (a) 3D vertical stress distribution, (b) 2D vertical stress
distribution at 20 μs, and the actual damage to the gate structure of the right
cell in Fig. 6(d).

7
K. Yao et al.
Fig. 16. Simulated short-circuit current in comparison with the measured
current at 800 V DC bias. The respective maximum temperatures of SiC in the
drift region and Al at source region are shown on the same time scale.
addition, according to the simulation results, the intrinsic carrier density
near the pn junction at body-contact reaches 3×1017 cm− 3 at such a high
temperature, which already exceeds the background doping density in
the drift region. As a result, the pn junction near the body-contact region
begins to lose functionality due to the high density of background
Fig. 17. Simulation results at T2, marked in Fig. 16: (a) simulated current distribution, (b) simulated current density at Cut-face C1 as marked in (a), (c) simulated
temperature at Cut-face C1 as marked in (a).
8
Microelectronics Reliability 122 (2021) 114163
intrinsic carriers at extremely high temperature. Further, when the lat­
tice temperature is over 1800 K, the build-in voltage of the p− base/n+
source junction would drop below 0.26 V, and the threshold voltage
would also drop at such high temperature. These factors could increase
the probability of the parasitic BJT being activated, resulting in the
electrical characteristics of the MOSFET being more similar to a
normally-on device. In sum, the short-circuit failure at 800 V DC bias
was caused by the activation of bipolar characteristics.
5. Conclusion
In this study, the short-circuit failure mechanisms of double trench
SiC MOSFETs were investigated, at 400 V and 800 V drain-source DC
bias, by experiment and three-dimensional numerical TCAD simulation.
Gate to source shorting caused by damage to the gate interlayer
dielectric was the reason for the 400 V short-circuit failure, with FIB-
SEM analysis revealing conductive paths between the gate poly-Si and
the source aluminum. The three-dimensional electro-thermal-mechani­
cal simulation showed that high-level mechanical stress concentrated at
the gate interlayer dielectric was the cause of the structural damage. The
stress components were also investigated. The vertical tensile stress on
the left and right sides of each gate interlayer dielectric and the
K. Yao et al.
Fig. 18. Simulated results at T3, as marked in Fig. 16 (a) simulated current distribution, (b) simulated temperature distribution.
horizontal stress in the dielectric valley, along with shear stress on the
gate side-walls, were the principal stresses causing the damage. In the
800 V short-circuit failure, the typical thermal runaway failure mode
was confirmed to be the concentration of high current density near the
gate cross-corner, followed by activation of the parasitic BJT and the loss
of pn junction functionality near the body-contact at extremely high
temperature.
CRediT authorship contribution statement
Kailun Yao: Methodology, Software, Simulation, Writing- Original
draft preparation.
Hiroshi Yano: Supervision.
Noriyuki Iwamuro: Supervision.
Acknowledgement
The authors would like to express special thanks to Dr. Y. Yamashita
of Toyota Central R&D Laboratories Inc., and the technical support staff
of Sentaurus Device and Sentaurus Interconnect from Synopsys Inc., for
their support in this study.
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