ECE 247

Modern Semiconductor Devices

MOS SYSTEM DEFECTS

Presented By :- Harshitha Ramesh
Sakshi Bhide

Course Advisor :- Dr. Zoulika Mouffak

Introduction
• The single most important technology for electronic device fabrication relies on the
metal-oxide-silicon (MOS) system[3].
• Defects in the oxide lead to shifts in threshold voltage in MOSFET’s. Also, the residual
unpassivated defects at the Si/SiO2 interface are responsible for decreased surface
mobility, and for “soft” threshold characteristics[3].
• While some defects are inherent, i. e. arise from differences in the thermal
expansion coefficients of silicon and silicon dioxide, and from lattice-network
mismatch, most exist due to ionizing radiation or hot-electron injection[3].
• They can be created during fabrication (during X-ray lithography, or during the
various plasma-assisted etching steps), or they can be a result of exposure to a space
environment where even a modest flux of gamma rays can cause dramatic changes
in device characteristics[3].

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 General defects in MOS System

Process Related Inherent Material Defects

• Oxide Defects • Crystal Lattice
• Gate Contamination • Interface Trap
• Doping • Electron / Hole Defects

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SiC MOSFET
• The traditional Si MOSFET power devices are restricted by the
properties of Si Materials and cannot meet the needs of the current
market. Therefore, the third-generation wide band gap
semiconductor. SiC MOSFET power device with better performance
has attracted extensive attention [1]

Table 1
Physical properties (room temperature values) of wide-bandgap
semiconductors for power electronic applications in comparison with
conventional semiconducting materials. [3]
[1]

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Basic Characteristics
(1)Transfer characteristics (2)Output characteristics

Fig 2.
[1]
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(3)Blocking characteristics
When there is no applied voltage on the gate or the connected applied power supply is a negative
potential, the SiC MOSFET is turned off. At this time, if a positive voltage is connected at the drain
port to make its potential higher than the source, the PN junction formed by the contact between the
base region dominated by holes and the drift region dominated by electrons will be in the reverse bias
state, which is approximately infinite resistance[1].
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 Characteristic Analysis
• Body Effect
When SiC MOSFET devices work in the third quadrant, that is, a positive voltage is applied to the
source, the potential of the source port is higher than that of the drain port and the phenomenon of
threshold voltage reduction is called body effect. When SiC MOSFET devices work in the third
quadrant, the current flows from the source to the drain when the source voltage exceeds the drain
voltage. At this time, the source and the base are connected, which can be considered a short circuit.
Therefore, the voltage of the P+ base area is higher than the voltage of the drain and equal to that of
the source.[1]
• BTI Characteristics
When SiC MOSFET is in an environment with high electric field strength, the gate oxide layer will leak
current, which will lead to quantum effects, and then cause Flower-Nordheim (F-N) type tunnel
current [8]. When the generated tunnel current flows inside or at the boundary of the gate oxide
layer, no matter whether the carrier in the current is an electron or a hole, it will be captured by the
three types of traps of the electron, hole, and neutral in the gate oxide layer, and the trapped carriers
will continue to accumulate charges in the traps. Finally, due to the accumulation of a large number of
charges in the trap, the local electric field near the trap will be greatly enhanced. If the local electric
field continues to increase beyond a certain limit value, the gate oxide will break down, causing
performance degradation of the gate oxide[1] 6
Defect engineering in SiC MOSFET
• Operation of normally-off MOSFETs is based on carrier accumulation
and transport through the MOS channel and, thereby, carrier trapping
at interface defects and carrier scattering dominate the VT stability
and channel mobility[2].
• Researchers focus on defect engineering strategies to intentionally
control and manipulate defects in a controlled manner. This approach
aims to enhance device performance by utilizing specific defect types
for beneficial purposes[2].

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• High-resolution TEM studies reported several-nm thick transition layers with extremely high excess
carbon impurities (∼20%) and structural imperfection on the SiC side of the interface.
• Based on the ion scattering technique pointed out an abrupt and near-perfect stoichiometric SiO 2/SiC
interface and ruled out formation of a thick transition layer at the interface[2].

Fig.4 Synchrotron XPS analysis of cleaned and oxidized SiC(0001) surfaces: (a) change in Si 2p core-level spectra with progress of
dry oxidation at 1100 °C, (b) curve fitting of Si 2p3/2 core level with bulk SiC and SiO2 signals and intermediate oxide states for
SiO2/SiC structure prepared with 10 min oxidation (corresponding to 3.5 nm thick SiO2), (c) change in total amount of intermediate
states in Si 2p3/2 spectra from oxidized SiC surfaces, in which the intensity ratio between the intermediate states and the bulk
signal is plotted as a function of oxidation time. [2] 8
• Fig 5.(a) Summary of electrical properties of SiC MOS capacitors fabricated by dry oxidation at 1100 °C. The
horizontal axis represents the oxide thickness determined from the measured maximum capacitance. The
vertical axis represents Vfb and Dit estimated from the C–V characteristics, in which Dit was estimated.[2]

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Interface Effect in Sic MOSFET
• The interface effect in Silicon Carbide (SiC) MOSFETs describes the
influence that the interface between the SiC and the gate oxide
(usually SiO2) has on the device's electrical properties. There are a
number of important parameters that this interface can significantly
affect.

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 Parameters affected by Interface effect
• Threshold voltage: The gate voltage necessary to turn on the device may shift because of
the interface effect. Interface traps or fixed charges at the interface may be the cause of
this shift.
• Channel mobility: The mobility of the charge carriers in the channel can be decreased by
interface traps acting as scattering centers. This may cause the device to have a higher on-
resistance and a lower drain current.
• Transconductance: The ability of a device to convert gate voltage to drain current is
measured by its transconductance. Through a shift in the threshold voltage or a decrease
in channel mobility, the interface effect can lower transconductance.
• Reliability: The device's long-term dependability may also be influenced by the interface.
Stress can cause interface traps to deteriorate, which can increase leakage current and
reduce functionality.

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Parameters affected by Interface effect
• Increased Gate Capacitance : In parallel with the gate oxide capacitance, interface traps function
as extra capacitive elements. These traps catch electrons when a positive bias is applied to the
drain, which increases the build-up of charge at the interface. Consequently, the total gate
capacitance rises as a result, especially at low and medium frequencies.
• Frequency Dependence of Gate Capacitance : There is a limited rate at which electrons are
captured and released by interface traps. The effective gate capacitance decreases as the
measurement frequency rises because the traps can't follow the AC signal quickly enough.
Because they can catch and release electrons more easily, traps situated closer to the SiC
conduction band edge exhibit a greater frequency dependence.
• Gate Capacitance Hysteresis : The trapped electrons in interface traps are not instantly released
when the gate voltage is swept in one direction and then reversed. As a result, the measured gate
capacitance versus gate voltage curve exhibits a hysteresis loop. The energy distribution and trap
density determine the hysteresis loop's size.

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Testing Methods for Detecting MOSFET Defects
(Deep Level Transient Fourier Spectroscopy (DLTFS) )
• The versatile technique known as Deep Level Transient Fourier
Spectroscopy (DLTFS) is used to investigate electrically active defects
in semiconductor structures.
• It offers details on the capture cross-section, the defect densities, and
where they are located within the energy gap. This analysis is a crucial
component of the research because it facilitates continuous device
improvement and growth.

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Mitigation methods for Interface Effect on
Sic MOSFET
• Superior oxide growth
• Nitridation
• Surface cleaning
• Annealing
• Gate electrode material selection
• Channel doping
• Reduced gate oxide thickness
• Field-plate structures
• Gate current limitation
• Post-fabrication hydrogen passivation
• In-situ hydrogen passivation
• Developing accurate models
• Utilizing simulation tools
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Conclusion
• The defects is MOS system was presented. A more focused working of
SiC MOSFET and its operation and defects were discussed. Apart from
the defects, it’s effect on the properties of the device and mitigation
strategy was presented.

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Further Reading
• Edwards, A.H. , “Theory of Defects in the MOS System. In: Helms, C.R., Deal, B.E.
(eds) The Physics and Chemistry of SiO2 and the Si-SiO2 Interface,” Springer,
Boston, MA.
• Shaker, Hesham H et al. “Improved Buildup Model for Radiation-Induced Defects
in MOSFET Isolation Oxides.” arXiv.org (2020)
• Berens, Judith et al. “Detection and Cryogenic Characterization of Defects at the
SiO2/4H-SiC Interface in Trench MOSFET.” IEEE transactions on electron devices,
2019.

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References
1. J.Yao, “Working principle and characteristic analysis of SiC MOSFET,” Journal of
Physics: Conference Series, 2023.
2. Tsunenobu Kimoto and Heiji Watanabe, “Defect engineering in SiC technology
for high-voltage power devices, Appl. Phys, 2020.
3. Chaturvedi, M, Haasmann, D. Moghadam, H.A, Dimitrijev, S, “Electrically Active
Defects in SiC Power MOSFETs” Energies, 2023.
4. K. Ni et al., "Electrical Effects of a Single Extended Defect in MOSFETs," in IEEE
Transactions on Electron Devices, vol. 63, no. 8, pp. 3069-3075, Aug. 2016.
5. Chen PC, Miao WC, Ahmed T, Pan YY, Lin CL, Chen SC, Kuo HC, Tsui BY, Lien DH.
“Defect Inspection Techniques in SiC. Nanoscale Res Lett”, 2022.
6. J. F. Zhang et al., "Defect loss and its physical processes," 2020 IEEE 15th
International Conference on Solid-State & Integrated Circuit Technology
(ICSICT), Kunming, China, 2020.

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