Transactions on Electrical and Electronic Materials Online ISSN 2092-7592

https://doi.org/10.1007/s42341-020-00222-y Print ISSN 1229-7607

REVIEW PAPER

A Journey from Bulk MOSFET to 3 nm and Beyond

Asharani Samal1 · Suman Lata Tripathi2 · Sushanta Kumar Mohapatra1 

Received: 7 January 2020 / Revised: 1 June 2020 / Accepted: 27 June 2020

© The Korean Institute of Electrical and Electronic Material Engineers 2020

Abstract
To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction,
polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work
function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional
planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in
the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s
law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles.
Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to
continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or
2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node.
In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research
to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of
Moore’s law, and bring the miniaturization back in the track.

Keywords  Scaling · Scaling challenges · Bulk MOSFET · SOI device · High-k · High-k metal gate · DG-MOSFET · TFET ·
FinFET · GAAFET · CFET · Vertical FET · NCFET · Nonsilicon channel materials

1 Introduction resulted in consistent improvement in both device density

The breakthroughs in this electronic era are due to the
advancement of semiconductor technology. The technol-
ogy manifested the prediction by Gordon Moore in 1965
i.e. the number of transistors per chip will double every
2 years [1–5]. The increased demand for battery-operated
portable devices has necessitated the requirement of high
speed, lower power, and compact devices. The downscal-
ing of the physical size of the device known as scaling has
and performance over many technology generations.
The device scaling benefitted the semiconductor industry
in terms of
• Faster-operating speed as the electrons have to move a
lesser path from source to drain.
• Cheaper circuit design due to the integration of large no
of transistors on a single chip.
• Lesser dynamic power due to lower capacitance of the
smaller transistor.

The Metal Oxide Field Effect Transistor (MOSFET) scale

* Sushanta Kumar Mohapatra down to a small size was provided by Dennard, reached its
skmctc74@gmail.com
limit, thus began the ‘equivalent scaling’ era of the past two
Asharani Samal decades [6].
asharani.samal@gmail.com
With every new technology node (a node is a genera-
Suman Lata Tripathi tion of semiconductor process parameters associated with
tri.suman78@gmail.com
the size) performance, cost and dynamic power have been
1
School of Electronics Engineering, KIIT University, improved, but it has resulted in short channel effects (SCEs).
Bhubaneswar, Odisha, India With the scaling of channel length (­ Lg), at higher drain volt-
2
School of Electronics and Electrical Engineering, Lovely age the barrier height for electrons to move from source to
Professional University, Jalandhar, India

13
Vol.:(0123456789)

drain, which should be ideally controlled by gate voltage
­(Vg), is also affected by drain voltage (­ Vd) thus reduces the
gate controllability over drain current (­ Ion), which results
in drain induced barrier lowering (DIBL) and degradation
of (that is, an increase) subthreshold slope (SS). These two
effects are additive, and both increase the leakage current
­(Ioff) of the transistor. DIBL is an effect that causes a reduc-
tion in the threshold voltage ­(Vth) as the channel length
reduces [7]. The reduction of ­Vth due to DIBL is commonly
known as V ­ th roll-off [8]. The classical solution to prevent
SCE in conventional MOSFET is to increase the electrostatic
control by reducing gate oxide thickness (­ tox) in proportion
to ­Lg without capacitance degradation [7]. However thinning
of ­tox i.e. Silicon dioxide (­ SiO2) which has served as the tran-
sistor gate insulator, since the emergence of MOS devices
beyond a certain limit (0.8 nm) resulted in intolerable direct
tunneling current which increased the ­Ioff [9–14] As scal-
ing of planar CMOS has faced significant challenges, new
device structures, and new materials are explored to prevent
the issues because of downscaling of MOSFET dimension
i.e. to reduce the SCEs like DIBL, sub-threshold conduction
(Increase in ­Ioff), degradation of SS and ­Vth roll off [15–17].
The paper gives a roadmap of various engineering
invented in order to reduce SCEs in shorter channels. The
Engineering fall into categories like Gate Dielectric Engi-
neering, Gate Material Engineering, and Device Engineer-
ing, Channel Engineering etc.
This paper is divided into seven main sections. Section 2
discusses the challenges faced by bulk planar MOSFET due
to ­Lg scaling. Section 3 focuses on the Silicon on Insulator
(SOI) and its advantage and disadvantage over bulk MOS-
FET in regard to scaling. Section 4 gives an idea about the
limitation of S ­ iO2 as the gate dielectric and the evolution of
high k gate dielectric. Section 5 gives the need of transition
from polysilicon gate to metal gate. Section 6 gives the idea
of transition from planar structure to non-planar structure.
Section 7 discusses FinFET. Section 8 discusses the about
GAAFET which will replace FinFET and Sects. 9–13 gives
Poly Silicon
SiO2
Gate Oxide
Source Channel Drain
Silicon Substrate
(a)
Fig. 1  a Layout of bulk planar conventional MOSFET, b illustration of barrier faced by electrons from source to drain
13
Transactions on Electrical and Electronic Materials
an idea about next-generation transistors. Section 14 gives a
pictorial representation of the technology trend. Section 15
concludes the paper.
2 Bulk MOSFET and Its Challenges
In conventional MOSFETs with long channel technology,
the transistor characteristics were at par with the required
speed and power requirements [7]. However, with shortening
of ­Lg various SCEs came into the picture such as
1. Increase in ­Ioff
2. Degradation of SS
3. DIBL
4. Threshold voltage ­(Vth) variations
Figure 1 shows the layout of bulk MOSFET and the bar-
rier faced by the electrons to move from source to drain. A
simulation was carried based on the device parameter [18]
in Fig. 2 to verify SCEs. Here the bulk MOSFET for gate
length ranging from (90 to 2000 nm) is considered that is
from micro to nanoscale. It is observed from Fig. 2a that the
­Ioff increases from ­10−8 to 50 µA with decreasing the ­Lg. An
increase in I­ off was a concern for device’s power consump-
tion. In Fig. 2b gives the ideal about the higher SS (un-
natural) drastically below 500 nm of ­Lg.
3 SOI Technology: A Device Engineering
In this electronic era, power-saving hence low leakage is
more crucial than random speed increase. Unfortunately,
drive current ­(Ion) increases with each new generation of
the transistor, but it also results in a threefold increase in
subthreshold leakage (­ Ioff), which would increase power
consumption [19]. To get rid of those significant leakages
Gate
Cg Oxide
Source
Source Channel C Drain
Drain
Source
dg
C
Silicon Substrate
(b)
Transactions on Electrical and Electronic Materials

away from the channel surface such as source-to-drain or
subthreshold leakage from the channel surface, one of the
device engineering technology concepts came into the pic-
ture that is SOI [19–21]. These SOI devices fall into two
categories, as shown in Fig. 3: if the thickness of silicon
film ­(tsi) is larger than the Source/Drain depletion width,
then the channel region is partially depleted called par-
tially depleted (PD) SOI device. If t­si is thinner than the
depletion width, then the channel region under the invert-
ing layer is fully depleted called a fully depleted (FD) SOI
device.
In SOI transistors, the higher mobility results in a sig-
nificant increase in ­Ion over a conventional substrate [22].
The reduced parasitic junction capacitances in SOI devices
also drives the I­ on and enable them to be high-speed devices
over their bulk silicon counterparts [23]. The reason for the
reduction of junction parasitic capacitance is due to the fact
that in bulk devices, there are two components of parasitic
capacitance, whereas in SOI devices its only one is depicted
in Fig. 4. Thus SCE is well suppressed in a MOSFET fabri-
cated on a silicon-on-oxide (SOI) than bulk-silicon devices.
It is found that thinner the SOI layer is, the more the SCEs
are suppressed.

Fig. 2  a ­ID–VGS characteristics of bulk planar conventional MOSFET, b subthreshold slope as a function of gate length for ­VDS = 1.5 V

Fig. 3  The layout of SOI

planar conventional MOSFET a Source Poly Silicon Drain Gate
Depletion Width Depletion Width Source
FDSOI, b PDSOI Drain
Gate Oxide Depletion Width Gate Oxide Depletion Width
Source Drain Source Drain
Channel Channel
Buried Oxide ( SiO2) Buried Oxide ( SiO2)

Silicon Substrate Silicon Substrate

(a) (b)

Gate oxide Gate oxide

Source Field Implant Drain Source Field Implant Drain

Buried Oxide
Substrate
Substrate
(a) (b)

Fig. 4  Parasitic junction capacitance component a Bulk, b SOI MOSFET

13

Moreover, SOI MOSFETs are low power devices for
its lower inverse subthreshold because it allows the use of
devices with a smaller value of threshold voltage without an
increase in leakage current as compared to bulk devices in
the case of long gate lengths [24]. This reduces static power
consumption significantly. Beyond 32 nm technology, thin
SOI multi-gate devices are very attractive due to their excel-
lent electrostatic control in addition to enhanced transport
properties [25, 26].
The TCAD simulation for the advantage of SOI over bulk
MOSFET is illustrated in Fig. 5 with the considered device
dimensions. It is evident that SOI technology provides high
­Ion and lower SS (which is nearly equal to the typical value
that is 60 mV/decade).
Although SOI devices offer many benefits, it also brings
in few reliability issues like self-heating due to poor heat
dissipation [23], hot-electron degradation due to thin-film
effects [23] and the existence of two interfaces and floating
body effect in PD-SOI devices [23].
4 High‑k: Gate Dielectric Engineering
4.1 Gate Dielectric Scaling
As we go down in technology nodes, in order to increase the
performance when the transistor is on and to reduce sub-
threshold leakage when the transistor is off or in other words
to reduce SCEs ­tox has to be reduced in proportion to L ­ g in
order to increase electrostatic control over channel [19]. The
reason to reduce t­ ox is to get a larger oxide capacitance hence
an increased on-current (­ Ion) and also to control threshold
voltage roll-off (∆Vth) (and therefore the subthreshold leak-
age) in the reducing channel length. The increase of on cur-
rent with reduction of t­ ox can be explained with Eqs. 1 and 2:
Fig. 5  Comparison of Bulk and SOI MOSFET a ­Ion, b SS with respect to ­Lg
13
Transactions on Electrical and Electronic Materials
A
COX = k𝜀0 (1)
d
1 W
IDS = 𝜇COX (VGS − VTH )2 (2)
2 L
where k is the relative dielectric constant, Ɛ0 is the permit-
tivity of the free space, A is the product of ­Lg and W where
­Lg is the channel length, W is the channel width, and d is the
thickness of gate oxide. Thus both lateral dimension (litho-
graphic feature sizes) and vertical dimensions (gate oxide
thickness and junction depth) should be reduced to increase
the packing density of devices while avoiding SCE.
As shown in Fig. 6 the reduction of dielectric thickness
has resulted in the improvement of DIBL, which is the root
cause of SCE [7]. DIBL is calculated as per Eq. 3:
ΔVth V − Vth2
DIBL = = th1 (3)
ΔVDS VDS1 − VDS2
However, around the year 2003 at 90 nm generation at t­ ox of
1.2 nm it was realized that it is no longer possible to shrink
it further as the oxide had hit its five-atom limit. Beyond
1.2 nm ­SiO2 started to lose its insulating properties and
began to leak current as shown in Fig. 6. This is due to
the quantum mechanical phenomenon of electrons [19] and
this leakage current was the most limiting factor as it was a
source of undesirable heat; hence was drainage on the power.
4.2 The High‑k SOI MOSFET
The favorable oxide material S ­ iO 2 has served as the
transistor gate insulator since the emergence of MOS
device. In the conventional MOSFETs when ­tox shrinked
beyond 1.2 nm, the industry needed a significant innova-
tion to maintain performance while controlling SCEs and
power in advanced technologies as ­S iO 2 started to lose
Transactions on Electrical and Electronic Materials

Fig. 6  Effect of oxide thickness on SCEs a DIBL, b leakage current (­ Ioff) with respect to dielectric thickness ­(tox)

its dielectric properties. Thus there was the need to find

a gate dielectric that can be replaced with ­S iO 2, which Poly Silicon
was thick enough to prevent direct tunneling of electrons
High-k
through it, and yet it should be permeable enough for the Thicker Dielectric
electric field of the gate to enter into the channel. Thus Gate Oxide
the solution was to use a dielectric material that has a
Source Channel Drain
higher dielectric permittivity than ­SiO2, which was called
high-k dielectric [27]. As per the concept of equivalent
oxide thickness (EOT) a high-k gate dielectric can store Buried Oxide ( SiO2)
more charge due to capacitance rise because capacitance is
directly proportional to the dielectric constant of the mate- Silicon Substrate
rial Thus to lower leakage current a thicker insulator can
be used which can provide same capacitance or it can be
Fig. 7  The layout of high-k SOI transistors
used to store more charge for the same thickness of insu-
lator [14, 19, 28–30]. The EOT refers to the thickness of
any dielectric scaled by the ratio of its dielectric constant
to that of ­SiO2 ­(kSiO2) [31] and can be expressed as Eq. 4:
3.9
EOT = tHi−k (4)
k
where ­tHi-k is the physical thickness of the high-k gate dielec-
tric material, and k is its dielectric constant, for e.g. a gate
dielectric with k value of 12 can be almost thrice as thick
as ­SiO2 gate insulator, while capacitance per unit area value
remains same so as to maintain same electrostatics [32]
The layout of high-k MOSFET is shown in Fig. 7. The high-
k MOSFETs reduced the leakage current to a great extent as
shown in Fig. 8, but it exhibited trapped charge problem [31,
33]. Among the dielectrics as given in Table 1 whose dielectric
constant ranges from 10 to 30, the most favorable material
considered for the replacement of ­SiO2 is ­HfO2 [Dielectric
constant: ~ 20] because of its merit in-band offset, thermal
stability and better electrical characteristics [31, 34–37]. The
trapped-charge problem also eliminated in ­HfO2. Fig. 8  ID–VGS characteristics of SOI high-k devices to show Fermi
level pinning and mobility degradation

13
 Transactions on Electrical and Electronic Materials

Table 1  Dielectric materials [12]

Dielectric Dielectric constant

Silicon dioxide-(SiO2) 3.9

Silicon nitride-(Si3N4) 7
Aluminium oxide-(Al2O3) ~ 10
Tantalum pentoxide-(Ta2O5) 25
Lanthanum oxide-(La2O3) ~ 21
Gadolinium oxide-(Gd2O3) ~ 12
Yttrium oxide-(Y2O3) ~ 15
Hafnium oxide-(HfO2) ~ 20–25
Zirconium oxide-(ZrO2) ~ 23

There were some other downside observed in high-k MOS-

FETs like “Fermi level pinning” problem, that is the increase
in the threshold voltages means more voltage required to turn
on the MOSFET transistor [38]. Severely degraded channel
mobility observed, which slowed down device’s switching
speed [15]. These two demerits were represented in Fig. 7
using TCAD simulation. Researchers found out that the source
of trouble was the interaction between the high-k gate dielec-
trics and polysilicon gate electrode [19].
Also, direct use of high-k gate material on silicon wafer
resulted in weaker electrostatics due to the fringing fields from
the gate to the source/drain regions that enhance the electric
field into the channel, thus increasing SCE. This might happen
due to the reason that dielectric thickness became comparable
to the gate length [39]. This issue was taken care by a stacked
gate structure in which high-k dielectrics is used over an extra-
thin ­SiO2 layer, which ultimately improves the interfacial qual-
ity and stability [39] as shown in Fig. 9. The overall EOT is
given by Eq. 5:
𝜀1
EOT = tSio2 + EOTHi−k = t1 + t2 (5)
𝜀2
In 65  nm high-k transistors, although direct tunneling
through the gate, significantly reduced but it introduced
other issues. Those issues were later solved by incorporat-
ing new deposition techniques and the replacement of poly-
silicon with metal gates [40]. These added features allowed
further scalability hence opened the doors for the 45 nm
technology [19].
5 The High‑k Metal Gate Transistor
(HKMG)‑Gate Electrode Engineering
The dielectric layer issues were due to the interaction between
polysilicon and high-k dielectric. In a dielectric, there is the
vibration of dipoles and this vibration causes strong vibrations
in a semiconductor’s crystal lattice, called phonons. These
phonons slow down the channel electrons due to scattering
Fig. 9  Gate stack architecture
and reduce the switching speed of the transistor. However,
increasing the density of electrons in a gate electrode can
minimize the influence of dipole vibrations on the channel
electrons significantly, as shown in Fig. 10. So the obvious
choice was metal, which contains 100 times more electrons
than silicon. Thus metal gates higher electron density screens
out electron scattering phonons and allow smooth flow of cur-
rent flow through the channel [41]. Also, the bond between
high-k dielectric and the metal gate was so well, it solved the
problem of fermi level pinning [19]. The work function of the
metal should be chosen wisely as it is very critical in view of
MOSFET operation [42].
Around Jan 2007, the first working 45 nm HKMG MOS-
FET made by Intel [43]. The transistors, with a high-k material
as the gate dielectric (hafnium-based oxide) along with metal
as gate electrode, exhibited the right threshold voltage with a
very low leakage current and a large on current thus forms the
basis for low power application [44].
6 Double Gate (DG) MOSFET on SOI‑Device
Engineering
The use of high-k dielectrics with metal gates, although
extended the lifetime of planar MOSFET to another dec-
ade but beyond 50 nm introduction of new devices, was
required to meet the challenges faced by conventional
MOSFET [12]. Researchers found out multi-gate struc-
tures such as DGMOSFET can be of use when planar
MOSFETs finally runs out of steam [45]. In planar dou-
ble-gate devices, the gate is on both sides of the chan-
nel [22] i.e. in DG-MOSFET an active biased gate is

13
Transactions on Electrical and Electronic Materials
Metal
High-k
Thicker Dielectric
Gate Oxide
Source Channel Drain
Buried Oxide ( SiO2)
Silicon Substrate
(a)
Fig. 10  a Layout of high-k metal gate transistors, b bumpy ride of electrons in polysilicon gate, c smooth ride of an electron in the metal gate
replaced with the passive substrate so that there can be
control over the channel from both top and bottom simul-
taneously [46]. Figure 11 shows the schematic structure
for DGMOSFET. There are two configurations possible
for DGMOSFET: Asymmetric DG MOSFET (ADG) and
Symmetric DGMOSFET (SDG) as shown in Fig. 11a, b
respectively. In ADG, separate biasing is given to the front
and back gate. The thickness of the two oxides is also dif-
ferent, whereas in SDG, both oxides have same thickness,
and both the gates are tied together with common bias.
DGMOSFET can be scaled to 25–30 nm of channel length,
this was demonstrated by the Monte Carlo and drift–diffu-
sion modeling work by Fiegna et al. and Frank et al. [12].
In a DGMOSFET device, geometry and thin silicon
channel are the features which help in reducing SCEs. It
is electrostatically more robust, and suppression of SCE is
due to the reason that the encroachment of the drain elec-
tric field over the channel is lesser as the channel is sand-
wiched between two gates. The DG feature helps in achiev-
ing sharper subthreshold slope better carrier transport due
to a reduction in channel doping, higher current and also
improves scalability over bulk FET. In bulk MOSFET the
front gate capacitance has to be substantially larger than
VGS
Metal
Gate Oxide (tox)
Source Drain
Channel
Gate Oxide (tox)
Metal
(a)
Fig. 11  The layout of DGMOSFET a SDG, b ADG
Polysilicon Gate Metal
High-k dielectric High-k dielectric
Channel Channel
(b) (c)
substrate depletion layer capacitance, but no such restric-
tions present in DG structure [46]. The added advantage is
that in a DGFET for controlling the device, both the gates
can be used independently.
The key challenges for the fabrication of DGFET are set-
ting the threshold voltage, adjusting the threshold voltage for
multiple threshold voltages on the same chip. Beyond 10 nm
the significant challenge in fabrication are maintaining a
thin, uniform silicon channel. Optimization of the series
resistance and parasitic capacitance of the “overlap” region
also proved to be difficult beyond 10 nm [12]. The most dif-
ficult part in realizing a planar self-aligned DG-MOSFET is
the alignment of back gate to the front gate and still allowing
access to the source and drain [46].
The first double-gate MOSFET was fabricated by
researchers Sekigawa and Hayashi in 1984 in which they
demonstrated that an additional gate could reduce short
channel effect significantly [47]. More robust modeling,
which includes Monte-Carle simulations that explores the
ultimate scaling of the silicon DG-MOSFET [48]. Fully
depleted lean channel transistor (DELTA 1989) was the
first double-gate SOI MOSFET [49]. The structure of the
FinFET is quite similar to DELTA, but in FinFET, there
VGS1
Metal
Gate Oxide (tox1)
Source Channel Drain
Gate Oxide (tox2)
Metal
VGS2
(b)
13

is the presence of an extra dielectric layer called the “hard
mask” on top of the silicon fin, which differentiates it from
the DELTA structure [50]. Thus when the planar structures
become impractical at lower technology nodes, to increase
scalability and the performance of the device, other means
have to be explored [15, 51–53]. Due to the challenges faced
by planar technologies in lower technology nodes, FinFETs
are considered to be suitable for the replacement for planar
MOSFETs due to its various advantages [54].
The multi-gate structures plays various roles in digital,
memory, analog and biomedical applications. SOI FinFET
based instrumentation amplifier are used for biomedical
applications with very low power usage [55]. FinFET are
widely used in-memory applications such as fabrication of
SRAM and DRAM [56–63] Multi-gate structures such as
FinFET have also very strong potential for analog applica-
tions [64, 65].
7 FinFET/Trigate MOSFET
Fin Field Effect Transistor (FinFET) is a tri-gate non-
planar 3D structure commercially adopted around 22 nm
technology in which the gate is on three sides of the chan-
nel [66]. This name FinFET is because the source and
drain formed on the silicon substrate resemble fin like
structure in Fig. 12. The wrapping of the gate around the
channel improves the gate control hence suppresses SCEs
and reduces leakage as observed in sub 50 nm FinFET
[67], and the simulation ensures the feasibility of Fin-
FET to 10 nm length. A self-aligned gate, source-drain
first, and gate-last process FinFET structure is adopted at
17 nm [68], which reduced parasitic resistance and also
suppressed SCEs. A 10 nm FinFET fabricated [69] which
demonstrated superior results such as higher current den-
sity and faster switching ratio as compared to the classical
CMOS, while some challenges were also faced. FinFET is
one important invention in the area of nano-electronics and
7 nm technology is in place [70] by using extreme ultravio-
let lithography (EUV) process and researchers believe that
it is the most promising technology to extend the Moore’s
law all the way to 5 nm technology as demonstrated in
some of the works [71] however beyond that scaling of
FinFET seems unfeasible.
8 Gate All Around FET
The post FinFET era, i.e. beyond 7/5 nm of FinFET, the
next alternative for further scaling are gate all around
(GAA) FET given in Fig.  13. GAAFET is a structure
similar to FinFET except that gate surrounds the channel
13
Transactions on Electrical and Electronic Materials
in four sides of its channel [72], thus, and it ensures bet-
ter control over the channel, which is the fundamental
requirement while going down in technology nodes. There
are two main types of GAA device one is nanowire FET,
and the other is nanosheet FET, which is the elongated
nanowire. GAA structure reported for technology below
5 nm [73] and demonstrated excellent electrostatics, bet-
ter immunity to SCEs, reduced power leakage, immunity
to substrate bias effect; however, there were challenges
in fabrication [74]. GAA structure could take the scaling
beyond 7/5 nm as demonstrated in some of the works [75,
76] and as it utilizes a maximum of channel width hence
results in increased I­ on [77] as compared to same gen-
eration FinFET. Based on the roadmap, GAA structures
may also open the pathways for 3 nm [78], but there is an
increase in parasitic capacitance and also added process
complexity. Beyond 3 nm stacked GAAFET are one of the
most potential candidates [79].
9 CFET
Beyond 3 nm the researchers are trying to use a further
evolution of GAA device i.e. CFET, for further scaling
in Fig. 14. In a traditional GAA device, it either stacks
PFET or NFET; however, a CFET stack both NFET and
PFET on each other hence results in area gain. However,
the electrostatics remain the same as the GAA device,
such as a simple nanowire. CFET meets the requirement
of power and performance and results in 50% reduction in
standard cells as well as SRAM area at 3 nm range [80–82]
as demonstrated by a design technology co-optimization
framework thus extending the perspective of Moore’s law.
CFET seems to be relevant below 3 nm range [83–85],
Fig. 12  Cross-sectional layout of FinFET
Transactions on Electrical and Electronic Materials
Fig. 13  Cross-sectional layout of GAAFET
which yields lesser area and lesser routing congestion, as
demonstrated. Although CFET is advantageous due to the
complimentary stacked nature of CFET, however, CFET
may require a taller structure and are more complex to
make in the fab, which means it may lead to higher capaci-
tance [86].
10 Vertical FET
Beyond 3 nm the alternative to CFET is vertical FET. Verti-
cal FET is a device contrast to horizontal nanowire wherein
the former the wire is stacked vertically, and in the later, the
Fig. 14  Next-gen transistor architectures. Source Imec/ISS
wires are stacked horizontally. It has some drawbacks, very
difficult to make in the fab, and it cannot scale logic cells
although it is a suitable device to scale SRAM.
11 NCFET
Negative capacitance FET (NCFET) is a low voltage device
targeted for 10 nm and up to 3 nm and beyond that [87].
NCFET is a device shown in Fig. 15, that does modification
to the gate stack by incorporating a ferroelectric layer between
the high-k and metal gate [88]. A 7 nm FinFET is studied
by incorporating ferroelectric layers in gate stack [89] and
observed various advantages such as a boost in processor fre-
quency, reduction in power density as compared to the conven-
tional 7 nm FinFET. NCFET technology on this 7 nm FinFET
made it suitable for ultra-low power applications. NCFETs
show improved subthreshold slope up to 54 mV/decade, and
this improved SS reduced the active power but it faced some
challenges such as reliability parasitic issues.
12 Germanium or III–V or 2D Channel
Materials
Alternative channel materials of higher electron and hole
mobility are widely studied for future device scaling. The
non-silicon channel materials such as III–V compound semi-
conductors shown in Fig. 16 are the new hopes for continued
device scaling in the nanoscale range [90]. These high mobil-
ity compounds show improved transport properties over Si
hence are considered to replace silicon. InGaAs and InGaSb
13
 Transactions on Electrical and Electronic Materials

Fig. 15  Cross-sectional layout of NCFET

Fig. 16  The layout of alternate channel MOSFET

are widely experimented candidates for future III–V based
n-MOSFETs and P-MOSFETs, respectively. A III–V nanow-
ire [91] demonstrates improved electrostatics. Germanium
(Ge) is also one of the most suitable channel materials for
P-MOSFET due to its highest hole mobility [92]. 2D material
like graphene, which has ultra-high carrier mobility, may also
be an expected channel material in future MOSFETs, but it
possesses demerits of proper MOSFET switching due to its
zero gap. Many other 2D materials such as MoS2, WS2, or
WSe2, MoS2, MoSe2, and MoTe2 are also in the research
scope to take the scaling beyond 5 nm and to achieve ultra-
short channel MOSFETs [92]. The research on 2D materials
are at very initial stage but it may be one of the candidate to
extend the Moore’s law further.
13 TFET
based on 2D crystals are also of great interest [98–100] as
they overcome the challenge faced by conventional TFET
i.e. low ­Ion and can be seen as a potential candidate for
scaling beyond the limit of CMOS. Vertical TFET with
some additional features such as SiGe pocket, dual source,
negative capacitance, III–V/Si heterojunction, hetero-gate
JLTFET based even show greater potential for ultra-low
power applications [101–107] These advanced VTFET
structures also reduced the SS even further and increased
the performance. These advanced TFET architectures may
serve as one leading candidate beyond 3 nm range as ultra-
low power is requirement of today’s world.

TFET structure in Fig. 17 is one of the most promising

structure which gained attention in nanoscale range to
overcome the SCEs when CMOS devices faced many chal-
lenges. The mechanism of quantum mechanical tunneling
or BTBT tunneling of carriers from source to channel in
TFET makes them different from the MOSFET. TFET
has subthreshold swing lesser than 60 mV/decade, unlike
the MOSFET, which lower ­I off and operating voltage,
thus making them ideal for low power applications. The
constraint of lesser drive current in conventional TFET is
overcome by reducing the ambipolar effect by adopting
various multigate TFETs such as double-gate tunnel FET
(DG-TFET), triple-gate tunnel FET (TG-TFET), double-
gate pocket intrinsic tunnel FET (DG-PI-TFET), triple-
gate TFET structures with pocket intrinsic layer (TG-
PI-TFET) and Dual Material Double Gate Tunnel Field
Effect Transistor (DM-DGTFET) etc. [93–97]. TFETS Fig. 17  Layout of conventional TFET

13
Transactions on Electrical and Electronic Materials
Fig. 18  Pictorial representation of technology trend
14 Prominent Technology Trends
Out of the study the Fig. 18 is a pictorial representation
of the technology advancemnts. After reading this we can
have a vision and motivation to think further innovation
based the recent requirement and demand.
15 Conclusion
The continuous and aggressive scaling of the MOS transis-
tor has led to the phenomenal growth of IC industry over
the past decades. Around 22 nm when conventional MOS-
FETs became incompetent to deliver desired performance,
new device structures such as TFET, FDSOI devices, and
FinFETs came into picture. Out of all inventions, Fin-
FETs played a major role in scaling beyond 22 nm and
shown a path for miniaturization till 7 nm process. GAA
devices such as nanowire and nanosheet are in research to
realize 3 nm device. Vertical FET, CFET, stacked FET,
NCFET and alternative channel materials are in the road
map for narrowing down the transistor beyond 3 nm when
Moore’s law is under pressure. However, beyond 1.5 nm
the roadmap is not clear. The futuristic devices may be
advanced TFET structures, spin-wave devices, 3D nano
fabrics for ultra-low power applications, and improved
performance. While moving from one device to another
to achieve higher mobility, the industry must take care of
some fundamental challenge of low leakage, subthreshold
voltage, and low power supply voltage.
In this review work, effort has been made to include
related articles starting from scaling issues on the bulk
MOSFETs to 3 nm and beyond transistor technology. We
have tried our best to enlist various advancement in the
semiconductor engineering. Still, a few important contri-
butions may be missed and the authors apologize for unin-
tentionally omission of other researchers’ works.
Compliance with Ethical Standards 
Conflict of interest  The authors declare that they have no conflict of
interest.
References
1. W. Arden, M. Brillouët, P. Cogez, M. Graef, B. Huizing, R.
Mahnkopf, Version 2, 14 (2010)
2. G.E. Moore et al., Electronics (1965). https​://www.cs.csub.
edu/~melis​sa/cs350​-f15/notes​/Doc/gordo​n_moore​_1965_artic​
le.pdf
3. R.R. Schaller, IEEE Spectr. 34, 52 (1997)
4. M. Lundstrom, Science (80–) 299, 210 (2003)
5. P.K. Bondyopadhyay, Proc. IEEE 86, 78 (1998)
6. R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, A.R.
LeBlanc, IEEE J. Solid-State Circuits 9, 256 (1974)
7. C. Hu, ECS Trans. 50, 17 (2013)
8. S. Deb, N.B. Singh, N. Islam, S.K. Sarkar, IEEE Trans. Nano-
technol. 11, 472 (2011)
13

9. J.H. Stathis, IBM J. Res. Dev. 46, 265 (2002)
10. J. Suñé, M. Nafria, E. Miranda, X. Oriols, R. Rodriguez, X.
Aymerich, Semicond. Sci. Technol. 15, 445 (2000)
11. G. Ghibaudo, R. Clerc, E. Vincent, S. Bruyere, J.L. Autran, C.
R. l’Acad. Des Sci. IV-Phys. 1, 911 (2000)
12. H.-S.P. Wong, Solid State Electron. 49, 755 (2005)
13. I.R. Committee et al., Semicond. Ind. Assoc. http://www.itrs.
net/Links​/2011I​TRS/2011C​hapte​rs/2011E​xecSu​m.pdf (2011)
14. M. Wu, Y.I. Alivov, H. Morkoc, J. Mater. Sci. Mater. Electron.
19, 915 (2008)
15. S. Datta, Electrochem. Soc. Interface 22, 41 (2013)
16. P.M. Zeitzoff, H.R. Huff, in AIP Conference Proceedings
(2005), pp. 203–213
17. C.C. Wu, D.W. Lin, A. Keshavarzi, C.H. Huang, C.T. Chan,
C.H. Tseng, C.L. Chen, C.Y. Hsieh, K.Y. Wong, M.L. Cheng,
T.H. Li, in 2010 International Electron Devices Meeting
(2010). https​://doi.org/10.1109/IEDM.2010.57034​30
18. M.J. Sherony, L.T. Su, J.E. Chung, D.A. Antoniadis, IEEE
Electron Device Lett. 16, 100 (1995)
19. M.T. Bohr, R.S. Chau, T. Ghani, K. Mistry, IEEE Spectr. 44,
29 (2007)
20. V. Subramanian, J. Kedzierski, N. Lindert, H. Tam, Y. Su,
J. McHale, K. Cao, T.-J. King, J. Bokor, C. Hu, in 1999
57th Annual Device Research Conference Digest (Cat. No.
99TH8393) (1999), pp. 28–29
21. E. Rauly, O. Potavin, F. Balestra, C. Raynaud, Solid State Elec-
tron. 43, 2033 (1999)
22. L. Geppert, IEEE Spectr. 39, 28 (2002)
23. A. Chaudhry, M.J. Kumar, IEEE Trans. Device Mater. Reliab.
4, 99 (2004)
24. E. Suzuki, K. Ishii, S. Kanemaru, T. Maeda, T. Tsutsumi,
T. Sekigawa, K. Nagai, H. Hiroshima, IEEE Trans. Electron
Devices 47, 354 (2000)
25. T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst,
B. Previtali, S. Deleonibus, Microelectron. Eng. 80, 378 (2005)
26. Q. Liu, M. Vinet, J. Gimbert, N. Loubet, R. Wacquez, L. Gre-
nouillet, Y. Le Tiec, A. Khakifirooz, T. Nagumo, K. Cheng,
et al., in 2013 IEEE International Electron Devices Meeting
(2013), pp. 2–9
27. R.D. Clark, Materials (Basel). 7, 2913 (2014)
28. J. Robertson, Solid State Electron. 49, 283 (2005)
29. J. Robertson, J. Non. Cryst. Solids 303, 94 (2002)
30. J. Robertson, Compr. Semicond. Sci. Technol. Online Version
4, 132 (2011)
31. M. Houssa, L. Pantisano, R. Ragnarsson LÅand Degraeve,
T. Schram, G. Pourtois, S. De Gendt, G. Groeseneken, M.M.
Heyns, Mater. Sci. Eng. R Rep. 51, 37 (2006)
32. S. Mohsenifar, M.H. Shahrokhabadi, Terminology 2, 5 (2015)
33. B. Ryu, K.-J. Chang, Appl. Phys. Lett. 97, 242910 (2010)
34. D.G. Schlom, S. Guha, S. Datta, MRS Bull. 33, 1017 (2008)
35. J.H. Choi, Y. Mao, J.P. Chang, Mater. Sci. Eng. R Rep. 72, 97
(2011)
36. A. Srivastava, O. Mangla, R.K. Nahar, V. Gupta, C.K. Sarkar,
J. Mater. Sci. Mater. Electron. 25, 3257 (2014)
37. H. Wang, Y. Wang, J. Feng, C. Ye, B.Y. Wang, H.B. Wang,
Q. Li, Y. Jiang, A.P. Huang, Z.S. Xiao, Appl. Phys. A 93, 681
(2008)
38. H.-L. Lu, D.W. Zhang, High-k gate. Dielectr. C. Technol. 31
(2012)
39. K.P. Pradhan, S.K. Mohapatra, P.K. Sahu, D.K. Behera, Micro-
electronics J. 45, 144 (2014)
40. C. Zhao, C.Z. Zhao, M. Werner, S. Taylor, P.R. Chalker, ISRN
Nanotechnol. 2012 (2012). https​://doi.org/10.5402/2012/68902​3
41. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, M. Metz,
IEEE Electron Device Lett. 25, 408 (2004)
42. J. Robertson, R.M. Wallace, Mater. Sci. Eng. R Rep. 88, 1 (2015)
13
Transactions on Electrical and Electronic Materials
43. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M.
Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, et al., in
2007 IEEE International Electron Devices Meeting (2007), pp.
247–250
44. K.J. Kuhn, U. Avci, A. Cappellani, M.D. Giles, M. Haverty, S.
Kim, R. Kotlyar, S. Manipatruni, D. Nikonov, C. Pawashe, et al.,
in 2012 IEEE International Electron Devices Meeting (2012), pp.
1–8
45. B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kava-
lieros, T. Linton, A. Murthy, R. Rios, R. Chau, IEEE Electron
Device Lett. 24, 263 (2003)
46. P.M. Solomon, K.W. Guarini, Y. Zhang, K. Chan, E.C. Jones,
G.M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, H.J.
Hovel et al., IEEE Circuits Devices Mag. 19, 48 (2003)
47. T. Sekigawa, Solid State Electron. 27, 827 (1984)
48. D.J. Frank, S.E. Laux, M.V. Fischetti, IEDM Tech. Dig. 553
(1992). https​://doi.org/10.1109/IEDM.1992.30742​2
49. D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda, in International
Technical Digest Electron Devices Meeting (1989), pp. 833–836
50. V. Narendar, Silicon 10, 2419 (2018)
51. S. Dey, S.K. Banerjee (2011)
52. J.L. Huguenin, G. Bidal, S. Denorme, D. Fleury, N. Loubet, A.
Pouydebasque, P. Perreau, F. Leverd, S. Barnola, R. Beneyton
et al., Solid State Electron. 54, 883 (2010)
53. A. Fasoli, W.I. Milne, Mater. Sci. Semicond. Process. 15, 601
(2012)
54. D. Bhattacharya, N.K. Jha, Adv. Electron. 2014 (2014). https​://
doi.org/10.1155/2014/36568​9
55. R. Sonkusare, O. Joshi, S.S. Rathod, Microelectronics J. 91, 1
(2019)
56. C.H. Lee, J.M. Yoon, C. Lee, H.M. Yang, K.N. Kim, T.Y. Kim,
H.S. Kang, Y.J. Ahn, D. Park, K. Kim, in Digest of Technical
Paper 2004 Symposium VLSI Technology 2004 (2004), pp.
130–131
57. K. Kim, in IEEE International Devices Meeting 2005. IEDM
Technical Digest (2005), pp. 323–326
58. C.H. Lin, B. Greene, S. Narasimha, J. Cai, A. Bryant, C. Radens,
V. Narayanan, B. Linder, H. Ho, A. Aiyar, et al., in 2014 IEEE
International Electron Devices Meeting (2014), pp. 3–8
59. S.-J. Choi, J.-W. Han, S. Kim, D.-H. Kim, M.-G. Jang, J.-H.
Yang, J.S. Kim, K.H. Kim, G.S. Lee, J.S. Oh, et al., in 2008 IEEE
International Electron Devices Meeting (2008), pp. 1–4
60. T. Tanaka, E. Yoshida, T. Miyashita, in IEDM Technical Digest
IEEE International Electron Devices Meeting 2004 (2004), pp.
919–922
61. T. Dutta, G. Pahwa, A.R. Trivedi, S. Sinha, A. Agarwal, Y.S.
Chauhan, IEEE Electron Device Lett. 38, 1161 (2017)
62. H. Ananthan, A. Bansal, K. Roy, in International Symposium on
Signals, Circuits and Systems Proceedings, SCS 2003.(Cat. No.
03EX720) (2004), pp. 511–516
63. Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, B.
Nikolić, in Proceedings of the 2005 International Symposium
Low Power Electronics and Design (2005), pp. 2–7
64. A. Kranti, G.A. Armstrong, IEEE Trans. Electron. Devices 54,
3308 (2007)
65. V. Kilchytska, N. Collaert, R. Rooyackers, D. Lederer, J.-P.
Raskin, D. Flandre, in Proceedings of the 30th European Solid-
State Circuits Conference (IEEE Cat. No. 04EX850) (2004), pp.
65–68
66. C.C. Wu, D.W. Lin, A. Keshavarzi, C.H. Huang, C.T. Chan, C.H.
Tseng, C.L. Chen, C.Y. Hsieh, K.Y. Wong, M.L. Cheng, et al., in
2010 International Electron Devices Meeting (2010), pp. 21–27
67. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J.
Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano,
et al., in International Electron Devices Meeting 1999. Technical
Digest (Cat. No. 99CH36318) (1999), pp. 67–70
Transactions on Electrical and Electronic Materials
68. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano,
C. Kuo, E. Anderson, T.-J. King, J. Bokor, C. Hu, IEEE Trans.
Electron Devices 47, 2320 (2000)
69. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C.
Tabery, C. Ho, Q. Xiang, T.-J. King, et al., in Digest Interna-
tional Electron Devices Meeting (2002), pp. 251–254
70. R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S.
Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, et al., in 2016
IEEE International Electron Devices Meeting (2016), pp. 2–7
71. F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C.
Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, et al.,
in Digest Technical Paper 2004 Symposium VLSI Technology
2004. (2004), pp. 196–197
72. F. Ishikawa, I. Buyanova, Novel Compound Semiconductor
Nanowires: Materials, Devices, and Applications (CRC Press,
Boca Raton, 2017)
73. N. Singh, A. Agarwal, L.K. Bera, T.Y. Liow, R. Yang, S.C. Rust-
agi, C.H. Tung, R. Kumar, G.Q. Lo, N. Balasubramanian et al.,
IEEE Electron Device Lett. 27, 383 (2006)
74. M. Li, K.H. Yeo, S.D. Suk, Y.Y. Yeoh, D.-W. Kim, T.Y. Chung,
K.S. Oh, W.-S. Lee, in 2009 Symposium VLSI Technology
(2009), pp. 94–95
75. S.-D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, M.-H. Na,
in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technol-
ogy Unified Conference (2015), pp. 1–3
76. H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang,
K.-H. Kim, J. Lee, J.-H. Kim, S. Jeon, et al., in 2006 Sympo-
sium VLSI Technology 2006. Digest Technical Paper (2006), pp.
58–59
77. N. Mendiratta, S.L. Tripathi, J. Semicond. 41, 061401 (2020).
https​://doi.org/10.1088/1674-4926/41/6/06140​1
78. U.K. Das, T.K. Bhattacharyya, IEEE Trans. Electron Devices 67,
2633 (2020). https​://doi.org/10.1109/TED.2020.29871​39
79. H. Mertens, R. Ritzenthaler, A. Hikavyy, M.-S. Kim, Z. Tao, K.
Wostyn, S.A. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel,
et al., in 2016 IEEE Symposium VLSI Technology (2016), pp. 1–2
80. J. Ryckaert, P. Schuddinck, P. Weckx, G. Bouche, B. Vincent, J.
Smith, Y. Sherazi, A. Mallik, H. Mertens, S. Demuynck, et al.,
in 2018 IEEE Symposium VLSI Technology (2018), pp. 141–142
81. S. Kal, Y. Oniki, M. Falugh, C. Pereira, Q. Wang, F. Holsteyns, J.
Smith, A. Mosden, K. Kumar, J. Boemmels, et al., in Advanced
Etch Technology Nanopatterning VIII (2019), p. 109630L
82. N. Collaert, in 2020 IEEE International Solid-State Circuits Con-
ference (2020), pp. 25–29
83. A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J.
Ryckaert, in 2018 IEEE Symposium VLSI Technology (2018),
pp. 147–148
84. P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y.
Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, et al., in 2019
Symposium VLSI Technology (2019), pp. T204–T205
85. S.M.Y. Sherazi, J.K. Chae, P. Debacker, L. Matti, D. Verkest,
A. Mocuta, R.H. Kim, A. Spessot, A. Dounde, J. Ryckaert, in
Design Co-Optimization Manufacturing XIII (2019), p. 1096206
86. J. Ryckaert, M.H. Na, P. Weckx, D. Jang, P. Schuddinck, B. Che-
hab, S. Patli, S. Sarkar, O. Zografos, R. Baert, et al., in 2019
IEEE International Electron Devices Meeting (2019), pp. 24–29
87. E. Ko, J. Shin, C. Shin, Nano Converg. 5, 1 (2018)
88. A. Seabaugh, C. Alessandri, M.A. Heidarlou, H.-M. Li, L. Liu,
H. Lu, S. Fathipour, P. Paletti, P. Pandey, T. Ytterdal, in 2016
46th European Solid State Device Research Conference (2016),
pp. 349–351
89. H. Amrouch, G. Pahwa, A.D. Gaidhane, J. Henkel, Y.S. Chauhan,
IEEE Access 6, 52754 (2018)
90. J.A. Del Alamo, D.A. Antoniadis, J. Lin, W. Lu, A. Vardi, X.
Zhao, IEEE J. Electron Devices Soc. 4, 205 (2016)
91. L.-E. Wernersson, Microelectron. Eng. 147, 344 (2015)
92. F. Schwierz, J.J. Liou, in 2020 IEEE Latin-American Electron
Devices Conference (2020), pp. 1–4
93. A.S. Geege, N. Armugam, P. Vimala, T.S.A. Samuel, in 2020
5th International Conference on Circuits Devices and Systems
(2020), pp. 311–315
94. R. Dutta, S.C. Konar, N. Paitya, in Computational Advancement
in Communication Circuits and Systems (Springer, Berlin, 2020),
pp. 345–355
95. S.A. Sahu, R. Goswami, S.K. Mohapatra, Silicon 12, 513 (2020)
96. S. Dash, G.P. Mishra, Adv. Nat. Sci. Nanosci. Nanotechnol. 7,
25012 (2016)
97. N. Guenifi, S.B. Rahi, T. Ghodbane, Mater. Focus 7, 866 (2018)
98. D. Jena, Proc. IEEE 101, 1585 (2013)
99. H. Ilatikhameneh, Y. Tan, B. Novakovic, G. Klimeck, R. Rah-
man, J. Appenzeller, IEEE J. Explor. Solid-State Comput.
Devices Circuits 1, 12 (2015)
100. G. Fiori, F. Bonaccorso, G. Iannaccone, T. Palacios, D. Neu-
maier, A. Seabaugh, S.K. Banerjee, L. Colombo, Nat. Nanotech-
nol. 9, 768 (2014)
101. W. Li, J.C.S. Woo, IEEE Trans. Electron. Devices 67, 1480
(2020)
102. S. Badgujjar, G. Wadhwa, S. Singh, B. Raj, Trans. Electr. Elec-
tron. Mater. 21, 74 (2020)
103. V. P.-H. Hu, H.-H. Lin, Y.-K. Lin, C. Hu, IEEE Trans. Elec-
tron Devices 67, 2593 (2020). https ​ : //doi.org/10.1109/
TED.2020.29867​93
104. M.R. Tripathy, A.K. Singh, S. Chander, P.K. Singh, K. Baral, S.
Jit, in 2020 5th International Conference on Circuits Devices and
Systems (2020), pp. 180–183
105. S.B. Rahi, P. Asthana, S. Gupta, J. Comput. Electron. 16, 30
(2017)
106. P.K. Asthana, Y. Goswami, S. Basak, S.B. Rahi, B. Ghosh, RSC
Adv. 5, 48779 (2015)
107. S.M. Biswal, B. Baral, D. De, A. Sarkar, Superlattices Micro-
struct. 91, 319 (2016)
Publisher’s Note Springer Nature remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.
13