GENERAL RELIABILITY ISSUES

BASIC DEFINITIONS

 Memory Yield:
• Memory yield commonly expressed as the ratio of the passing devices during an initial test
such as wafer sort or wafer level acceptance testing versus the total number manufactured.

 Quality:
• Quality is measured by the proportion of chips (or packaged parts) that fall out during a
screening test flow.

 Reliability:
• Reliability is measured by the device failures that occur during the qualification and quality
conformance inspection (QCI).
• Field failures are devices which fail in the actual operating environment (subsequent to all
processing steps)
• A memory failure is defined as the loss of the ability to perform functionally or parametrically
as per the device specification.
• The failures are typically grouped into one of three categories , depending upon the product's
operating life cycle stage where the failures occur.

• These categories areas follows:

 Infant mortality,
 useful life and
 Wear out failures

 Infant mortality:
• The infant mortality failures for a device type occur during the early product life cycle, and by
definition, the rate of failure decreases with age.
• Causes: design-related defects, flawed materials and contamination, poor manufacturing
assembly and workmanship, improper process monitoring and lack of quality controls, and
inadequate screening (or burn-in).
 Useful life:
• The second type of failures occur during the useful life of the device for which the rate of
failure is assumed to be constant by a widely used model.
• Causes: inadequate derating, improper startups and voltage transients, and higher than
expected thermal and electrical stresses.

 Wearout failures:
• The third type are the wearout failures which occur late in the device operating life cycle.
• Causes: The cause of the wearout failures include aging phenomenon, degradation, and
material fatigue, and by definition, the rate of failure during this cycle increases with age.
Bathtub curve
 Bathtub curve

• If the failure rate is plotted against the operating life test data taken from a statistically large
sample size placed in operation at t == 0, then the resulting curve for medium- to low-level
stress takes the shape of a "bathtub curve.”

• For this bathtub curve,

 The high initial rate of failure represents infant mortality failures,

 The flat central portion of the curve indicating constant failure rate corresponds to the useful
life of the product,
 And the increasing rate of failure with advanced age is due to the wearout failures as
represented in fig.6.1.
 TYPES OF FAILURES

• In general, for micro electronic devices such as memories, the failure mechanisms can be
broadly categorized as:

(1)semiconductor bulk failures,

(2)dielectric failures,
(3) semiconductor dielectric interface failures,
(4) conductor and metallization failures, and
(5) assembly- and packaging-related failures.

• These failure mechanisms are applicable to random access memories and non-volatile
memories.
 (1)Semiconductor Bulk Failure

• The bulk failure mechanisms are those occurring within the memory semiconductor material
itself, and include the chip fracture, cracks or pits in the chip or passivation layers, secondary
breakdown, latch up, displacement damage due to the ionizing radiation, and single-event
upset (SEU).

 Secondary breakdown:
• The secondary breakdown which was first observed in early bipolar transistors results in
reduced voltage, and an increase in localized current density that may lead to permanent
device degradation or failure.

 Latchup:
• Latch up in the bipolar or CMOS circuits occurs when a parasitic p-n-p-n structure is turned on
due to a silicon-controlled rectifier (SCR) action.
• In the latch up condition, the gain of interconnected bipolar n-p-n and p-n-p transistors
exceeds unity, which provides a low-impedance current path from the power supply to
ground.
• It can also be caused by transient ionizing radiation and heavy particle space environment
 Ionizing radiation:
• In bipolar transistors, ionizing radiation can produce semiconductor bulk displacement
damage which reduces the lifetime of minority carriers, thereby reducing the current gain.
• Total dose and transient radiation effects for both the bipolar and MOS memories.
 (2)Dielectric-Related Failures

 Definition of Dielectric:
• Dielectrics are basically insulating and non-conducting substances. They are bad conductors of
electric current .
• Dielectrics are capable of holding electrostatic charges while emitting minimal energy.
• Examples of dielectrics include mica, plastics, porcelain, metal oxides and glass etc.

• Memory dielectric defects in the deposited dielectric (e.g., pinhole)-related failure mechanisms
can be attributed to causes such as:

 time-dependent dielectric breakdown (TDDB) at the defect sites in thermally grown oxides,
 dielectric wearout mechanisms due to the high field stresses,
 dielectric rupture due to ESD or electrical overstress (EOS).

• The dielectrics used in memories include the oxides over the base and collector regions of the
bipolar devices, thermally grown gate oxides and field oxides for the CMOS devices, tunneling
oxides, and inter-metal dielectrics in dual (or triple) levels of metallic conductors.
 About Thermally grown silicon dioxide:
• Thermally grown silicon dioxide has a low thermal activation energy of typically 0.3eV,but a
high-voltage acceleration factor(Y) of 107/MV/cm.
• As the MOS memories are scaled for higher densities, the margin between the intrinsic oxide
breakdown voltage and the device operating voltage is considerably reduced.

 Causes of Dielectric fractures:

• The dielectric fractures can be caused by the thermal coefficient of expansion mismatch
between the dielectric film and the underlying materials such as bulk semiconductor,
polysilicon , or conductor metal.
• Dielectric film rupture over an aluminum metal line may be caused by the encapsulant
plastic material , or the growth of hillocks from electro-migration in the metal lines.
 (3)Semiconductor-Dielectric
Interface Failures

• Memory semiconductor-dielectric interface faiIures are caused by the motion of charges in a

dielectric or across the interface between the dielectric and underlying semiconductor
material.

• The most significant failure mechanisms across theSi-Si02 interface are caused by alkali ion
migration from contamination, hot carrier effects, slow trapping instabilities, and surface
charge spreading.

• Ionic contamination results from the sodium (and to lesser extent potassium) ions which are
present in various materials and packaging processes in a typical memory IC manufacturing
cycle.
• The mobility of sodium ions in silicon dioxide is quite high, and the presence of a high electric
field at temperatures typically above 100°C causes these ions to drift toward the Si-Si02
interface.

• It is the surface potential which determines whether or not a conducting channel exists.

• Therefore , any drift or variation in the potential influences the gate threshold voltage , the
carrier regeneration-recombination rate, and the depletion width of p-n structures.

• The net effect of this ionic drift is to reduce the threshold of n-channel transistors and
increase the threshold voltage of p-channel transistors.

• The positive ionic contamination can degrade information which is stored in the EPROMs as
negative charge trapped within the floating gate.
• Because of imperfections in passivation layers, the contaminants can migrate to the defect
sites and cause device degradation.
• The wafer level mobile charge contamination is given by the equation
Qm=Cox.∆V fb

where Cox= oxide capacitance

Qm= mobile charge per unit area.

 Hot carrier effects:

• Hot carrier effects are also responsible for the Semiconductor-Dielectric Interface Failures.
• Hot-carrier effects are generated in short-channel (<2 μm) devices such as DRAMs when
operate data voltage near the break-down voltage(BVDS)by the presence of a high drain-
source electric field which may cause injection of some carriers across the Si-Si02 interface in
the region of channel in the drain .
• There are three types of hot carriers depending upon the source origin:

(1)channel hot carriers which, in crossing the channel , experience very few lattice collisions
and can thereby accelerate to high energies,
(2) substrate hot carriers which are thermally generated below the inversion layer in the
substrate and drift toward the interface, and
(3) avalanche hot carriers which are created in the avalanche plasma and result from
multiple-impact ionizations in the presence of strong lateral electric fields.

• The hot-electron injection can increase both the oxide-trapped charge (No,) and the interface
trapped charge(Nit) in the channel, which can affect both the threshold voltage (VTH) and
transconductance (gm) of the MOS transistors.
 (4)Conductor and Metallization
Failures
• Conductor and metallization major failure mechanisms in micro-electronic devices such as
memories include electro-migration, metallization cracks and voids, corrosion faults and effects,
and contact spiking.

 Electro-migration:
• Electro-migration is the transport of material caused by the gradual movement of the ions in a
metallic conductors so-called "electron wind" or "ion wind“.
• Electro-migration is a phenomenon which involves the transport of atoms of a metallic
conductor such as aluminum because of high current density.
• It occurs at elevated temperatures under the influence of a temperature gradient or current
density in excess of 10^6 A/cm2 .
• When the ionized atoms collide with the current flow of scattering electrons, an "electron wind“
is produced .
• This wind moves the metal atoms in the opposite direction from the current flow, which
generates voids at a negative electrode, modules or hillocks, and whiskers at the opposite end
electrode.
• The generated voids increase wiring resistance and cause excessive current flow in some areas,
which may lead to open metallization.
• The electro-migration-related failure modes can be summarized as follows:
 Catastrophic open failures due to voiding for single-layered AI-alloy metallization.
 Resistance increases due to the multilayered AI-alloy metallization systems.
 Inter-level and intra level shorting due to the electro-migration-induced extrusions
 Resistive contact formation and junction spiking(leakage).

• The micro cracks usually occur at oxide steps and at the contact windows . Advances in
memory processing techniques can minimize these effects.
• The electro-migration failures have log normal distribution , the median-time-to-failure(t50)
is given by
t50= AJ^(-N)exp[QA/KT]

where J=continuous dc current density in A/cm2

QA= activation energy
A= process-related parameter
N= constant(reported values from 1 to 7, with 2 being typical)
k=Boltzmann's constant
T= absolute temperature
 (5)Metallization Corrosion-Related
Failures

• The corrosion of aluminum metallization systems in semiconductor devices such as

memories in plastic-encapsulated packages is a major failure mechanism.

• This corrosion can be caused by the presence of halide ion contaminants which may originate
from following sources:
(1) plastic encapsulation-related in complete curing process, resulting in the ionic impurities,
presence of halogens, and other corrosive elements;
(2)atmospheric pollutants and moisture;
(3) fluxes used for lead finishing;
(4) impurities in die attach epoxies and molding compounds;
(5) byproducts from reactive ion etching of metallization; and
(6) human operators' fingerprints, spittle, etc.
• In plastic packages, a mismatch of thermal coefficients of expansion between the silicon die
and encapsulant materials, as well as chemical shrinkage, can cause mechanical stresses.

• These stresses can lead to cracks in the plastic package and/or die, including the passivation
layers and metallization.

• Advances in memory plastic packaging technologies have been made to reduce the corrosion
susceptibility by monitoring and controlling contamination levels, improvement of chip
passivation layers, and reduced thermal coefficient of expansion mismatch.

• C-mode scanning acoustic microscopy (C-SAM), in conjunction with the accelerated aging
conditions , can be used to characterize the moisture sensitivity of the plastic-packaged
memory surface mount devices
 (6)Assembly-and Packaging Related Failures

• The major reliability issues for memory chip assembly processes and packaging operations
are related to failure mechanisms pertaining to:

(1) die bonding,

(2) wire bonds,
(3) contaminant effects, and
(4) corrosion of aluminum metallization systems.

• The die bonding to a metallic (header/lead frame) or a ceramic substrate provides a

mechanical support for the chip and a low-resistance path for heat conduction from the chip.
• There are several die bonding materials used, such as gold-silicon (Au-Si) or Au-germanium
eutectic alloy , silver filled epoxy, and polyimide adhesives.
• Some of the major causes for die bonding failures include: voids in the die bonding materials,
contamination, formation of brittle inter metallics at the bonding surface, higher than normal
thermal resistance, and die cracking from the die bond-induced stresses
• To avoid die-bond-induced chip cracking, advanced assembly techniques include making
distortion measurements using sensitive gauges, the use of finite element analysis, and
thermal cycling test results.
• Wire bonding is a critical assembly process, and is automated to avoid manual assembly-
induced defects.
• Aluminum and gold are the two materials used for wire bonds, and the most common
methods of wire bonding are the thermo compression and ultrasonic techniques.
• Al wire bonding uses an ultrasonic technique in which the wire is placed in direct contact
with the metallization, and then the bonding pad and wire are vibrated to scrub off the oxide
and create sufficient heat to form a bond.
• In addition, high chip integration densities have been accompanied at the cost of the
following:
(1) reduced feature size,
(2) the use of new materials, e.g., complex silicides and oxides,
(3)multi level layers of metallization and polysilicon, and
(4) increased 3-D processing such as trenches and pillars
THANKYOU