Professional Documents
Culture Documents
in
Deep Submicron Devices
Mitigation Techniques
Conclusion
Introduction
Successful design of IC requires complicate optimization between several
parameter e.g. area, speed, power dissipation, testability etc.
Figure: Scaling trend of device feature size and optical wavelength of lithography process.
Sources of Process Variations
Optical lithography has been used from last three decades to fabricate IC.
Below 65nm technology, feature size becomes less than wavelength of light
that result in difficult to print accurate design.
These variations are systematic in nature and shift the device characteristic.
The process variations change the nature of delay and leakage from
deterministic to stochastic.
Intra-die Process Variation
Variations in devices characteristics within the same die are Intra-die
process variations.
Random dopant fluctuation (RDF) and Line edge roughness (LER) are two
main source of intra-die process variation.
These variation are random in nature i.e. circuit with intra-die process
variation behave randomly.
Intra-die Process Variation (cont)
Figure: Spatial variation (a) channel length variations, (b) RDF, (c)
Scaling trends of number of doping atoms in the channel and (d) LER
Intra-die Process Variation (cont)
RDF is caused by random placement of dopant atom in the channel region
Since the number of dopant atoms are very small (in scaled device) their
placement severely affect the device characteristics
LER is the distortion in gate shape along the channel width direction. This
is distortion occurred during process of gate etching and gate material
dependent
Since the channel width is very small, small fluctuation change the device
characteristics
The age related variation degrade the device strength when device is used
for long period of time.
Figure: NBTI degradation process in PMOS. Breaking of hydrogen bonds creates dangling Si that acts
as a defect trap near SiSiO2 interface, increases VTH of the transistor. VTH degradation and recovery
mechanism under NBTI stress is also shown.
NBTI (Cont)
NBTI increases threshold voltage, reduce channel mobility and introduces
parasitic capacitances.
Analysis show that NBTI degradation rate increases with scaling for
planner, triple-gate and surround-gate MOSFETs.
Positive Bias Temperature Instability (PBTI)
PBTI is experienced by NMOS transistor similar to NBTI experience by
PMOS.
The effect of NBTI in PMOS was considered more severe than PBTI in
nMOS.
HCI is more significant in nMOS as electrons have higher mobility and can
gain higher energy than holes.
Short circuit between substrate and gate electrode result in oxide failure
and once occurred, it causes a sudden energy burst may result in thermal
runaway
Figure: Growing proportion of within die process variation with technology scaling.
Effect of PV on Logic (cont)
Increased delay and spread of delay distribution: The inter-die and intra-
die variation modify the Vth which result in variation in speed/delay.
Chips slower than the target delay are discarded (or sold at a lower price).
Figure: Impact of within-die process variation becomes prominent with increasing pipeline depth.
Effect of PV on Dynamic Logic
The variations have different impact on the dynamic logic. As these logic
works on the principle of precharge and evaluate.
Figure: Example of a dynamic logic circuit. The VTH of NMOS transistor determines the noise margin
Effect of PV on Dynamic Logic (cont)
Large transistor sizing is required in the keeper to increase robustness if
devices shows large leakage due to process variation.
The variation in the stage delays thus results in variation in the overall
pipeline delay.
Effect of PV on Pipelined Logic (Cont)
Traditionally, the pipeline clock frequency has been enhanced by
Increasing the number of pipeline stages, which, in essence, reduces the logic
depth and hence, the delay of each stage; and
Balancing the delay of the pipe stages, so that the maximum of stage delays is
optimized.
The hot spots are one of the primary factors behind reliability degradation
and thermal runaways.
Designing for the worst case leakage causes excessive guard banding,
resulting in lower performance.
The higher temperature decreases the VTH (good for speed) but reduces the
on current reducing the overall speed of the design.
A higher voltage speeds up the circuit while a lower voltage slows down
the system.
Since the voltage and the temperature depend on the operating conditions,
the circuit speed becomes unpredictable.
The aging-related temporal variations, on the other hand, affect the circuit
speed systematically over a period of time.
Effect of Temporal PV on Logic (Cont)
The impact of NBTI degradation is manifested as the increase of delays of
critical timing paths and reduction of sub-threshold leakage current.
A compact statistical NBTI model considering the random nature of the Si
H bond breaking in scaled transistors has been developed.
It is observed that from the circuit level perspective, NBTI variation closely
resembles the nature of RDF-induced VTH variation.
Figure: Variation under NBTI degradation and RDF (a) both the mean and spread of inverter gate delay distribution increase due to combined
effect of RDF and NBTI. (b) inverter leakage is reduced with NBTI, however, the spread of leakage can increase due to statistical NBTI effect.
Effect of PV on SRAM
PV effect is more severe in SRAM than logic since transistors are of
minimum size for high density requirement.
Figure: (a) Overall cell failure probability due to combined effect of read, write, access, and hold failures. (b) Memory array equipped with
redundant columns for repair
Effect of PV on SRAM (cont)
Inter-die variation causes shift in Vth, this results in increase in effect of
random intra-die variation effect.
Low Vth shift increase read and hold failure probability while high Vth shift
increase write and access failure probability
Failure in any cell of a column make column faulty and if number of faulty
column are more than redundant column then chip is considered to be
faulty
Impact of temporal variation on SRAM
The process variation result in degradation in all transistor of SRAM cell
while NBTI affect only pMOS, result in increased failure
A SRAM with perfect SNM may experience failure after few years due to
NBTI. Results shows that SNM degrades more than 9% in three years
The cell storing constant data for long time results in more degradation
The technique are mainly two types design-time and run-time given in table
Circuit Level Technique for SRAM
Sizing: Length and width of different transistor of SRAM cell affect cell
failure probabilities by modifying access time, read voltage, trip point of
the inverter, write time, and minimum retention voltage
Weak access transistor reduces PRF but increases PAF, PWF i.e. it is good for
read but bad for write
Reducing strength of pull up transistor reduces PWF but increases PRF and
PHF also degrade i.e. weak pull up good for write but read
Increasing the strength of pull down nMOS transistor reduces PRF and PAF
Circuit Level Technique for SRAM (cont)
Body Bias Technique: Transistor threshold which varied due to PV, is
critical parameter can be controlled by applying body bias as shown below
Leakage monitor detect the threshold voltage of SRAM array if high
indicates low Vth may result in read and hold failure which is improved by
generating RBB to increase Vth with the help of body-bias generator
Similarly, high Vth due to PV effects Access and write failure can be
reduced by increasing Vth with the help of applied FBB by body-bias
generator
Circuit Level Technique for SRAM (cont)
Source Biasing: Source potential control the leakage in the memory
When a particular row is accessed, the source line is biased to zero results
in increase in drive current and achieve fast read/write operation.
When row is not accessed, source line is raise to VSB potential which
reduce subthreshold and leakage current in turn reduces hold failure
Adaptive source biasing is also used to minimize leakage while controlling
the hold failure
8T and 10T SRAM cell
The major problem with 6T is read and write margins have tradeoffs each
other, increasing one decrease other
If read and write operation are decoupled, designer will get better flexibility
to optimize read and write margins, 8T and 10T cell provide this feature
6T cell where two MOS are added provide read operation without
disturbing the internal node. This significantly improve the SNM at the cost
of ~30% increase in area
10T SRAM cell shown below improve read SNM equal to hold SNM and
M10 reduces leakage current but cell still have single ended read operation
Cache is built with online BIST to detect faulty cells and a configurator for
remapping the faulty block
Cache line deletion: In this faulty lines are marked and excluded from
normal cache line allocation and use.
RAZOR
References