California Eastern Laboratories
AN82901-1
Application of Microwave GaAs FETs
INTRODUCTION
The history of converting microwave communications, as
well as other communications technologies, to solid state
electronics is a long one. Early advances were first made in
receivers, and then in transmitters. Progress in bipolar tran-
sistor technology and the production of new semiconductor
crystals during the 1960’s made possible the development of
such new microwave diodes as the GUNN and the IMPATT
(impact avalanche and transit time). For this reason, the
decade might well be called the renaissance of microwave
semiconductor devices. A series of microwave communica-
tions amplifiers appeared in the first half of the 1970’s which
used GUNN and IMPATT diodes. They played a leading
role in the trend toward solid state technology. In the middle
of the same decade, a commercially feasible gallium arsenide
field effect transistor (GaAs FET) appeared, and the uses of
this device are still increasing. In the latter half of the 1970’s,
demands grew for systems more reliable than those using
IMPATT and GUNN diodes. Users were demanding greater
reliability, and those engaged in research and development
began working toward this goal. The work is still going on
today.
The demands of the industry turned the emphasis away from
creating new devices to developing competition among manu-
facturers of semiconductors to produce devices of higher per-
formance and greater reliability. Commercialization of GaAs
field effect transistors led to lower energy consumption and
smaller microwave components and systems. These are still
major concerns today. With new developments in infor
mation, communications and applied microwave systems,
the GaAs FET has become an indispensable item.
1. THE FIELD EFFECT TRANSISTOR (FET)
In 1952, Shockley conceived the structure of the field effect
type transistor and pointed out that it could be used for am-
plifier devices. Due to manufacturing difficulties, particu-
larly in production technology, the field effect transistor was
little known until the early 1960’s. The level of technology
at the time made it very difficult for people to understand the
importance of the FET. But with the development of planar
technology, the micro wave semiconductor industry grew with
explosive rapidity.
There are three major types of FETS. The simplest of the
three is the junction FET (JFET). Because of its simplicity
and ease of manufacture, the JFET was the earliest to be
produced commercially. It was put on the market about the
APPLICATION NOTE
9/82
same time as the first microwave bipolar transistor.
With the development of semiconductor manufacturing tech-
nology and the need for lower energy consumption, the metal
oxide semiconductor FET (MOSFET) appeared. The
MOSFET, like the JFET, was first developed for applica-
tions in circuits that demanded high impedance, such as in-
put circuits in analytical instruments. Field effect transis-
tors, particularly the MOSFET, became widely known for
their use as discrete devices in UHF band communications.
However, having focused solely on performance for many
years, nothing in the microwave band appeared on the mar-
ket which was superior to the bipolar transistor.
Around the time silicon reached its peak as a transistor ma-
terial, Schottky barrier type FETs made of gallium arsenide
appeared and quickly gained popularity by demonstrating
their high theoretical performance. This new device, known
as the Gallium Arsenide Metal Semiconductor FET (GaAs
MESFET) showed performance far superior to the bipolar
transistor.
This new device provided lower noise and higher gain in
established solid state applications. It also provided high
frequency characteristics previously unavailable from bipo-
lar transistors. It is made by using gallium arsenide (group
III-V); one of the semiconductor com pounds which has been
researched continually since the latter half of the 1960’s.
The electron mobility of gallium arsenide is five to seven
times that of silicon.
Gallium arsenide crystal technology was used to produce
the GUNN, varactor and Schottky diodes, and proved to be
far better than silicon in high frequency performance. A
GUNN diode made of silicon would be inconceivable, so the
appearance of the contemporary GaAs FET contributed
greatly to developing and commercializing the GUNN di-
ode. The reason for this is that even though the GaAs
MESFET is a three terminal device, it is simple in structure
and its performance depends only on the crystal quality.
Advances in crystal technology have made the commercial-
ization of FETs possible.
The GaAs FET is what is generally referred to as a “nor-
mally ON” type device. Its basic difference from the
MOSFET is the use of a Schottky barrier at the gate instead
of an oxide layer. This is an extremely important point. In
other words, almost no GaAs FET gates are insulated from
the channels in terms of direct current. Thus, even though
GaAs FETs are called “normally ON” type devices, the maxi-
mum gate voltage must be zero. It does not use a dielectric
like the MOSFET, so if a positive voltage is applied at the
AN82901-1

gate, direct current flows through it. Since the gate is a very Mutual conductance is defined as the ratio of the change in
small piece of metal (0.5,µ—1.Oµ—2.0µ), the gate electrodes direct current to the minor change in voltage between gate
will fuse completely in almost all cases. sources. This is generally described as the square-law char-
Figure 1 shows the properties of a GaAs MESFET. In al- acteristic and is shown in the equation for ID in Figure 2.
most all cases, a linear amplifier circuit biases the GaAs
MESFET. This applies to other circuits as well, but consid- 2
V GS (1)
ering gate bias alone, the range must be from IDSS, i.e., ID = IDSS 1-
VG = 0 V, to IDS = 0 (at pinch off, VG = VP). In this range, the VP
voltage VDS between the drain and the source has little effect
on the current IDS flowing through the channels. By chang- When ID in expression (1) is differentiated with
ing the gate voltage, VG, the drain to source (channel) cur- respect to VGS, the result is
rent can be controlled. Figure 2 shows the transfer charac-
teristics of a GaAs FET with n channels. This FET transfer dID 2IDSS V GS
=- 1- = gm (2)
characteristic is an important basic parameter in circuit de- dVGS VP VP
sign because it sets the bias conditions and operating point. and the mutual conductance for each value of VGS can be
The operating point line in Figure 2 is directly related to the obtained.
mutual conductance, gm.

II. GaAs FET BIAS AND OPERATING POINT

The most important characteristic to consider when design-

VG=0
ing a bias circuit for small signal GaAs FETs is the previ-
DRAIN CURRENT ( ID )

ously mentioned transfer characteristic. Generally, two meth-

VG = -1 V ods can be used to bias a GaAs FET.

-2 V 1. Dual Power Source Method

Figure 3 shows a bias circuit which uses the dual power
-3 V source method. Since the condition

VP < VGS < 0

DRAIN TO SOURCE VOLTAGE ( VDS )
must always apply to a GaAs FET, VGS can be derived from
expression (1)

Figure 1. Typical GaAs FET DC Characteristics ID (3)

VGS = VP 1 -
I DSS

2. Self Bias Method (Auto-Bias)

Figure 4 shows the most universal method for reducing
electrical potential between a gate and the source when there
is only one power source. If the source resistance is RS, and
ID the operating current is ID, then the drop in electric poten-
V GS
2 tial caused by RS will be
I D = I DSS 1
VP
ID x RS

The actual electrical potential between the gate

and the source will be

VGS = -ID . RS (4)

VP V P /2 0
VG

Figure 2. Square-Law Characteristic

 AN82901-1

which is negative, so the FET can be turned on. The value inductance and care must be exercised when using them at
RS is obtained by combining expressions (3) and (4). higher frequencies. Types D and E in Figure 5 require only
one power source. They are compatible with the previously
VGS VP ID described method. An advantage of this method is that if
RS =- =- 1- (5) the source voltage should increase for any reason, that in-
ID ID I DSS crease will be proportionate to the drop in potential caused
by RS, which is connected in series with the source,
Therefore, these are the basic bias principles.
RS X ∆ID

BIAS ORDER BIAS POLARITY

IDSS (1) VG NEGATIVE VG

(2) VD POSITIVE VD
(a) VG
VD

ID
(1) VS POSITIVE VS

VP VGS 0 (2) VD POSITIVE VD

VGS VS VD
(b)

Figure 3. Dual Source Bias Method

(1) VG NEGATIVE VG

(2) VS NEGATIVE VS
(c) VG VS
I DSS
RS = b
a
ID
VD ONLY POSITIVE VD
b

RS a RS
ID
(d) VD

VP V GS VG ONLY NEGATIVE VG
I D X RS
(e) VG

Figure 4. Self (Auto) Bias Method Figure 5. GaAs FET Bias Circuits

Figure 5 shows the five general bias types: A, B, C, D, and
E. Type A is the previously described dual power source
bias method appropriate for use in the higher frequencies.
When directly connecting the source to the ground terminal,
source inductance can be made relatively small. By using
this method, higher gain can be obtained and a lower noise
factor anticipated in the higher frequencies.
All other bias methods insert a bypass capacitor into the
source. Even if the high frequency performance of the by-
pass capacitors can be guaranteed, there will always be a
loss (tan δ) resulting from the material’s dielectric proper-
ties. Even with chip capacitors, there is always some
Here, ∆ID is the increment in drain current caused by the
increment in source voltage.
Drain current increase will be automatically suppressed, due
to the proportionate negative bias on the gate. Generally, if
a single source type (self biasing type) is selected, D is used;
if the only available source is a negative one, then E should
be selected.
Figure 5 shows the order for adding bias when a dual power
source is used. This is to prevent, as much as possible, a
AN82901-1

large current from flowing through the FET. The GaAs FET at the center of the bias line and wanders off in some direc-
being discussed here generally has a high mutual conduc- tion, the wave form will be distorted. Also, the amplification
tance, giving it excellent frequency characteristics. If the operation will be degraded, and DC will flow through the
gate voltage is near zero, gm is at a maximum and oscillation gate. In a similar manner, the maximum variation in voltage
may occur. For this reason, a bias scheme should be adopted between the gate and the source when there is no signal is
that first applies a negative bias to the gate and then turns on
the drain with a positive bias. There are slight differences ∆VGSQ = VGSQ(max) - VGSQ(min)
between a bias circuit for a small signal GaAs FET and one
for a power GaAs FET, but the above methods can be con- IQ is a function of both the temperature, T, and VGSQ
sidered for both.
Moving one step further, let’s examine a practical bias cir- IQ = f (T, VGSQ )
cuit. It is important to:
1. Obtain the necessary operating voltage and operating If, with a variation in temperature of δT, IQ changes by only
current, and δTQ .
2. Ensure a high level of stability.
δIQ = ∂IQ . δT+ ∂IQ . δVGSQ
∂T ∂VGSQ
RD
∂IQ . δT - gmδIQ R. S
=
∂T
and from this
RS
I DSS(max)
∂IQ .
δIQ (1 + gmRS) = δT
∂T
is obtained.
RS
I DSS(min) If RS = 0, that is, if there is no series resistance, then
I Q(max)

I Q(min)
∂IQ . δT = δI (0)
Q
∂T
V P(min) V P(max) VGS(max)
represents the drift. The bias stability coefficient is defined
VGS(min)
as

Figure 6. Possible Bias Points Fluctuation in IQ with respect to RS

S=
Fluctuation in IQ with independent of RS

Figure 6 shows the bias graph, indicating all possible bias
points. Bias will be in the range determined by
VGSQ = IQRS
Given the bias range, the operating point for the maximum
amplitude value, P, and the operating point where there is
no signal, Q can be obtained. The change in IQ from point P
to point Q, or ∆IQ, becomes
∆IQ = IQ(max) - IQ(min)
= δ IQ = 1 (6)
δIQ (0) 1 + gmRS
This means that fluctuation in the entire circuit is reduced by
means of negative feedback due to RS. This effect is particu-
larly important when using small signal FETs.
Figure 7 gives an example of a bias circuit. Since IDSS and
VP often vary between devices, it is important that the bias
circuit can absorb such variation, the optimum operating point
can always be established, and operation is stable regardless
of ambient temperatures. The circuit in Figure 7 is basically
a fixed bias circuit and not a self bias circuit.

This shows that with a variation in IQ, the drain voltage will
change only as RD . ∆IQ. If the signal midpoint is not fixed
 AN82901-1

Feedback is applied to the circuit by the insertion of RS into If there is no signal, the drain current ID is
the source.
2
vgs (7)
i D = IDSS 1 -
Vp

VR L1
+Vcc
Vout

C1
RF
Vin
VDD
RS

Rs
V
KF=
4(VGSQ PP)(1+gmRF)

IM= V1V2
2(VGSQ VP)(V12+V22) 1/2(1+gmRF)

Figure 7. A Low Cost, Stable Bias Circuit
As stated previously, since the voltage between the gate and
the source is VGS = -IDRS in a self bias circuit, and if ID is
known, RS can be readily determined. In such a fixed bias
circuit as the previously mentioned dual source type, the gate
voltage is selected independently of RS and ID. Thus, it is
understood that the value RS can be higher than that when
using a self-bias circuit, and the stability coefficient S can
therefore be improved.
Figure 8. Improving the Distortion Factor
Using a Series Feedback Resistance RF
Adding a simple sine wave voltage (Vsin wt) to the non-
signal voltage results in
υgs = VGSQ + Vsin wt
If the expression is rearranged and substituted into the fol-
lowing, then the harmonic distortion KF is

Relative value of second harmonic

III. GaAs FET CHARACTERISTICS AND KF =
Relative value of fundamental harmonic
APPLICATIONS

In this section, examples and explanations of GaAs FET
applications will be given. The first issue is the argument as
to whether or not the FET is better than the bipolar transis-
tor because of the FET’s cross modulation characteristic.
Discussion will then turn to applications of the small signal
FET and the large signal or power FET.
1. Distortion Factor
The transfer characteristic of a GaAs FET can be approxi-
mated using a quadratic equation, as was shown in expres-
sion (1). If the transfer characteristic could be perfectly rep-
resented by such an equation, then the second harmonic will
increase to its maximum and will actually include the higher
order harmonic components. To determine the value of the
second harmonic for a basic frequency, substitute the total
input voltage and total output current into the equation.
= V (8)
4(VGS - VP)
V is the maximum amplitude of the signal.
As expression (8) shows, the distortion factor approaches its
minimum as VGSQ approaches zero. However, as the input
signal increases and enters the realm of forward gate bias,
quite naturally the distortion factor increases.
Next, we will consider what happens to the cross modula-
tion (intermodulation) produced when two sine wave sig-
nals are amplified at the same time. That is
VGS = VGSQ + VI sin wt + V2 sin wt
Since the output current includes the sum and difference
components of two sine waves, crossmodulation
AN82901-1

(intermodulation) distortion, IM, is defined as follows:
Relative value of
IM = Relative value of
cross modulation component
fundamental harmonic
V1V2
= (9)
2(VGSQ VP)(V12+V22) 1/2
Even here, we see that the distortion factor decreases as bias
is brought closer to VGSQ = 0. The main cause of the distor-
tion is the curve (non linearity) in the transfer characteristic
line, but there are other causes as well.
Distortion can also be caused by the change in output con-
ductance, gd, related to the operating point and the drain
voltage, VDS. To improve distortion, carefully select gm and
gd, which to a certain degree work to reverse this effect.
Another point to consider is that since distortion can be pro-
duced internally, KF and IM can both be improved by apply-
ing feedback to the circuit.
As shown in Figure 8, by adding a resistance, RF, in series
with the source resistance, the distortion factor for the non-
bypass feedback is calculated, using expressions (10) and (11).
V of the commercially available GaAs FETs having character-
KF= 4(VGSQ VP)(1+gmRF) (10)
V1V2
IM= 2 2 (11)
2(VGSQ VP)(V1+V2) 1/2(1+gmRF)
in terms of noise, gain and output-power saturation char-
acteristics. Other than their primary use in ultra-high fre-
quency amplifiers, such as those for electronic countermea-
sures (ECM), most small signal FET applications are in low-
noise amplifiers. They are used in both line-of-sight and
over-the-horizon microwave communications, and in earth
stations communicating with satellites.
A low noise amplifier is designed by minimizing the noise
measure, M, shown in expression (12).
M+1=1+ NF - 1 (12)
1 - (1/G)
NF is the amplifier noise factor.
G is the amplifier gain.
In single-stage amplifiers, the general procedure for match-
ing input circuits is to mimimize the noise factor, NF; for
matching output circuits, the gain is maximized.
From observations of the input-output impedances of a GaAs
FET, it is noted that there is generally a difference in imped-
ance between maximum gain and minimum NF. This dif-
ference is particularly apparent at lower frequencies. As the
frequencies go higher, the difference seems to decrease. The
noise factor, which is a function of device gain, will be low
when the gain is maximized at high frequencies. However,
istics which allow a gain of 8 to 10 dB or more, there is still
a difference between the impedance at maximum gain and
the impedance at miminum NF. This difference will be seen
until the frequency range approaches the X band.

By applying feedback to the circuit, both the distortion factor

and the bandwidth can be improved. The value of RF will
reduce the total gain only by its relative portion. It is pos-
+1.0
+0.8

+1.5
sible to have a wide-band amplifier with a low distortion fac-
6
+0.

.0
tor by initially designing the amplifier for high gain and tun-
+2
5
S2 4
ing the gain to its optimum level by using feedback.
.4

12 2 6
+0

S11 GHz

GH +3
3
1

z
2

+4
11

2. Small Signal FET Applications 2

+0.
Z Fopt 2 +5

The first practical and commercially available GaAs FET 7

10
was introduced around 1973. Since then, many small signal
9 8 GHz
amplifying devices with 1µm gate lengths and smaller have 11
0.8
0.6

2.0
1.0
0.4

been marketed.
0

8
The greatest advantages for these devices are found in the
higher frequency bands. Compared to the silicon bipolar 7
-0.2
2
-5
transistors and tunnel diodes, GaAs FETs are far better 10
6 -4
3
-3
9
.4

4
-0

2
8
7
5

0
6

-2.
-0.6

3
-1.5
4
-0.8

-1.0

Figure 9. Frequency Characteristics Of S1l, S22,

and ZFopt in the NE24406

Figure 9 shows S11 and S22, indicating input output imped-
ance for the NE24406 and the signal source impedance when
the noise factor, NF, is minimized. Circuits can be matched
using these impedances. As mentioned previously, input
circuit matching is accomplished by matching to ZFopt; and
output circuit matching is accomplished by matching to S22.
In the design of a multi-stage amplifier, the first and second
stages are designed so that (M + 1) will be minimized, and
the third and subsequent stages are made in such a way that
their gain is maximized. Or, alternately, the amplifier can
be designed according to the characteristics determined by
the frequency and the device.
One impedance matching circuit, shown in Figure 10(a), is
the well known Tchebycheff filter type multi-stage imped-
ance matching circuit. The distinctive feature of this circuit
lies in its applicability to the input/output circuits of wide-
band amplifiers. In many cases, the circuit is used in ampli-
fiers covering the band range 8 GHz to 12 GHz and above.
Although this type of matching network was originally ap-
plied to comparatively narrow bands (such as a 500 MHz
bandwidth at 4 GHz), the matching circuits shown in Figure
10(b) and (c) are now believed to be best suited for bands
having approximately a 10 to 15 percent ratio to the
amplifier’s center frequency.
IMPEDANCE ADMITTANCE
INVERTER INVERTER
λ/4
_ l 34 _ l 34 _ l 23
jX 34
(a)
l2
l1 λ/4
λ/4
(b)
Figure 10. GaAs FET Matching Networks
AN82901-1
For these bandwidths, the NF can be reduced to its lowest
absolute value. If the widest possible bandwidth is the ob-
jective, then reduction of the NF to its absolute minimum is
not possible throughout the band. In the former amplifier,
the most important consideration is reducing, as much as
possible, the loss in the impedance matching circuit. The
Tchebycheff filter type impedance matching circuit in Fig-
ure 10(a) uses a large number of components and is not well
suited for obtaining a low loss matching network.
As Figure 9 shows, both S11 and S22 go from capacitive to
inductive with increasing frequencies. Consequently, S11
and S22 can use the circuit in Figure 10(b) for frequencies
which exhibit a capacitive response, or the circuit of Figure
10(c) for the frequencies which exhibit an inductive response.
In Figure 10(b), for frequencies slightly higher than the
amplifier’s center frequency, the GaAs FET input or output
has a resonance of either L1 or L2 (with a reactance of 0),
which is then matched to the desired impedance by the λ/4
impedance conversion circuit. This is only one of the count-
less possible impedance matching circuits. However, this is
a very effective design method for low noise amplifiers re-
quiring a band ratio of 10 to 15 percent when the amplifier’s
center frequency is 4 GHz or greater.
IMPEDANCE
INVERTER
λ/4 l
_ l 23 _ l 12 _ l 12
jX12
λ/4
C2
λ/4
C1
(c)
AN82901-1

3. Low Noise Amplifiers in the 4 GHz Band
Figure 11 is an example of a two-stage low-noise amplifier
for the 3.7 to 4.2 GHz band using either the NE21889 or the
NE72089. The matching circuit in Figure 11 is based on the
same idea as Figure 10(b). It uses a microstrip with an
0.8 mm thickness teflon glass fiber substrate and transistor
leads with lumped constant inductance. Figure 12 shows
the schematics. Figure 13 shows the gain and noise factor
normally obtained using this circuit.

THRU HOLES FOR

NE72089 SOURCE LEADS
4 PLACES

CEL 3.7-4.2 GHz LNA

10 pF 10 pF 10 pF 28.0 mm

IN OUT

69.6 mm
1000 pF SHIM STOCK TO GROUND
4 PLACES ALL 4 SOLDER PADS

Parts List: NE72089 FET (2 ea.) California Eastern Laboratories

10 pF Chip Capacitors (3 ea.) ATC #100A-100-J-P-X-50 or equivalent
1000 pF Chip Capacitors (4 ea.) Johanson #50R11W102KP or equivalent
1500 pF Feed-through Capacitors (4 ea.) Erie #2425-003-W5U0153AA or equivalent
Ferrite Beads (4 ea.) Fairrite #2643001301 or equivalent

Figure 11. PCB Layout of a 2-Stage Amplifier in the 3.7 GHz-4.2 GHz Band

λ/4
TRL2(Z0)
TRL1 Z0 C3
Z0 TRL3
C2
λ/4
λ/4
C1
λ/4 λ/4 λ/4 SST4
C13 C14 C15
SST1 SST2 SST3
C4 C5 C6 C7 C8 C9 C10 C11 C12

Vd2
Vg1 Vd1 Vg2

Figure 12. Schematics for a 3.7 GHz-4.2 GHz Band 2- Stage Amplifier
 AN82901-1

4. Low Noise Amplifiers in the 1 GHz Band

Figure 14 shows a PCB layout for an amplifier designed for
25 4.0 low noise operation in the 1 to 1.4 GHz band. Since the

NOISE FACTOR, NF (dB)

microstrip lines used are very thin, the diagram shown here
is twice the actual size. During the design, it should be drawn
GAIN, G (dB)

3.0 four times the actual size and then reduced.

Figure 15 shows the equivalent circuit. In the design of this
G
circuit, a band ratio of 10 to 15 percent was not obtained as
20 2.0
with the previous amplifier. Instead, emphasis has shifted
to making the band as wide as possible and the noise factor
NF
1.0 as low as possible. Since it is in the relatively low-frequency
3.5 3.7 3.9 4.1 4.3 4.5 1 GHz band, the loss due to the reactance elements (includ-
FREQUENCY (GHz) ing the microstrip) was not given much concern. The
Tchebycheff filter type multi-stage impedance matching cir-
cuit could have been used. However, considering the fre-
Figure 13. Frequency Characteristic of NF and G for the quencies involved and the large physical size of such a cir-
cuit, a method was chosen that gives the transmission line
NE72089 2-Stage Amplifier
as high an impedance as possible for input and output, and
which would gradually match to the characteristics imped-
ance of 50Ω. Figure 16 shows the typical performance char-
This two-stage amplifier uses the inductance in the first stage
input section to produce resonance. Then, using the λ/4 acteristics of this amplifer.
impedance transformer, it forms a matching circuit for the
50Ω characteristic impedance. Since there is a relatively
small difference in values between S11and S22, the inter-
mediate stage matches impedance by the simple means of a 120 Ω 70 Ω 70 Ω 85 Ω
77 Ω 70 Ω 70Ω
transmission line. 120 Ω
2SK281 1.8 pF
4 pF
Output matching is done in the same way as in the first step, 70 Ω 60 Ω
74 Ω 94 Ω
i.e., the matching circuit shown in Figure 10(b) is used. Fig-
ure 11 is a full-scale pattern showing lines and open stubs
inserted in parallel. Although these are not necessary for
the ideal design, they are included to correct impedance
matching problems caused by the printed circuit board con-
Figure 15. Equivalent Circuit for a NE72089
nectors (microstrip to coaxial connection) and the DC block-
ing chip capacitors. They are inserted after the design is Low-Noise Amplifier
completed.

4.625 cm
24
G 4

NOISE FACTOR, NF
THROUGH-HOLES
GAIN,G (GHz)

20
3
16
2
12 NF 1
IN OUT 8
1.1 1.2 1.3 1.4 1.5

FREQUENCY (GHz)

0.85 cm
Figure 16. NE72089 Low-Noise Amplifier

MATERIAL 0.8 mm THICK TEFLON GLASS When this amplifier was designed, a 4 pF blocking chip ca-
pacitor was used as part of the matching circuit, as shown in
Figure 14. PCB Layout for 1.0-1.4 GHz Amplifier Figure 15. The input matching circuit was designed chiefly
AN82901-1

to obtain matching for the noise factor. The data used for 5. Applications to Other Amplifiers
the NE72089 is shown below:
(A) A technique of attaining wide band performance by
inserting a source inductance.
f ΓFopt* Fmin G NF @ 50 Ω L. Neven, et al., have proposed a type of feed back circuit for
1 GHz 0.59<32.5 0.6dB 17.5 dB 1.73 dB relatively low frequency GaAs FET amplifiers. For amplifi-
1.3 GHz 0.65<47.0 0.6 dB 15.0 dB 1.74 dB ers operating in the 1 GHz to 2 GHz range, these circuits
VDS = 3 V, IDS = 10 mA guarantee a low noise factor as well as good input-output
impedance.
*(I' Fopt signifies the reflection coefficient obtained when comparing the
Figure 18 shows what is considered the universal GaAs FET
signal course impedance with 50 Ω when NF is minimized)
equivalent circuit. In this circuit, drain noise current, Idn, is
The bias circuit used to actuate this amplifier is shown in referred to the input by the Vander-Ziel theory, then the gate
Figure 17. The figure shows a bias circuit for a two-stage source resistances, Ri, becomes noiseless and, RS remains
amplifier. For a single stage amplifier, only one half of the noisy. The noise currents at the gate and drain have been
redundant portion of the circuit would be used. This circuit removed from the two-port. The circuit in Figure 18 is bet-
is a constant voltage, constant current type bias circuit, one ter handled by computers, where the noise and signal are
of the most applicable examples of circuits for use in small- compared as a function of the externally added source in-
signal amplifiers. ductance. In this instance, it is easier to consider the equiva-
lent circuit shown in Figure 19.

15V 2N3643
DUAL
15V
POWER 330
330
SUPPLY
1
2 A1 R2 R3
15V (3V) 500 (3V) 500 (3V)
V DS1 V DS2
100K 100K
10K 100K 4.7µF
2 A1
1
R1 4.3K 4.3K
500 1
2 A2 V GS1 1
2 A2 V GS2
(3V) 100K 6.8V 6.8V
3.3K 3.3K
.01µF .01µF
2.2K 6.8V

100K 100K
5.6K

A1 AND A2: 747 DUAL OP-AMP

ALL RESISTORS: 1/4 Watt

Figure 17. Two Stage GaAs FET LNA Bias Supply

LG RG Cgs Rd Ld en

+ -
Ci
gd
Ri
g mV I dn IC NOISELESS
Cds TWO-PORT
Iu
RS

LS

LS '
EXTERNAL SOURCE INDUCTANCE
EXTERNAL SOURCE INDUCTANCE

Figure 18. Universal GaAs FET Equivalent Circuit Figure 19. Cascade Connection of Device's Noise
and S-Parameter Circuits
 AN82901-1

Figure 19 shows the cascade connections of the device’s noise
and S-parameter equivalent circuits. The circuit should be
10.6 nH
10 nH
1.5 nH
NOISE FACTOR, NF (dB)d GAIN, G (dB)
designed so that matching is obtained for the input-output
impedance given to this equivalent circuit. After the design
goals have been chosen, the noise figure, NF, and impedance
matching networks are calculated. The circuits and charac-
teristics of an amplifier designed by this method are shown
in Figures 20(a) and 20(b).
0.8 pF
0.13 11.4 (B) Ultra-wide band amplifiers using GaAs FETs.
pF nH
The method normally used to achieve wide-band amplifica-
tion involves applying negative feed back to the transistor.

This method improves the VSWR and dynamic range char-

13 acteristics and also ensures very flat gain response. Another
G
12 method for achieving wide-band amplification involves us-
11 ing a balanced amplifier design which ensures good VSWR.
This method is widely used in applications that cover fre-
quency ranges of one to several octaves in the higher fre-
SWR quency bands. However, it is difficult to obtain a very wide
8 band using a 3 dB, 90° coupler while also trying to ensure
ISWR
6 good input-output VSWR in ranges exceeding 10 octaves, or
2 NF 4 in the low frequency ranges. Figure 21 shows an equivalent
1 OSWR 2 circuit for the balanced amp.
1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (GHz)
(a) IN 3 dB, 90˚ 3 dB, 90˚
Figure 20(a). Lumped Element Matching Network Zo
AMPS (BOTH ARE
THE SAME)
λ 4 @ 1.5 GHz
10 n H 60 Ω
10 n H
Zo OUT

1.5 n H
Figure 21. Balanced Amplifier Allowing
Wide-Band Amplification
GAIN, G (dB)

15
The use of GaAs FETs with negative feedback is an effective
14 method of ensuring low cost and simplicity for bandwidths
G
13
exceeding 10 octaves.
Figure 22 shows the basic circuit for negative feedback am-
12 plifiers. For the sake of simplicity, the DC bias circuit and
NOISE FACTOR, NF (dB)

the coupling capacitors have been omitted. If the character-

SWR

4 istics of the GaAs FET to be used are suitable at frequencies

ISWR 3 of 10 MHz to 2 GHz, the device’s parasitic elements will be
2 small in size, and the equivalent circuit can be simplified to
OSWR 1 that shown in Figure 23. The simplified equivalent circuit
2
shown in Figure 24 is obtained by adding the negative feed-
1 NF
back resistor shown in Figure 22 to the circuit in Figure 23.
0 The S-parameters may now be calculated for this situation.
1.3 1.4 1.5 1.6 1.7

FREQUENCY (GHz)
(B)

Figure 20(b). Transmission Line Matching Network

AN82901-1

2
gmZ 0
R2
S 11 = 1 1 -
∆ R 2(1 + gmR1 ) (14)
OUT

IN 2
gmZ 0
S 22 = 1 1 -
R1 ∆ R2 (1 + gmR1 ) (15)

2Z0
S12 = 1
Figure 22. Basic Feedback Amplifier Circuit ∆ R2 (16)

-2gm Z0 2R0
S21 = 1 +
∆ 1 + gm R1 R2 (17)
GATE DRAIN

2
2Z0 gm Z 0
V gs gm V gs ∆ =1+ +
R2 R2 (1 + gm R1)

SOURCE Assuming that a negative feedback amplifier must improve

VSWR, the input and output reflection coefficient must be
0, then expressions (14) and (15) become
Figure 23. Equivalent Circuit for GaAs at Low Frequency
S11 = S22 = 0

The admittance matrix can be determined by using the From this, the following expression can be derived:
following expression. g m Z 02
1 + = g m R1 = (18)
R2

1 1 When expression (18) is substituted into expressions (16)

and (17), the following results are obtained
I1 R2 R2 V1
= (13)
I2 gm 1 1 V2 Z 0 — R2 (19)
S21 =
1 + gmR1 R2 R2 Z0

Z0
S12 = (20)
R2 + Z 0
I1 R2 I2
Then, using expression (18), R1 is obtained as follows

gm Vg 2
Z0 1
Vg R1 = – gm (21)
V1 V2 R2
R1
Since the transconductance, gm, in a GaAs FET is not usu-
ally large enough, the equation S11 = S22 = 0 will not be
Figure 24. Simplified Feedback Amplifier satisfied. However, the range of the gm values needed to
Equivalent Circuit satisfy the expression can be calculated. If R1= 0 then

S21 = I - gmZo (22)

If at this time, the input-output for Figure 24 is terminated
at Z0, the S matrix can be easily obtained by using expres-
sion (13).

is obtained, and thus
gm| min = 1 - S21 (23)
Zo
For example, consider the design of an amplifier with 10 dB
gain. Logically, if we take the input output VSWR as a low
value and the characteristic impedance, Z0, as 50Ω, when
S11 = S22 = 0, then substituting this in expression (23) yields,
1 - (-3.16)
= 0.082 S
50
It will therefore be acceptable if gm⊕83mS. Figure 25 shows
the characteristics of an ultra wide band amplifier designed
using this method.
8
6
GAIN, G (dB)
4 covered only those signal levels in the range in which oper-
2 signal current. In other words, each terminal’s voltage and
0.01 0.1 1 10
FREQUENCY (GHz)
Figure 25. GaAs FET Feedback Amplifier
6. Relation of Ambient Temperature, Frequency
and Noise Temperature in GaAs FETs
Up to this point, only the applications of GaAs FETs in am-
plifiers have been examined. Now, the discussion will turn
to the relationship between ambient temperature and noise
temperature.
Noise in a GaAs FET is chiefly thermal noise. Since there is
rarely shot noise, the noise temperature in an amplifier
changes greatly in response to the ambient temperature. Fig-
ure 26 shows the relationship of operating temperature and
the noise temperature for the NE67383/NE71083. The noise
temperature, Te and ambient operating temperature, Ta, can
be shown to correspond to the following:
ωCgs
Te = K TA (24)
gm
Figure 26 shows the linearity in the relationship between the
ambient operating temperature and the noise temperature.
By taking advantage of this characteristic, a super low-noise
amplifier can be produced by cooling the amplifier with car-
bonic gas, liquid nitrogen or liquid helium.
AN82901-1
300
250
NOISE TEMPERATURE, T (K)
200
12GHz
150
100
4GHz
50
0
100 150 200 250 300 350
GaAs FET OPERATING TEMPERATURE, Ta (K)
Figure 26. Te vs. Ta for the NE67383/NE71083
7. Power GaAs FET Applications
For the small signal GaAs FETs discussed so far, we have
ating characteristics are not dependent on signal voltage or
current was in a range which satisfied a linear relationship.
As the signal level increases, this relation- ship is no longer
satisfied and we have a situation known as large signal op-
eration. Of course, even if the element is in non-linear op-
eration, the electrophysical quantity of the signal frequency
is still in a linear relationship if non-linearity is small. Thus,
the S-parameter relationship in a GaAs FET can be deter-
mined for small signal operation.
Because the voltage and current-to-terminal conditions which
define each parameter are not fixed for large signal opera-
tion, it is difficult to determine parameters indicating a lin-
ear relationship.
Figure 27 is a simplified diagram showing the small and
large signal operation of a Class A GaAs FET. Load lines A
and B indicate the optimum conditions for maximum input
and output when the input gate signal voltage is VGA and
VGB.
The optimum load for small signal operation is equal to the
drain conductance (∂IDS /∂VD). In large signal operation,
however, the input signal level will increase and gate volt-
age, VG, will enter the nonlinear zone. The output current,
which is the drain current, ID, will then reach its upper limit
and the load line gradient must increase to increase the out-
put power. Therefore, when designing a circuit, it is neces-
sary to use data which takes all factors into consideration.
AN82901-1

I DS

iD B VG =0

i DB A
i DA P VGB
VGB
t
t1

VDS
VD

t1

VDA

VDB
t
Figure 27. Simplified Load Line for a Class A GaAs FET in Small and Large Signal Operation

8. Operating Methods for Power GaAs FETs

(A) Introduction
An important factor to consider when working with Power taken at this time since the amount of gate current has a
GaAs FETs is power GaAs FETs are basically a group of bearing on whether or not the FET will be destroyed.
small signal GaAs FETs connected in parallel so that they
can handle a large power source. Therefore, they have an
extremely high transconductance. Another important and 10

GATE CURRENT (mA)

necessary factor to consider is at which bias point operation 5
takes place. Consideration must be given as to whether there 0
is adequate bias resistance to suppress the gate current. As
5
mentioned previously, Schottky gates are used in a GaAs
10
FET, and there is the possibility that the operating point will
cause an excessive current to flow across the gate.
OUTPUT, Pout (dBm)

The gate structure in a GaAs FET is very delicate, with a

30
typical gate length of 0.5/µm to 1.0µm. In some cases, just
a slight current flow across the gate will have a current den-
sity of 106A/cm2. With such high current density, the gate
DRAIN CURRENT (mA)

will eventually fail.

Figure 28 shows the change in input-output characteristics
due to the increasing gate current. Here, the operating drain 20
voltage is constant, but direct current begins to flow in the 1.3
opposite direction at the gate when the input signal level is 1.2
increased sufficiently. When the input signal power increases, 1.1
the Schottky gate is biased in the forward direction and gate
current begins to flow in that direction. Caution must be 10 20 30
INPUT, Pin (dBm)

Figure 28. Relationship of Input-Output Characteristics to

Increasing Gate Current
 AN82901-1

(B) Bias Circuits One thing that is very basic when biasing power GaAs FETs
Table 1 shows the maximum allowable gate current for is the need for increased impedance of the gate bias circuit.
each of NEC’s high power GaAs FETS. Care should be The example in Figure 29 shows a type of feedback circuit
taken at all times when planning bias circuits and input power incorporating a resistor in series with the bias circuit which
to ensure that these values are not exceeded. produces a drop in potential when the current across the gate
begins to increase, and adds to the gate series bias. By in-
NE8001 3.0 mA serting a low pass filter, such as an RFC or capacitor, unnec-
NE8002 6.0 mA essary oscillation or phase shift will be prevented.
NE8004 10.0 mA Another important factor is the order in which bias is ap-
NE8008 15.0 mA plied. It is generally disadvantageous, both thermally and
NE3716 20.0 mA electrically, to self-bias a power GaAs FET. Therefore, a
NE9000 0.5 mA positive and negative dual power source should be used to
NE9001 1.3 mA bias the drain and gate separately. For a GaAs FET, maxi-
NE9002 2.6 mA
mum current will flow when the gate voltage is at zero. With
a high output level FET, IDSS is sometimes greater than sev-
NE9004 5.0 mA
eral amps and since typical gm is extremely high, oscillation
NE9008 8.0 mA
will occur and the FET will be destroyed either thermally or
NE8681 3.0 mA electrically. For this reason, any appreciable flow of high
NE8682 6.0 mA current must be prevented from reaching the drain. The
NE8684 10.0 mA bias method used must be one whereby negative voltage is
NE8688 15.0 mA applied to the gate first, after which positive voltage is ap-
NE8691 1.3 mA plied to the drain. The following is a detailed example of
NE8692 2.6 mA this method.
NE8694 5.0 mA (1) Add a negative potential to the gate which is
close to -5V or to the pinch off voltage.
Table 1: Maximum Allowable Gate Currents for the NEC (2) Specify the drain voltage in such a way that
Power GaAs FET Series it moves as rapidly and smoothly as possible from zero volts
to the preset VD. If there is no possibility of a surge voltage
being produced and the drain voltage is completely stable,
add the preset voltage instantaneously.
Figure 30 gives three recommended bias circuits for biasing
power FETS. Figure 30(a) is an excellent bias circuit be-
V R 1000 pF RFC TO GATE cause there are no limitations requiring that either positive
or negative voltage be applied to the circuit first. Drain volt-
age, VD, will reach its preset value according to the time
1 µF 4.7 pF
VR

Figure 29. Example of a Gate Bias Circuit

STABILIZED
V VD V VD V VD

-
R D1 +
C
STABILIZED
V V G STABILIZED VG
V
V VG
(a) (b) (c)

Figure 30. Power GaAs FET Bias Circuits

AN82901-1

Q3 .1 2W
A
+ VDS
S1A 2A Q2 1K
3 1 100 .0003 47µF

+ 6 4
10µF Q1
9 IC1 5
DUAL
±15V
5V R1 .001
2K 20K 8 7

POWER 6.8K 2 10
SUPPLY .01µF

S1B
330 22 6 7

5 8
R2 R3
10µF 3 500 33
+ IC2
2.4K 2 .0003 + 47µF
VGS
1 9
Q1 - SK3448
Q2 - 2N706 10µF 2.5K
Q3 - 2N3771 +
IC1- MC1469
IC2-LM304

NOTE: 1) Ammeter is optional.

2) Q3 is mounted on external heat sink.
3) R1, R2 and R3 are mounted externally.
4) All resistors are 1\4 watt unless otherwise noted.

Figure 31. Power GaAs FET Regulated Bias Supply

constant determined by C and R. When the power source is
OFF, the electrical charge will pass through diode D1, and
return quickly to the power source side, thus the FET can
then be safely biased.
Figure 31 shows a bias circuit recommended for biasing a
multistage (5 stages) power GaAs FET amplifier.
9. Examples of C-Band Application Circuits Using NEC’s
Power GaAs FET Series
With the exception of the devices with the 96 package, NEC’s
C-Band GaAs FET series using multiple chips contain in-
ternal matching network (IMN) circuits within the packages.
The IMNs are not intended to match the devices to 50Ω but
to facilitate and reduce the external matching networks. The
GaAs FET series which are in 98 packages have both input
and output matching circuits close to VSWR, 1:2.5. The
devices in 95 and 98 packages which have internal match-
ing circuits are identified by the numbers -4, -5, (-5H), -6,
-7, (-7H), and -8. Each of these numbers indicates the
center frequency at which the IMN circuit is optimized and
tested. For example, -4 is at 4 GHz (3.5-4.5 GHz) and -6 is
at 6 GHz (5.5-6.5 GHz).
Figures 32 to 68 relate typical characteristics and illus-
trate application circuits using an 0.8mm thick teflon glass
circuit board. The units used in these charts are millimeters
(mm). Figure 69 gives AM-PM conversions for NE800,
NE371, and NE868 series. This data is particularly effec-
tive when designing a PCM transmitter. Figure 70 gives the
standard characteristics for the third order intermodulation
of NE800898-7H and NE868898-6.
This brief report explains current GaAs FET technology.
Improvement of device characteristics is a major goal for
both applied technology and research in electronics. GaAs
FET reliability has already been confirmed and there is little
doubt that FETs will eventually be used at frequencies of 40
GHz and higher.
 AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN OUT
28
20.0 20.0 P in = 18 dBm
3.0 4.0
3.0 26 f = 5.5GHz

Pout (dBm)
24

3.0
3.0
17.0

2.1
22

20
12 14 16 18 20 22 24
Pin (dBm)
Figure 32. NE800196, 5 GHz Circuit
4.9 5.0 5.1 5.2 5.3 5.4 5.5
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
28
P in = 18 dBm
IN OUT
26
20.0 20.0

Pout (dBm)
f = 6.5 GHz
4.0 4.0
9.0 2.0 24

22
4.0

4.0
17.0

2.1

20
12 14 16 18 20 22 24
Pin (dBm)

5.9 6.0 6.1 6.2 6.3 6.4 6.5

Figure 33. NE800196, 6 GHz Circuit f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm
30
P in = 22 dBm

IN OUT 28
f = 6.5GHz
Pout (dBm)

20.0 20.0
3.0 4.0 26

24
5.0

2.0
17.0

2.1

22
2.0

4 16 18 20 22 24 26
Pin (dBm)

5.9 6.0 6.1 6.2 6.3 6.4 6.5

f (GHz)
Figure 34. NE800296 Circuit

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm
34

P in=25 dBm
32

IN f=4.2GHz
OUT
Pout (dBm)

30
20.0 20.0
4.0 2.0 4.0
28

26
5.0

3.0
17.0

2.1

24
3.0

16 18 20 22 24 26 28
Pin (dBm)

3.6 3.7 3.8 3.9 4.0 4.1 4.2

f (GHz)
Figure 35. NE800495-4 Circuit
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
P in = 25 dBm
IN OUT
32
20.0 20.0

Pout (dBm)
5.0 3.0
30

f = 5.5 GHz
28

4.0
4.0

2.1
17.0

26

4.0
4.0

24
16 18 20 22 24 26 28
Pin (dBm)
Figure 36. NE800495-5 Circuit
4.4 4.5 4.6 4.7 4.8 4.9 5.0
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
34
IN OUT
P in = 26 dBm
20.0 20.0 32

3.0 5.0

Pout (dBm)
30

f = 6.5 GHz
3.0
4.0

2.1 28
17.0

26

24
16 18 20 22 24 26 28
Pin (dBm)

5.9 6.0 6.1 6.2 6.3 6.1 6.3

Figure 37. NE800495-6 Circuit
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm
34

IN OUT
32
20.0 20.0
P in = 26 dBm
2.0 5.0 5.0 3.0 2.0
Pout (dBm)

2.0 11.0 30
f = 7.2 GHz

28
4.0

3.0
3.0
3.0
17.0

2.1

26
3.0

24
16 18 20 22 24 26 28
Pin (dBm)
Figure 38. NE800495-7 Circuit 6.6 6.7 6.8 6.9 7.0 7.1 7.2
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 34
IN OUT

20.0 20.0 32

4.0 8.0 4.0 8.0 4.0 Pin = 26 dBm

Pout (dBm)

30

f = 8.4GHz
28
4.0
3.0
17.0

2.1

26

24
16 18 20 22 24 26 28
Pin (dBm)

7.8 7.9 8.0 8.1 8.2 8.3 8.4

Figure 39. NE800495-8 Circuit
f (GHz)
 AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 38
P in = 29 dBm
IN OUT
20.0 20.0 36

Pout (dBm)
3.0 3.0
10.0 14.0
34
f = 4.2GHz

5.0
4.0
17.0

2.1
32

4.0
30
22 24 26 28 30 32 34
Pin (dBm)
Figure 40. NE800898-4 Circuit
3.7 3.8 3.9 4.0 4.1 4.2 4.3
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 38
P in = 29 dBm

IN OUT 36
20.0 20.0 f = 5 GHz

Pout (dBm)
3.0 6.0 4.0 6.0 3.0
11.3 34
1.0
3.0

3.0

32
17.0

2.1

30
22 24 26 28 30 32 34
Pin (dBm)

4.4 4.5 4.6 4.7 4.8 4.9 5.0

Figure 41. NE800898-5 Circuit
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm 38
IN OUT

20.0 20.0 P in =29.5 dBm

36
5.0 2.0
10.0 17.0
Pout (dBm)

34
2.0
3.0
17.0

f = 5.5 GHz
2.1
2.1

32
4.0

1.0

30
22 24 26 28 30 32 34
2.0 1.0
Pin (dBm)

Figure 42. NE800898-5H Circuit 5.0 5.1 5.2 5.3 5.4 5.5 5.6
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm 38
IN OUT
P in = 29.5 dBm
20.0 20.0
36
2.0 2.0
Pout (dBm)

34
1.0

2.0

f = 6.4 GHz
17.0

2.1

32

30
22 24 26 28 30 32 34
Pin (dBm)
Figure 43. NE800898-6 Circuit
5.9 6.0 6.1 6.2 6.3 6.4 6.5
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 38

IN OUT
P in = 29.5 dBm
36
20.0 20.0
6.0 9.0 7.0

Pout (dBm)
34

f = 7.2 GHz
32

3.0
2.0
17.0

2.1
30

28
22 24 26 28 30 32 34
Figure 44. NE800898-7 Circuit Pin (dBm)

6.6 6.7 6.8 6.9 7.0 7.1 7.2

f (GHz)
MATERIAL -TEFLON GLASS
IN OUT THICKNESS: 0.8mm 38

20.0 20.0
P IN = 30 dBm
3.0
2.0

2.0 36
2.0
2.0
2.0

5.0 5.0

Pout (dBm)
1.5
34
3.0
f = 7.4 GHz

2.1
17.0
32

30
22 24 26 28 30 32 34
Pin (dBm)
Figure 45. NE800898-7H Circuit
7.2 7.3 7.4 7.5 7.6 7.7 7.8
f (GHz)
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 38
IN OUT

20.0 20.0 36
3.0 4.0 3.0
10.0 Pin = 30.5dBm
Pout (dBm)

34

f = 8.4GHz
32
3.0

2.0
17.0

2.1

30

28
22 24 26 28 30 32 34
Figure 46. NE800898-8 Circuit Pin (dBm)

7.8 7.9 8.0 8.1 8.2 8.3 8.4

f (GHz)
MATERIAL -TEFLON GLASS
IN OUT THICKNESS: 0.8mm 40
P in = 31.5 dBm
20.0 20.0
38
3.0 7.0 3.0
12.0
Pout (dBm)

36
5.0
4.0

f = 4.2 GHz
17.0

2.1

34
4.0

5.0

32
24 26 28 30 32 34 36
Pin (dBm)
Figure 47. NE371698-4 Circuit
3.7 3.8 3.9 4.0 4.1 4.2 4.3
f (GHz)
 AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 40
IN OUT P in = 32 dBm

20.0 20.0
38
7.0 10.0 3.0 3.0 4.0
f = 5.5GHz

Pout (dBm)
36

34

3.0
3.0
17.0

2.1
32

3.0

2.0
30
24 26 28 30 32 34 36
Pin (dBm)

3.0 10.0 4.9 5.0 5.1 5.2 5.3 5.4 5.5

f (GHz)

Figure 48. NE371698-5H Circuit

MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 40
IN OUT
P in = 32 dBm

20.0 20.0 38

5.0 8.0 7.0 3.0 3.0 3.0

f = 6.5 GHz

Pout (dBm)
36
4.0

4.0

34
3.0
17.0

2.1

32

30
24 26 28 30 32 34 36
Pin (dBm)
Figure 49. NE371698-6 Circuit
5.9 6.0 6.1 6.2 6.3 6.4 6.5
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm
40
IN OUT
P in = 32.5 dBm
20.0 20.0 38
4.0 7.0 3.0 3.0
f = 7.2 GHz
Pout (dBm)

36

34
5.0

4.0
17.0

2.1

32

30
24 26 28 30 32 34 36
Pin (dBm)
Figure 50. NE371698-7 Circuit 6.6 6.7 6.8 6.9 7.0 7.1 7.2
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm 40
IN OUT
20.0 20.0 P in = 32.5 dBm
3.0 3.0 2.0 4.0 38
Pout (dBm)

36 f = 7.7 GHz

34
4.0

2.0
17.0

2.1

32

30
24 26 28 30 32 34 36
Pin (dBm)

Figure 51. NE371698-7H Circuit 7.1 7.2 7.3 7.4 7.5 7.6 7.7
f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 30

Pin = +17 dBm

IN OUT

Pout (dBm)
30
3.5 3 4 3.8
14 6
20
f = 4 GHz

21 10.5 5
9 2

10
0 10 20
Pin (dBm)
Figure 52. NE868196, 4 GHz Circuit 3.5 4 4.5
f (GHz)

MATERIAL -TEFLON GLASS

30
IN OUT THICKNESS: 0.8mm
20 P in =17 dBm
3.5 3 8.5
7

Pout (dBm)
6.5

20
f = 5 GHz
15

10
2

10
0 10 20
Pin (dBm)

4.5 5 5.5
Figure 53. NE868196, 5 GHz Circuit f (GHz)

MATERIAL -TEFLON GLASS 30

IN OUT THICKNESS: 0.8mm
20 P in = +17 dBm
2.6 4 8.4
Pout (dBm)

8.3 5.2
f = 6 GHz
20
6.8
6.5
2
15

10
0 10 20
Pin (dBm)
5.5 6 6.5

Figure 54. NE868196, 6 GHz Circuit f (GHz)

MATERIAL -TEFLON GLASS 30

IN THICKNESS: 0.8mm
OUT
20 Pin =+ 17 dBm
3 3.5
10.5 11.5
Pout (dBm)

20
f = 7.2 GHz
VDS = 9 V
5

6
15

ID = 125 mA

10
0 10 20
Pin (dBm)
6.5 7 7.5
Figure 55. NE868196 Test Circuit (6.5 GHz and 7.5 GHz) f (GHz)
 AN82901-1

MATERIAL -TEFLON GLASS

40
THICKNESS: 0.8mm

IN OUT
30

Pout (dBm)
8.5 6.5
11.5
2 9 2 30
Pin = 22 dBm

4
21

9.5
15
2

6
f = 4 GHz
20
10 20 30
Figure 56. NE868296, 4 GHz Circuit Pin (dBm)

3.5 4 4.5
f (GHz)

MATERIAL -TEFLON GLASS 40

THICKNESS: 0.8mm

IN OUT

Pout (dBm)
30
3.5 3
20 4 5 6 8.5 5
30

5.5
21

9.5
10
2

Pin = 22 dBm
f = 5 GHz
20
10 20 30
Pin (dBm)
Figure 57. NE868296, 5 GHz Circuit 4.5 5 5.5
f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm 40

IN OUT
20
2.5
Pout (dBm)

6.5
Pin = 22 dBm
2 2 7.5 2 30
4
15

5
6

f = 6.5 GHz
4
20
10 20 30
Pin (dBm)
Figure 58. NE868296, 6 GHz Circuit
5.8 6 6.2 6.4 6.6
f (GHz)

MATERIAL -TEFLON GLASS

40
THICKNESS: 0.8mm

IN OUT
Pout (dBm)

20
3 4.5 3 2.7 3
8.7 30
4

Pin = 22 dBm
15

6.5
6.7
2

f = 7.2 GHz
20
10 20 30
Pin (dBm)
6.5 7 7.5
Figure 59. NE868296 Test Circuit (6.5 GHz and 7.5 GHz) f (GHz)
AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm 40
VDS = 9.0 V

IN OUT

Pout (dBm)
28.5 28.5 Pin = 25 dBm
2.5 2 2 1.5
3 18.0
30

f = 4.0 GHz
4.5

10.5
9.5
7.5
20
10 20 30
Pin (dBm)
3.5 4.0 4.5
Figure 60. NE868495-4 Circuit
f (GHz)

MATERIAL -TEFLON GLASS

IN OUT
THICKNESS: 0.8mm
30
3.5 2.5
6 12.7
2.5
2.2 2.5

5
21.5

3.7

7.7
2.1

8.5

2.1
Figure 61. NE868495-5 Circuit

MATERIAL -TEFLON GLASS

IN OUT THICKNESS: 0.8mm 40
18.5 VDS = 9.0 V
18.5

9.5 14
3.5
Pout (dBm)

3
2.5 2 Pin = 26 dBm

30
7.0
6.5
6

f = 6.5 GHz
20
10 20 30
Pin (dBm)
6.0 6.5 7.0

Figure 62. NE868495-6 Circuit f (GHz)

MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm 40
IN OUT

20.0 11.0
9.0 9.0 f = 7.0 GHz
Pout (dBm)

1.9 1.9 2.0

30 Pin = 26 dBm
5.2
4.7
15.0
2.1

6.7

2.1

VDS = 9.0 V
20
10 20 30
Pin (dBm)
6.5 7.0 7.5
Figure 63. NE868495-7 Circuit f (GHz)
 AN82901-1

IN
MATERIAL -TEFLON GLASS
OUT
THICKNESS: 0.8mm
20

6.2 11
2.4
2 1.5 2.6 2 2

4.5

3.5
7
2.1
15

5
3.3

2.1
Figure 64. NE868495-8 Circuit

IN OUT MATERIAL -TEFLON GLASS

THICKNESS: 0.8mm
30 15
4.5 4
5

2.1
5
21.5
2.1

4
4.3

Figure 65. NE868898-5 Circuit

MATERIAL -TEFLON GLASS

IN OUT
THICKNESS: 0.8mm
25 40
25 VDS = 9.0 V
13.5
9.8 13.5
7.8 9.0
Pout (dBm)

Pin = 29 dBm
30
5.5

f = 6.0 GHz
4.0

20
10 20 30
Pin (dBm)
5.5 6.0 6.5

f (GHz)
Figure 66. NE868898-6 Circuit
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm
IN OUT
40 VDS = 9.0 V
25 25
3.5
12 2 14.5
Pout (dBm)

P in= 29 dBm
30
3.6

8.8

f = 7.2 GHz

20
10 20 30
Pin (dBm)
6.5 7.0 7.5

Figure 67. NE868898-7 Circuit f (GHz)

AN82901-1
MATERIAL -TEFLON GLASS
THICKNESS: 0.8mm f = 8 GHz
IN OUT
35

Pout (dBm)
20
2 3
1.5 Pin = 30 dBm
30

20 dBm

3.7

2.1
2.1 25
15

4.8
VDS = 9 V
20
10 15 20 30
Pin (dBm)
7.5 8.0 8.5
f (GHz)

Figure 68. NE868898-8 Circuit

6 6

NE800898-4 NE371698-4

4 4
PHASE (deg.)

PHASE (deg.)
2 2

0 0

-2 -2
20 22 24 26 28 30 22 24 26 28 30 32

Pin (dBm) Pin (dBm)

6 6 6
NE868196
(NE868199) NE868495 NE868898
4 4 4
PHASE (deg.)

PHASE (deg.)
PHASE (deg.)

2 2 2

0 0 0

-2 -2 -2

-4 -4 -4
0 5 10 15 20 25 10 15 20 25 30 35 10 15 20 25 30 35

Pin (dBm) Pin (dBm) Pin (dBm)

Figure 69. AM-PM Conversion for the NE800, NE371 and NE868 Series
 AN82901-1

50 10 40
Pout

45 0 30
f = 7.7 GHz, ∆f = 10 MHz
VDS = 9 V
IDS = 1.0 A
40 -10 20

Pout IM3

Pout, IM3 (dBm)

35 -20 10
Pout (dBm)

IM3 (dB)
30 -30 0
IDS = 1.2A,Pin =30 dBm
IDS = 0.8A,Pin =30 dBm
IM3
25 -40 -10

NE800898-7H NE868898-6
20 -50 -20

15 -60 -30
15 20 25 30 35 10 20 30 40
Pin (dBm) Pin (dBm)

Figure 70. Third Order Intermodulation Distortions for the NE800898-7H and NE868898-6

References

[1] Masuo Fukuda, et. al., [5] L. Nevin, et. al., “L-Band GaAs FET
”Low Noise GaAs FET Ampliliers,” MW77-21. Amp.,” Microwave Journal, Apr. 1979.

[2] Charles A Liechti, et. al., MTT-22, No. 5, May 1974 [6] Eric Ulrich, “Use Negative Feedback to Slash
Wideband VSWR,” Microwaves, Oct. 1978.
[3] Herman Sfatz, et. al., ED-21, No. 9, Sept. 1974.
[7] K. Honjo, et. al., “Broadband Internal Matching of
[4] P. Bura, Electronics Letters, Vol. 10, No. 10, p. Microwave Power GaAs MES FETs.,” IE3, Trans,
181-,16th, May 1974. Mit. Jan. 1979.

[8] Y. Takayama, “A New Load-Pull Characterization

Method for Microwave Power Transistors,”
1976 MTT-S, Digest, p. 218-220, June 1976.

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© California Eastern Laboratories 01/23/2003