International Journal of Wisdom Based Computing, Vol.

1 (3), December 2011

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Design and Simulation of a Two Stage OPAMP Using DG MOSFETs for Low Power and Low Voltage Applications
Santosh Kumar Gupta
Member, IEEE National Institute of Technology, Silchar Silchar, India 788 010 e-mail: santoshty@gmail.com AbstractDouble Gate MOSFET (DGFET) is one of the promising technologies for sub-50nm transistor design. To accommodate future technology nodes transistor dimensions have to be reduced which leads to several disadvantages in transistor function. By using double-gate design many of these problems can be resolved to give efficient circuit performance. As we go for further scaling down, use of double-gate transistors in analog circuit design gives significant improvements over conventional singlegate CMOS design. These are observed by comparing the designs of a classical two-stage op-amp with single-gate and double-gate transistors using HSPICE simulation.
Keywords - double-gate; analog; OPAMP; HSPICE
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Gaurab Gunjan Pathak, Debajit Das, Chandan Sarma

National Institute of Technology, Silchar Silchar, India 788 010 e-mail: 1gaurabgunjan@gmail.com

plane is electrically connected to the transistor gate, then the ground plane acts as a second gate. The double-gate structure is comprised of a conducting channel usually undoped surrounded by gate electrodes on either side. The most common mode of operation is to switch both gates simultaneously. Another mode is to switch only one gate and apply bias to the other (back gate ). DGFET is of the following types [4]a. Planar (Gates and channel are horizontal), b. Vertical (Conduction direction is vertical), c. FinFET (Channel is vertical, conduction is parallel to wafer surface). A general DGFET structure is shown in Fig.1[3]-

I.

INTRODUCTION

In 1965 Gordon Moore predicted that the number of transistors per chip would quadruple every three years [2]. In order to keep up with this, transistor dimensions have been reduced by half every three years. The submicron level was overcome in 1980s. SOI devices came into picture in 1990s[2]. They give improved circuit speed and power consumption. However as transistor dimensions are shrunk, the close proximity between source and drain reduces the ability of the gate electrode to control the potential distribution and flow of current in the channel. This increases the electrostatic effect of the source, drain electrodes on the channel. As a result Short Channel Effects take prominence. To reduce SCEs we need to increase gate to channel coupling with respect to source/drain to channel coupling. For this planar CMOS requires high channel doping. But this leads to increased band-to-band tunneling, gate induced drain leakage (GIDL) and large variability due to channel doping level fluctuations. So, conventional bulk MOSFET cannot be scaled down below 20nm [2]. These limitations can be overcome by the double-gate FETs. With one more gate the gate to channel coupling is doubled resulting in good suppression of SCEs [1, 2]. II. BASIC DESIGN AND TYPES OF DGFET The main idea of a double-gate MOSFET is to have a Si channel of very small width and to control the Si channel by applying gate contacts to both sides of the channel. The double gate concept can be garnered from the FDSOI structure [2]. If the buried oxide thickness is reduced to that of the gate dielectrics and if the ground

Figure 1. General DGFET structure.

III.

ADVANTAGES OF DGFET

The double-gate concept considerably increases the efficiency of transistors as they are scaled down as compared to planar CMOS. The gate to channel coupling is doubled and hence SCEs are easily suppressed. Very lowly doped or even undoped channel can be used in DGFET. This gives good carrier mobility in reduced dimensions and hence better intrinsic switching time. The leakage currents or off-state currents are reduced. The current driving capability of DGFET is twice that of planar CMOS and hence DGFET can be operated at much lower input and threshold voltages. Hence power consumption is less in DGFET. Due to the presence of two gates no part of the channel is far away from the gate. The voltage applied on the gate terminals control the electric field, determining the amount of current flow through the channel. This gives a ideal sub-threshold slope for suitable sub-threshold operation. Hence DGFET can be operated at much lower voltages [1, 2].

International Journal of Wisdom Based Computing, Vol. 1 (3), December 2011 IV. DGFET IN ANALOG CIRCUITS

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A classical two stage op-amp with compensator capacitor CC is shown in Fig.2. It consists of a cascade of VI and IV stages [5]. The first stage consists of a differential amplifier converting the differential input voltages to differential currents. These differential currents are applied to a current-mirror load recovering the differential voltage. This of course is nothing but the differential voltage amplifier. The second stage consists of a common-source MOSFET converting the second stage input voltage to current. This transistor is loaded by a current-sink load which converts the current to voltage at the output. The second stage is also nothing more than the current-sink inverter. This two stage op-amp is so widely used that it is called classical two stage op-amp [5]. The capacitor CC is the Miller compensation capacitor used to increase the phase margin of the system. Some important design parameters of the two stage op-amp are discussed below in relation to the use of double gate technology. 1) Gain:- The open loop gain can be expressed as the product of the gain of the two stages.

Figure 2. Classical two stage op-amp

2 gm2 gm6 AV = I 5 I 6 ( 2 + 3 ) ( 6 + 7 )

(1)

Thus gain depends on trans-conductance gm and the channel length modulation parameter . The effective mobility of DGFET is much higher than that of the bulk transistors because of the undoped channel resulting in an enhanced gm [6]. The channel length modulation parameter is considerably minimized in DGFET because of the better control of short channel effects in double-gate structure. Thus gain can be increased by using DGFET. 2) Power dissipation:-It is given by (2) Pdiss = ( I 5 + I 6 ) (VDD + VSS ) The DGFET op-amp can be operated at low VDD maintaining high gain and good slew rate. Thus power dissipation is very much reduced. 3) Slew rate:- The rate of change in the output voltage caused by a step input is called slew rate, SR. It depends on the compensator capacitor Cc and I5 [7] given by the relationI (3) SR = 5 CC Now trans-conductance gm is higher in double-gate compared to single-gate MOSFET resulting in good phase margin for the uncompensated DGFET op-amp. So, a smaller value of CC is required for DGFET op-amp. Also, the drive current of DGFET is twice than that of conventional bulk MOSET. So, I5 is more for DGFET structure. Thus SR is more. 4) Unity gain bandwidth:- It specifies the frequency at which the open-loop voltage amplification is 1. The unity gain bandwidth (f) is given by
f = g m1 CC

As discussed gm is higher and CC is lower for DGFET op-amp. Hence unity gain bandwidth is higher resulting in enhanced gain-bandwidth product. 5) Settling Time:-The time in which the op-amps output would settle to within a particular value of its final value is called settling time (ts). It primarily depends on bandwidth and slew rate [8], both of which are high in DGFET op-amp. Moreover DGFET has faster switching time than single-gate MOSFET. So, ts is higher for DGFET op-amp. V. SIMULATION AND RESULTS The two stage op-amp circuit is first simulated for single-gate design. We have used in-built HSPICE model level-57 for the design. The standard transistor dimensions are Width (W)=1m, Length (L)=1m. We tabulate the results for VDD= VSS= 1V, CC = 3pF, CL= 10pF in Tables I and II
TABLE I. Gain, unit frequency and settling time of single gate op-amp VDD (V) 1 Gain Gain (DB) Unit Frequency (MHz) 1.1553 Settling Time (s) 1.44

5.0667

14.095

TABLE II. Power dissipated and slew rate for single gate op-amp VDD (V) 1 Power dissipated (watts) 180.60 SR Pos. (V/s) 0.00891 SR Neg. (V/s) 0.0293

(4)

Now the same op-amp circuit is implemented with double-gate concept. For simulation we have used the PTM 32nm FinFET model. Here tied gates are used, that is, both the gates are switched simultaneously. The transistor dimensions are Width (W)=80 nm, Length=32 nm.

International Journal of Wisdom Based Computing, Vol. 1 (3), December 2011 We try to achieve an optimum value of input VDD for good op-amp characteristics. The HSPICE simulation results are tabulated in Tables III and IV. From the above table we observe that 0.5 V is the optimum operating voltage for DGFET op-amp. At VDD= 0.5V, we have maximum gain and unit frequency. Also the power dissipation and settling time are less than that of single-gate op-amp at VDD= 1V. Moreover, the slew rate is much higher for DGFET structure at VDD= 0.5V. A comparison of gain and unit frequency for doublegate op-amp at VDD= 0.5V and single-gate op-amp at VDD= 1V is shown in Fig. 3. A comparison of power dissipated, slew rate and settling time for double-gate op-amp at VDD= 0.5V and single-gate op-amp at VDD= 1V is shown in Fig. 4.
TABLE III. VDD (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 TABLE IV. VDD (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Gain, unit frequency and settling time of double gate op-amp Gain Gain (db) 22.028 22.344 22.594 22.732 22.660 22.232 21.205 19.223 Unit frequency (MHz) 17.825 16.843 15.629 14.264 12.409 10.122 7.2334 3.6404 Settling time(s) 0.68 0.66 0.64 0.62 0.58 0.44 0.32 0.28

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From the discussion and results we clearly observe that use of DGFET considerably increases the performance of two stage op-amp. Comparing the DGFET op-amp at VDD= 0.5V with single-gate op-amp at VDD= 1V, we see that DGFET OPAMP gives greater voltage amplification

12.629 13.098 13.481 13.696 13.583 12.931 11.488 9.1443

Power dissipated and slew rate for double gate op-amp Power dissipated (watts) 817.35 644.11 491.09 358.26 246.19 154.25 82.25 30.02 SR Pos. (V/s) 0.3023 0.3395 0.4028 0.6736 0.3826 0.3467 0.4475 0.5983 SR Neg. (V/s) 0.4304 0.4478 0.5411 0.8434 0.6422 0.6399 0.8436 1.2904

Figure 4. Single gate op-amp v/s double gate op- amp for power dissipated, slew rate and settling time

consuming less power. Other parameters like slew rate, unity gain bandwidth and settling time for DGFET design are much better than single-gate design. Thus, we can conclude that DGFET two stage OPAMP can be implemented in low-voltage and low-power applications. REFERENCES
[1] Amara Amara, Oliver Rozeau, Editors, Planar Double-Gate Transistor: From Technology to Circuit, Springer, 2009, pp. 120. Jean-Pierre Colinge, Editor, FinFET and Other Multi-Gate Transistors, Springer, 2008, pp 1-13. Kavita Ramasamy, Cristina Crespo, Double-Gate MOSFETs, Portland State University, ECE 515- Winter 2003. Mike Duffy, Eric Dattoli, Alain Espinosa, Nanoscale Silicon Technology, http://www.guo.ece.ufl.edu/project4.ppt Phillip E. Allen, Douglas R. Hollberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press,2002, pp. 249-250. M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, and L. Mathew, Carrier mobility transport in undoped-utb dg nfets, Electron Devices, IEEE Transactions on, vol. 54, no. 5, pp. 11251131, May 2007.

[2] [3] [4] [5]

Figure 3.Single gate op-amp v/s double gate op-amp for gain and unit frequency VI. CONCLUSION

[6]

International Journal of Wisdom Based Computing, Vol. 1 (3), December 2011

[7] Till Kuendiger, Joseph Schrey, Iman Taha, Yi Lin, Tao Di, Li Liang, Song-Tao Hunag, Yue Huang, Cadence Op-amp Schematic Design Tutorial for TSMC CMOSP35. [8] M. Taherzadeh-Sani, R.Lotfi, H. Zare-Hoseini, 0.Shoaei, A high slew-rate low-voltage low-power operational amplifier using a new current injection circuit., December 2001. [9] Anish S. Kulkarni, Study of Tunable Analog Circuits Using Double Gate Metal Oxide Semiconductor Field Effect Transistors, Russ College of Engineering and Technology, M. Sc. Thesis, March 2009, pp. 25-30. [10] Chetan Nagendra, Robert Michael Owens, and Mary Jane Irwin, Power-Delay Characteristics of CMOS Adders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2,no. 3, p. 377, September 1994. [11] Srinivasa R. Vemuru, Norman Scheinberg, Short-Circuit Power Dissipation Estimation for CMOS Logic Gates, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 41, no. 11, p.762, November 1994. [12] Predictive Technology Models (PTM) available at http://ptm.asu.edu/ Authors

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Tech. degree in electrical engineering from Indian Institute of Technology, Mumbai, India in 2002. From 2002 to 2005, he worked as lecturer in the department of Electronics and Communication Engineering of Kumaon Engineering College, Dwarahat, Uttarakhand, India. Later he joined the

department of Electronics and Communication Engineering of National Institute of Technology (NIT), Silchar, India as lecturer in 2005 and is currently there at the post of Assistant Professor. His research area includes modeling and simulation of novel device structures on SOI MOSFETs. He is a member of IEEE Electron Device and Solid State Circuits. Gaurab Gunjan Pathak, Debajit Das and Chandan Sarma are B. Tech. students of the Electronics & Communication Engineering Department, National Institute of Technology, Silchar, Assam, India.

Santosh Kumar Gupta was born (DOB-1979) in Balepar, Sant Kabeer Nagar District, Uttar Pradesh, India. He received the M.