A REVIEW: MODELLING OF CARBON NANOTUBE FIELD
EFFECT TRANSISTORS BASED DIGITAL LOGIC DEVICES
Priyanka Tyagi *
Aakansha Garg **
Abstract
In electronics industry the size of device is a matter
of concern. With the small size there is another
issue is high performance and low power
dissipation. For these purpose improve the
performance of digital circuit CNTFET are explored.
CNTFET are the advance and best components for
future electronics world. This paper present review
of CNTFET and CNTFET based devices. The structure
and working of CNTFET, CNTFET Modelled devices
and advantage of CNTFET or MOSFET have been
discussed.
CNTFET digital logic devices small size low power
consumption has been presented in this paper.
Keywords: CNTFET, SPICE, CPL, TG,DOMINO.
* ABES Institute of Technology, Ghaziabad.
** ABES Institute of Technology, Ghaziabad.
Introduction
In last few years silicon based technology has
experienced phenomenal growth. Due to scaling
property, MOS transistors become the most
successful component in semiconductor industry.
From this property, designers can scale down the
dimensions, which results improved
performance. Moreover, there are certain
limitations with MOSFET size that’s why the
silicon industry has searched out the new
material to integrate the devices based on the
current silicon based technology. The electrical
properties of the CNTFETs are superior to the
MOSFETs. For this reason they can be the best
option to replace the MOSFETs.
The size of transistor and electronic circuits is
reduced gradually from their invention and the
power dissipation is also reduced. This feature
of size reduction is represent by well known
‘Moore’s law’. This law represents the evolution
in transistor industry with growing years.
However, as the feature size becomes smaller,
scaling of the silicon MOSFET becomes
increasingly harder. This increasing challenge is
often attributed to quantum mechanical
tunnelling of carriers through the thin gate oxide,
quantum mechanical tunnelling of carriers from
source to drain and from drain to body, control
of the density and location of dopant atoms in
the channel and source/drain region to provide
high on/off current ratio.
43
This limitation can be resolved with many other can be rolled into a tube, as shown below.
solutions. There can be two types of solutions. The terms “armchair” and “zig-zag” refer to the
The first can modify the existing material arrangement of hexagons around the
properties or structures. Other solution is using circumference. The third class of tube, which in
the new material and new structure which will practice is the most common, is known as chiral,
replace the old one completely. From the second meaning that it can exist in two mirror-related
solution, the silicon material is replaced by the forms. An example of a chiral nanotube is as
carbon and the transistor or MOSFET structures shown in fig. below.
are replaced by the CNTFETs. These new
technologies and devices require the creation of
accurate compact models, suited to the circuit
design and easily translatable into a hardware
description language (HDL) such as VHDL-
AMS.(Very high speed integrated circuit hardware
description language-Analog mixed signal)

In this paper, first we brief about CNT structure

and properties of CNT. Then we will discuss
CNTFET and type of CNTFET. In second part , We
discuss about digital electronics application and
digital logic for CNTFET based devices.
Multi-Walled CNT’s:
CNT’s
Multi-walled nanotubes (MWNT) consist of
CNTs are allotropes of carbon. They are tubular
multiple rolled in on themselves to form a tube
in shape, made of graphite. They are nanometres
shape. There are two models which can be used
in diameter and several millimetres in length and
to describe the structures of multi-walled
have a very broad range of electronic, thermal,
nanotubes. In the Russian Doll model, sheets of
and structural properties. These properties vary
graphite are arranged in concentric cylinders. In
with kind of nanotubes defined by its diameter,
the Parchment model, a single sheet of graphite
length, chirality or twist and wall nature. single-
is rolled in around itself, resembling a scroll of
walled nanotubes (SWNT) have a diameter close
parchment or a rolled up newspaper.
to 1nm, with a tube length that can be many
thousands of times longer. SWNTs are very
The resistivity of the SWNT ropes was in the order
important carbon nanotube because they exhibit
of 10–4 ohm-cm at 27°C. This means that SWNT
important electric properties that are not shared
ropes are the most conductive carbon fibers
by the multi-walled carbon nanotubes (MWNT)
known. CNTs are an example of true
variants.
nanotechnology: they are only about a nanometer
in diameter, but are molecules that can be
SWNTs can be excellent conductors and the most
manipulated chemically and physically in very
building block of SWNT system is the electric
useful ways. They open an incredible range of
wires. One useful application of SWNTs is in the
applications in materials science, electronics,
development of the first intramolecular field
chemical processing, energy management, and
effect transistors (FETs). The bonding in carbon
many other fields.
nanotubes is sp², with each atom joined to three
neighbours, as in graphite. The tubes can therefore
be considered as rolled-up graphene sheets
CNTFETs
(graphene is an individual graphite layer). There SWCNT have ability to carry high current and
are three distinct ways in which a graphene sheet due to current carrying capability they are used

44
to fabricate CNTFET. CNTFET Types are based of
two parameters Geometry and Electrode
dependent CNTFET.
Geometry Dependent CNTFET:
a. Back Gate CNTFET: Tans et.al [1] proposed
first back gate CNTFET in his paper. There
SWCNT used as the channel and metal
electrodes are used as source and drain.
The heavily doped Silicon wafer act as back
gate. These CNTFET used as P-Type FET. It
has a limitation high parasitic resistance
and low drive current.
b. Top Gate CNTFET : Wind et.al [2] describe
first top gate of CNTFET in 2003. A top gated
CNTFET with Ti source , drain and gate
electrodes. A SIO2 film of 15nm was used
as gate oxide placed over the CNT.
Electrode Dependent CNTFET :
a. Schottky Barrier CNTFET : In SB CNTFET
intrinsic CNT act as a channel region. This
connected to metal source and drain and
form schottky barrier. In this type of fat the
alignment of schottky barrier and gate
electrode is a matter of concern.
b. Partial Gated CNTFET : PG CNTFET is the
type of depletion mode CNTFET. In this FET
the nanotube is uniformly doped with omic
contacts at their end. PG CNTFET can be N-
Type and P-Type according to their doping.
c. Doped-Source and Drain CNTFET: These
types of FET are composed of three reason
below the gate it is an Intrinsic nature and
two ungated reason are doped with either
N-Type and P-Type. Depending upon the
doping profile these FET can be classified
as Conventional CNTFET and tunneling
CNTFET.
Fig. 1 Different types of CNTFETs: (a) Schottky-barrier (SB)
CNTFET with ambipolar behaviour, and (b) MOSFET-like
CNTFET with classic behaviour.
Digital CNTFET Devices
Ian O’ Connor at.el [3] 2007, Present multi
functional dynamic reconfigurable login Gates.
The function likes AND, OR, NOT, NAND, NOR and
XOR are designed in a single circuit with the help
of seven CNTFET. This paper also present the
layout of CNT-DR8F –cell there are seven input
and two output. It is use to Data input A and B
with 0 and 1 login values. These inputs are used
in different Boolean expression, In this paper also
discuss about the full adder application and ALU.
The best thing of the paper is the calculations
obtain from zone folding methods are pre
computed with the help of flow diagram.
Murotiya at.el [4] 2013, described dual Edge
triggered DFF and SISO register and LFSR. All these
application are implemented using CNTFET. In
this paper comparative analysis of CMOS
technologies has given on the parameter of size
clock frequency output load and supply voltage.
In this paper propagation delay, power
dissipation and transition time are find out less
then CMOS DFF.
Keshavarzin at.el 2013, In this paper the study
of full adder on the basis of ternary login is given
there are 3 login values 0,1,2 . In which 0= GND ,
1=1/2 VDD , 2=VDD. The full adder design is
proposed based on CNTFET with low delay and
power consumption. This design has two parts
sum and carry. The two ternary values and the
carry of the last stage are added and the sum and
carry value are produced.
S.Bhat at.el 2012 , Present SRM cell with different
modelling like 4TSRM , 5TSRM, 6TSRM, 7TSRM,
8TSRM , 9TSRM , 10TSRM with there specification
about their size and number of tubes. These circuit
are design using CNTFET 32nm technology.
Murotiya at.el 2015, This paper present 4 input
ternary XOR function with low power dissipation
and low delay.
Koushik at.el 2014 , In this paper 10CNTFET full
adder circuit with ultra low poper specification
is defined.
45
Shreg et.al 2014 , this paper compare the
parameter like power dissipation and circuit
delay with the convection CMOS of different logic
gates like NOT , NAND , NOR and XOR.
Farhan et.al 2014, In this paper the spice model
of CNTFET and its characteristic is defined. The
spice analyze high frequency properties
including quantum capacitance and ballistic
transport.
Farhan et.al 2014, proposed the high voltage
gain CNTFET invertors. For voltage gain
calculation he use small signal model of CNTFET.
Sankar et.al 2014, present all logic style with
CNTFET like pass transistor logic (PTL)
Transmission gate logic (TG) complementary pass
transistor login (CPL) and CNTFET domino logic.
Kunal Sharma 2013, Present mode 16 counter
using Verilog –A model of CNTFET which is based
on Stanford compact model.
Conclusion
In this paper we conclude that CNTFET are more
promising component in electronics industry. In
today’s world portability is the matter of concern.
CNTFET provide the less size as compare to
conventional CMOS devices which make
applications more portable. Second demand of
electronic world is less power consumption by
using the CNT FET this can be achieved. In this
paper we reviewed much digital logic with less
size and low power consumption. Another
requirement of electronic industry is switching
time the propagation delay of all digital logic
devices are less as we do the comparative study.
All these features make CNTFET most promising
character of future electronic world. In this paper
we review logic gates, digital memories like RAM,
all application like flip flop, counters, registers,
adders with low power dissipation and
propagation delay and less size. The conclusion
is that CNTFET improve the performance of
MOSFET device.
46
References
1. Tans S. J , Alwin R.M Verschueren and Dekker
C. Room-temperature transistor based on
a single carbon nanotube. Nature Vol.393,
PP.49-52, 1998
2. Wind S. J ., Appenzeller J., Avouris P. Lateral
scaling in carbon nanotube field effect
transistor . Physical Review letter . Vol 91,
No. 5, pp .058301, 2003
3. Ian O’ Connor, , lallement C, Zimmer T :
CNTFET Modelling and reconfigurable
Logic-Circuit Design . IEEE Trans On Circuit
and system, 54 (11) 2007
4. Murotiya Sl and Gupta A : performance
evaluation of CNTFET based dynamic dual
edge triggered registor . ICAES 2013
5. kashavarzin T , Sarikhani R: A novel CNTFET
based ternary Full adder Circuit signal
process 33:665-679 2014
6. Bhat N.S : design and modelling of different
SRM based on CNTFET 32nm technology,
VLSICS Vol 3 No.1 2012
7. Murotiya Sl and Gupta A Pandit A: CNTFET
based low power design for input ternary
XOR function IEEE Trans ICCT 2014
8. kumar K Sahithai C , Sahoo R , Sahoo S.K :
Ultra low power full adder circuit using
CNTFET proc. of IEEE 2014
9. Shreya S , Chnadela R : performance
analysis of CNTFET based digital login
circuit proc. of IEEE 2014
10. farhan S , Alam A.Z , Khan S: Spice model
design for carbon nanotube filed effect
transistor proc. of IEEE –ICSE2014
11. farhan S , Alam A.Z , Khan S: CNTFET Invertor:
A high Voltage gain login gate proc. of IEEE
–ICSIMA 2014 25-27
12. Shankar P.A.G Udhykumar K : MOSFET like
CNTFET based logic gate library for low
power application a comparative studies
Journal of semiconductor Vol 35 No.7 2014
13. Sharma K K , Monica P.R : Implementation
of Mode 6 counter using verilog_A Model
of CNTFET IJRECT Vol 1 32-36 2013
14. NANOHUB online simulations and more,
CNT bands. [Online]. Available: http://
www.nanohub.org [April 2006].
15. Pr´egaldiny F., Krummenacher F., Di-agne B.,
Pˆecheux F., Sallese J-M, and Lallement C.:
Explicit modelling of the double-gate
MOSFET with VHDL-AMS.
16. Int. Journ. of Numerical Modelling: Elec.
Networks, Devices and Fields, 19(3):239–
256, 2006.
17. Pr´egaldiny F., Krummenacher F., Sallese J-
M., Diagne B., and Lallement. C.: An explicit
quasi-static charge-based compact model
for symmetric DG MOSFET. In NSTI-
Nanotech 2006, WCM, volume 3, pages
686–691, 2006. ISBN 0-9767985-8-1..
18. Pˆecheux F., Lallemen C. t, and Va-choux A.:
VHDL-AMS and Verilog-AMS-static charge-
based compact model for symmetric DG
MOSFET. In NSTI-Nanotech 2006, WCM,
volume 3,pages 686–691, 2006. ISBN 0-
9767985-8-1.
19. Pˆecheux F., LallemenC. t, and Va-choux A.:
VHDL-AMS and Verilog-AMS as alternative
hardware description languages for e?cient
modelling of multi-discipline systems. IEEE
Trans. Computer-Aided Design, 24(2):204–
224, 2005.
20. Raychowdhury and Roy K..: Carbon
nanotube-based voltage-mode multiple-
valued logic design. IEEE Trans. Nano-
techno., 4(2):168–179, 2005.
21. Sordan R., Balasubramanian K., Burghard
M., and Kern K..: Exclusive-OR gate with a
single carbon nanotube. App. Phys. Letters,
88, 2006. 053119.
22. Taur Y., Liang X., Wang W. and Lu H.: A
continuous, analytic drain-current model
for DG MOSFETs. IEEE Electron Device Lett,
25(2):107–109, 2004.
23. 1076.1-1999 IEEE Standard VHDL Analog
and Mixed-Signal Extensions Language
Reference Manual, IEEE press edition, 1999.
ISBN 0-7381-1640-8.
24. Mojtaba Jamalizadeh, FazelSharifi,
Mohammad Hossein Moaiyeri, Keivan Navi
and Omid Hashemipour, Five new MVL
current mode differential absolute value
circuits based on carbon nano-tube field
effect transistors (CNTFETs),Nano-Micro
letters, Vol. 2, No. 4,227-234 , 2010.
25. Mariya Lyubomirova Spasova, George
Vasilev Angelov and Marin Hristov Hristov,
Simulation of 1T DRAM Memory Cell with
Verilog-A Model of CNTFET in Cadence,
ANNUAL JOURNAL OF ELECTRONICS, 2012,
ISSN 1314-0078.
26. T. Dang, L. Anghel, R. Leveugle, CNTFET Basics
and Simulation, IEEE Trans. Elec.dev., 2006.
27. V. Saravanan, V. Kannan, Design of Cascade
Counter using Carbon Nanotube Field Effect
Transistor Technology, European Journal of
Scientific Research ISSN 1450-216X Vol. 91
No 1 November, 2012, pp.58-67.
28. Stanford University CNFET model Website,
Stanford University, Stanford, CA,http://
nano.stanford.edu/model.php?id=23 (10/
22/11).
29. S. Farhana, and A. H. M. Alam.
"Environmental Friendly Device: Modeling
of Carbon Nanotube with Optimum
Chirality." Australian Journal of Basic &
Applied Sciences 7, no. 8 (2013)
30. S. Farhana, A. H. M. Zahirul Alam, Sheroz
Khan, and S. M. A. Motakabber. "Modeling
of small band-gap CNT for designing of
faster switching CNTFET." In Business
Engineering and Industrial Applications
Colloquium (BEIAC), 2013 IEEE, pp. 589-592.
IEEE, 2013.
31. S. Farhana, A. H. M. Alam, and Sheroz Khan.
"High frequency small signal modeling of
CNTFET." IEEE Regional Symposium on
Micro and Nanoelectronics (RSM), 2013
(2013): 364-367.
32. S. Farhana, and AHM Zahirul Alam.
"Modeling of a Carbon Nanotube Sensing
Device." Middle-East Journal of Scientific
Research 17, no. 10 (2013): 1475-1478.
33. K. Jabeur, N. Yakymets, I.O’Connor and S.
LeBeux, “Ambipolar doublegate FET binary-
decision diagram (Am-BDD) for
reconfigurable logic cells”, Proc. of 2011
IEEE/ACM International Symposium on
Nanoscale Architectures (NANOARCH’11),
pp.162-168, 2011.6.
34. F. Prégaldiny, J.-B. Kammerer, and C.
Lallement, “Compact modelling and
47
 applications of CNTFETS for analog and
digital circuit design,” in Proc. IEEE ICECS,
Nice, France, Dec. 10–13, 2006, pp. 1030–
1033.
35. A. Javey et al., “High-K dielectrics for
advanced carbon nanotube transistors and
logic gates,” Nature Mater., vol. 1, pp. 241–
246, 2002
36. Vaddi R, Dasgupta S, Agarwal R P. Device
and circuit co-design robustness studies
in the subthreshold logic for ultralow-
power applications for 32 nm CMOS. IEEE
Trans Electron Devices,2010, 57(3): 654
37. Duan Y, Juhala J L. Solution-based
fabrication of p-channel and n-channel
field-effect transistors using random and
aligned carbon nanotube networks.
Microelectron Eng, 2013, 103: 18
48
38. Bok K Y, Lombardi F. Novel design
methodology to optimize the speed and
power of the CNTFET circuits. IEEE
International J. Semicond. 2014, 35(7) P. A.
Gowri Sankar et al.Midwest Symposium On
Circuits and Systems, Mexico, 2009:
39. A New Low Power 9T SRAM Cell based on
CNTFET at 32nm Technology Node Rajendra
Prasad S1, Dr. B K Madhavi2, Dr. K Lal
Kishore3 Rajendra Prasad S et al, / (IJCSIT)
International Journal of Computer Science
and Information Technologies, Vol. 2 (6) ,
2011, 2761-2764