2012 - International Conference on Emerging Trends in Science, Engineering and Technology

317

Design and Analysis of Carry Bypass Adder

Using CNTFET

Sree Harsha Parimi S.Mukilan M.Govindaraja Chowdary T.Ravi

M. Tech VLSI Design
Sathyabama University
Chennai, Tamil Nadu ,
harsha.parimi@gmail.com
M. Tech VLSI Design
Sathyabama University
Chennai, Tamil Nadu
er.mukilansaka@gmail.comcr
M. Tech VLSI Design
Sathyabama University
Chennai, Tamil Nadu
govindarajachowdary89@gmail.
com
M. Tech VLSI Design
Sathyabama University
Chennai, Tamil Nadu
ravi_vlsi123@yahoo.co.in

Abstract— This paper enumerates the efficient design and
analysis of a Carry Bypass Adder using Full Adder cell. The Full
Adder is designed using Stanford University CNTFET model and
proposed 10nm CNTFET model. There are many issues facing
while integrating more number of transistors like short channel
effect, power dissipation, scaling of the transistors. To overcome
these problems, the carbon nano tubes have promising
applications in the field of electronics. The carbon nanotube is
emerging as a viable replacement to the MOSFET. The transient
and power analyses are obtained with operating voltage at 0.9V.
Simulations and analyses are carried out for the Full Adder Cell
and Carry Bypass Adder. The simulation results are presented
and the analyses are compared with circuits designed using 32nm
MOSFET. The comparison of results indicated that the proposed
10nm CNTFET based design is more efficient in power savings
and speed.
Index Terms— CNT, CNTFET, Full adder cell, carry bypass
adder, Design constraints and Circuit simulation
I.INTRODUCTION
Moore's law describes a long-term trend in the history of
computing hardware. The quantity of transistors that can be
placed inexpensively on an integrated circuit has doubled
approximately every two years. The trend has continued for
more than half a century until 2007. Recent advancements
made this law to continue even after this period. The scaling
down of devices has been the driving force in technological
advances since late 20th century [2]. Aggressive scaling of
CMOS circuits has led to higher and higher integration density,
more functional complexity and better performance. However
further scaling down has faced serious limits related to
fabrication technology and device performances as the critical
dimension shrunk down to sub-22 nm range. Within the
bounds of MOS technology, the possible circuit realizations
may be based on pMOS, nMOS, CMOS and even BiCMOS
devices. As the device dimensions, such as the channel lengths
approach to the sub-10 nm regime, direct tunnelling between
source (S) and drain (D), and severe short channel effects
present a fundamental challenge in continued scaling of Silicon
devices [2].
Tremendous research efforts have recently been undertaken
by various academic and industrial research groups for
integrating new semiconductors, as the channel material to
enable (i) more efficient transport of carriers that are having
higher mobility and (ii) improved electrostatics at nanoscale.
Towards this goal, molecular devices are becoming hopeful
alternatives to the existing silicon technology. Carbon Nano
Tube (CNT) technology is at the front of these technologies
due to the unique mechanical and electronic properties. Semi-
conducting carbon nanotube can be used as the channel in
Carbon Nanotube Field Effect Transistor (CNTFET) [1].
CNTFETs are novel devices that are expected to sustain
the transistor scalability while increasing its performance. One
of the major differences between CNTFETs and MOSFETs is
that the channel of the former devices is formed by CNTs
instead of silicon, which enables a higher drive current density,
due to the larger current carrier mobility in CNTs compared to
bulk silicon. The main drawbacks of the MOSFET is that the
sensitivity of a MOSFET’s gate to static and high-voltage
spikes makes it vulnerable to damage resulting from parasitic
oscillation. This undesired self-oscillation could result in
excessive gate-to-source voltage that permanently damages the
MOSFET’s gate insulation. Another MOSFET limitation is
gate capacitance. This parameter limits the frequency at which
a MOSFET can operate effectively. CNTFET overcomes these
limitations to produce better performance than MOSFET [2].
II.BASICS OF CARBON NANOTUBES
The Carbon nanotubes were discovered by S. Ijiima in
1991 while performing some experiments on molecular
structure composed of carbonium. They can be considered as
the result of folding graphite layers into carbon cylinders and
may be composed of a single shell–single wall nanotubes
(SWNTs), or of several shells—multi-wall nanotubes
(MWNTs) as shown in fig.1. Depending on the folding angle
and the diameter, nanotubes can be metallic or semiconducting.
Based on the chiral vector, the circular vector that is
perpendicular to the axis of the tube, CNTs are classified into
Arm Chair, Zigzag & Chiral as shown in fig.2. SWNTs are

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 2012 - International Conference on Emerging Trends in Science, Engineering and Technology
typically one atom in wall thickness, few tens of atoms in
circumference and many microns in length [5].
Fig. 1. Single walled and multi walled nanotubes
Fig. 2. Arm-chair, zigzag and chiral forms of nano tubes
They have attracted much of an attention recently because
of their remarkable electronic and mechanical properties.
III.CARBON NANO TUBE FIELD EFFECT TRANSISTOR
A CNFET is formed by a carbon nanotube connecting two
metal electrodes on either side that form source and drain
contacts, with gate electrode separated from the nanotube by a
thin oxide film. Even though different types of gate structures
are in use, a coaxially gated CNTFET is considered for
symmetry and optimal results. Single-walled carbon nanotube
(SWCNT) transistors have attracted intensive attentions for
their potential as a novel generation of basic cells in IC design
[3]. Fig. 3 shows ballistic CNTFET structure [2].
Fig. 3. Ballistic Carbon Nano Tube Field Effect Transistor
Theoretical and experimental research has demonstrated the
unique electrical features of carbon nanotube transistors,
including high transconductance and high ON/OFF current
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318
ratio. The valence and conduction bands of the carbon
nanotube are symmetric, which allows complementary
structures in applications. The nearly ballistic transport at low
bias implies the possibility of deriving carbon nanotube
transistors [6].
CNTFET could be more of an interest due to its similarities
with MOSFET in terms of inherent electronic properties. Due
to these similarities, previously designed CMOS architectures
and basic CMOS-based platforms can still be used without any
major modifications.
A. Ballistic CNTFET Model
Stanford University 32nCNTFET model is the Ballistic
CNTFET model. The resistance of short one-dimensional
conductors is independent of their composition or the length of
the conductor, and only a function of the number of available
conduction channels (i.e., one-dimensional sub bands) and the
transmission at the contacts. For a single conduction channel
with 100% transparent contacts, the quantum resistance is a
universal constant given by [10]
RQ = 26 kΩ
This behavior is often called ballistic conduction, since
electrons travel between two terminals without any scattering
event. Note that the resistance of a ballistic conductor is not
zero, even though there is no scattering in the conduction
channel and no backscattering for electrons exiting the
conductor. The quantum resistance (or contact resistance, as it
is sometimes called) originates from the mismatch between the
large number of modes in the macroscopic contacts that the
current is distributed over, and the few electronic modes (one-
dimensional sub bands) available in the one-dimensional
conductor.
Fig. 4. Illustration of a ballistic transport in a CNTFET
In fig.4, the carriers are injected into the CNT from contact
1 with energies up to μ1 and from contact 2 with energies up to
μ2. There is no scattering in the CNT, and carriers that are
injected at certain energy E traverse the tube without any
energy loss. The electrochemical potential equilibrates inside
the macroscopic leads. The net current is carried by carriers
with energy between μ1 and μ2 that travel from contact 1 to
contact 2 [10].
Short channel MOSFET like CNFETs are of particular
interest because they are shown to provide near ballistic
current, thereby indicating maximum performance
The peripheral length of the nanotube is given by[6]
L = |Ch| = a (1)
 2012 - International Conference on Emerging Trends in Science, Engineering and Technology
where, Ch is the chiral vector and a is the lattice constant.
The tube diameter, dt, is given by [1, 2, 3]
dt = = (2)
For a given set of chiral vectors, and tube diameter the
parameters of the CNTFET are designed [6].
The major parameters of the Stanford University CNTFET
model are the channel length is 32nm, Diameter is 0.144nm,
LSS and LDD is 32nm, TOX is 4nm, K is 16, Pitch is 20nm
and Chiral vector is (19,0).
B. Proposed Cntfet Model
The proposed model major parameters are like the channel
length is further reduced to 10nm. The chiral vector is taken as
(17, 0). The diameter of the tube is thus obtained at 1.33nm. as
the channel length is taken as 10nm, the source side and drain
side extensions (Lss and LDD) are also taken as 10nm. The oxide
thickness tOX should be 2 nm for the given channel length. The
dielectric constant is K = 15 for graphite and the pitch is taken
as 4nm [3].
IV.FULL ADDER CELL
Full adders form the basic building blocks of all digital
VLSI circuits. Addition is used in many other arithmetic
operations such as subtraction and multiplication. Adders are
used not only in the arithmetic logic units (ALUs), but also in
other parts of the processor, where they are used to calculate
addresses, table indices, and similar. Thus, lowering the power
consumption of the adder is an important design objective [12].
The full adder takes three inputs – A, B and Cin and gives
two outputs – Sum and Carry. Sum is given by Equation 3.
(3)
Carry is given by Equation 4.
(4)
The gate level diagram of the full adder is shown in fig.4.
Fig. 5. Full Adder Cell
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319
V.CARRY BYPASS ADDER
Fast adders are used to carry out complex additions with
minimal delay. Each fast adder is tailor made for each function.
Fig. 6. Carry Bypass Adder
Carry bypass adder (CBA) is an adder implementation that
improves on the delay of a ripple carry adder (RCA).
In order to build a 4-bit carry-bypass adder, 6 full adders
would be needed. The input buses would be a 4-bit A and a 4-
bit B, with a carry-in (CIN) signal. The output would be a 4-bit
bus X and a carry-out signal (COUT).
The first two full adders would add the first two bits
together. The carry-out signal from the second full adder (C1)
would drive the select signal for three 2 to 1 multiplexers. The
second set of 2 full adders would add the last two bits assuming
C1 is a logical 0. And the final set of full adders would assume
that C1 is a logical 1 [11].
The multiplexers then control which output signal is used
for COUT, X2 and X3 [11].
VI. RESULTS AND ANALYSIS
A. Transient Analysis
The Full Adder Cell and Carry Bypass Adder are designed
with Stanford University 32nm CNTFET Model and the
proposed 10nm CNTFET model. Both circuits are simulated at
0.9V using HSPICE tool. For the purpose of comparison, the
circuit is designed using 32nm MOSFET, and simulated under
the same parameters. The transient analysis of the Full Adder
using the Stanford model is shown in fig.6.
Fig. 7. Transient analysis of FA using Stanford University CNTFET Model.
The transient analysis of the FA using the proposed
CNTFET model is shown in fig.7.
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TABLE I. POWER, DELAY AND POWER DELAY PRODUCT

ANALYSES FOR FULL ADDER CELL

MOSFET Stanford Proposed

(32 nm) University CNTFET
CNTFET (10nm)
(32nm)
Average
Power 156.8 nW 17.48 nW 13.58 nW

Delay 21.06 ps 13.42 ps 9.642 ps

Power
Delay 3.302 E -18 J 0.235 E -18 J 0.131 E -21 J
Product
Fig. 8. Transient analysis of FA using the proposed CNTFET model.

The analyses for the Carry Bypass Adder are shown in

Table 2.

TABLE II. POWER, DELAY AND POWER DELAY PRODUCT

ANALYSES FOR CARRY BYPASS ADDER
MOSFET Stanford Proposed
(32 nm) University CNTFET
CNTFET (10nm)
(32nm)
Average
Power 533.7 nW 275.2 nW 180 nW
Delay 54.232 ps 35.35 ps 25.31 ps
Power
Delay 28.944 E -18 J 9.728 E -18 J 4.556 E -18 J
Fig. 9. Transient analysis of CBA using Stanford University CNTFET model. Product

The graphs comparing the average power, delay and power

delay product of the full adder circuits are shown in figs.11, 12
and 13 respectively.

200 MOSFET 32 nm
100 CNTFET 32 nm

0 CNTFET 10 nm
Avg. Power (nW)

Fig. 11. Average Power

Fig. 10. Transient analysis of CBA using the proposed CNTFET model.

B. POWER AND OTHER ANALYSIS 40

The CBA is also designed using 32nm MOSFET MOSFET 32 nm
20
technology and Stanford University CNTFET and also with CNTFET 32 nm
proposed CNTFET model. The average power, delay and 0 CNTFET 10 nm
power delay product are analysed. The analyses for the Full
Delay (ps)
Adder Cell are shown in Table 1.
Fig. 12. Delay

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with the proposed model consumes 34.59% less power than the
Stanford model. The delay of the circuit is reduced by 34.82%
4000 MOSFET 32 nm in the Stanford model and by 53.33% in the proposed model as
2000 compared to the MOSFET model.
CNTFET 32 nm It is observed that there is a significant decrease in the
0 power and delay of the circuits designed with CNTFETs. The
Power Delay CNTFET 10 nm
performance of the circuits designed with Stanford University
Product (10^-21 J) model is much better than MOSFET design, while the circuits
designed with the proposed CNTFET model show better
Fig. 13. Power Delay Product
performance characteristics than the other two models.
The graphs comparing the average power, delay and power
delay product of the CBA circuits are shown in figs.14, 15 and REFERENCES
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