ISSCC 2013 / SESSION 6 / EMERGING MEDICAL AND SENSOR TECHNOLOGIES / 6.
6.8 Experimental Demonstration of a Fully Digital
Capacitive Sensor Interface Built Entirely
Using Carbon-Nanotube FETs
Max Shulaker1, Jelle Van Rethy2, Gage Hills1, Hong-Yu Chen1,
Georges Gielen2, H.-S. Philip Wong1, Subhasish Mitra1
1
Stanford University, Stanford, CA,
2
KU Leuven, Heverlee, Belgium
Low-power applications, such as sensing, are becoming increasingly important
and demanding in terms of minimizing energy consumption, driving the search
for new and innovative interface architectures and technologies [1]. Carbon
Nanotube FETs (CNFETs) are excellent candidates for further energy reduction.
CNFET-based digital circuits are projected to potentially achieve an order of mag-
nitude improvement in energy-delay product at highly scaled technology nodes
[2, 3].
This paper presents a complete sensor interface implemented entirely using
CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This
is made possible by using the imperfection-immune paradigm [4], which suc-
cessfully overcomes major obstacles for CNFET-based circuits: mis-positioned
and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200
CNTs depending on transistor sizing, are used to build the circuit. In contrast,
earlier demonstrations of CNFET-based circuits included only small stand-alone
components such as an adder sum, latch, percolation transport-based decoder,
and ring oscillator on a single CNT [4]. Because it is easier to implement digital
circuits using immature technologies compared to analog circuits, highly-digital
sensor interfaces such as the PLL-based design in [5] are ideal implementations
when using a new technology. The implemented capacitive sensor interface is
based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architec-
ture, which processes the sensor information entirely in the frequency domain
(Fig. 6.8.1). Its funcationality is described in detail in [5].
The working principle is as follows: the sensor-controlled oscillator (SCO) gen-
erates a frequency-modulated oscillating signal dependent on the capacitive sen-
sor value ΔCsensor - the value of ΔCsensor influences the delay (and thus the fre-
quency) of one inverter delay cell of the SCO. The sensor information is now
incorporated in the frequency of the SCO (FM modulation). The digital BBPLL
demodulates the sensor-modulated signal, digitizing the sensor information [5].
The demodulation is performed with a digital BBPLL consisting of a single-bit
phase detector (implemented using a D-latch which acts as a single-bit quantiz-
er) and a single-bit digitally-controlled oscillator (DCO) in the feedback loop,
which is implemented identically to the SCO. The single-bit DCO control bit cor-
responds to the output of the system, which is the output of the D-latch. Since
this architecture resembles a first-order noise-shaped ΣΔ-modulator with sin-
gle-bit quantization, a decimation filter (oversampling) has to be utilized to aver-
age the output and thus to increase the resolution of the single-bit output (D-
latch) [5].
All FETs in Fig. 6.8.1, including the 9-stage ring oscillators, the single FETs, and
the D-latch, are fabricated using CNFETs. The CNFETs are fabricated using the
process described in [6], with the modification of using a local back-gate struc-
ture (Fig. 6.8.2). Scanning electron microscopy images of the fabricated circuit-
ry composed of the CNFETs are also shown in Fig. 6.8.2. All the CNFETs are
PMOS, and therefore for proper voltage swing and improved gain in this PMOS-
only logic, the pull-up CNFETs are all sized 20X larger than their respective pull-
down CNFETs. In the past, mis-positioned and metallic CNTs posed major
obstacles to successful demonstration of VLSI-compatible CNFET circuits. We
use the imperfection-immune paradigm [4] which makes the overall circuit
immune to both mis-positioned and metallic CNTs (Fig. 6.8.3). After undergo-
ing all of the processing steps described in [6] and using the design methodol-
ogy described in [4], correct logic functionality is ensured. The D-latch layout
immune to mis-positioned CNTs is shown in Fig. 6.8.3. Transistor implementa-
tions of the circuit elements in Fig. 6.8.1 are also shown in Fig. 6.8.3. The gate
length of the CNFETs is equal to 1μm and the supply voltage of the circuits is 3V,
while Vbias is -5V.
112 • 2013 IEEE International Solid-State Circuits Conference
As a first demonstration of the sensor interface, we use an external capacitor as
the sensor. The capacitance value can be precisely controlled and swept over a
known range. This external capacitor acts as the ΔCsensor of the circuit. The
capacitance ΔCfixed in the DCO is a fixed capacitance, which is equal to the max-
imal value of ΔCsensor. This ΔCfixed can be switched in and out at the DCO. The
9-stage SCO and DCO are both characterized in Fig. 6.8.4. The characteristics of
the frequency as a function of varying capacitive load, controlled through
ΔCsensor, show that both oscillators are running at approximately 1kHz for
ΔCsensor=0 and are closely matched. This is necessary to ensure that the PLL
will be able to lock. Both oscillators show monotonically decreasing frequency
that is directly proportional to the value of ΔCsensor, with a nonlinearity RMS
error of 1.5% for the SCO and 1.9% for the DCO (calculated as the RMS of the
differences between the measured output and a linear fit of frequency vs.
ΔCsensor). Figure 6.8.5 shows the operation of the D-latch with ideal input sig-
nals, confirming that the D-latch functions correctly with good swing. The out-
put of the D-latch is used to connect or disconnect the ΔCfixed from the DCO by
turning on or off the PMOS transistor that connects ΔCfixed to the DCO. We ver-
ified the reproducibility of our results through measurements of multiple
instances of circuit components (SCOs, DCOs and D-latches).
The sensor measurement results are shown in Fig. 6.8.6. The D-latch single-bit
output waveform is plotted as a function of ΔCsensor for 4 discrete values. Since
it is an oversampled output, the average value of the single-bit output equals the
digitized value (as depicted in the plots with the horizontal lines). Simulated
SPICE results show similar trends with the measured output (Fig. 6.8.6), with a
5.5% RMS error between the expected and measured duty cycles. The conver-
sion characteristic shows monotonic behavior as a function of ΔCsensor, but also
shows non-linear behavior. This is due to the fact that a transparent D-latch is
used as the phase detector instead of the more ideal D-flip flop.  In addition, mis-
match in the frequency of oscillation between the SCO and the DCO limits the
dynamic input range. The complete interface consumes 336μW from a 3V sup-
ply.
This work demonstrates the feasibility of CNFET-based electronics for applica-
tions, such as sensing, by successfully implementing a complete sensor inter-
face entirely using CNFETs. The CNFET-implemented sensor interface is capa-
ble of converting a range of sensor capacitance values to a single-bit oversam-
pled digitized output. Although CNFET challenges (doping, contacts, CNT densi-
ty, CNT variations [4]) result in less than ideal performance, this first demonstra-
tion confirms that CNFET-based electronics can be effectively integrated (repro-
ducibly) in a VLSI-compatible way and applied to low-power sensor interface
applications.
Acknowledgements:
The authors acknowledge the support of NSF, FCRP C2S2, FCRP FENA and FWO
Flanders, and the Stanford Graduate Fellowship and the Hertz Foundation
Fellowship for Max Shulaker.
References:
[1] A.-J. Annema, et al., “Analog Circuits in Ultra-Deep Submicron CMOS,” IEEE
J. Solid-State Circuits, vol. 40, no. 1, pp. 132-143, Jan. 2005.
[2] L. Wei, et al., “A non-iterative compact model for carbon nanotube FETs
incorporating source exhaustion effects,” IEDM Dig. Tech. Papers, pp. 917-920,
Dec. 2009.
[3] A. D. Franklin, et al., “Sub-10nm Carbon Nanotube Transistor,” Nano Letters,
vol. 12, no. 2, pp. 758-762, Feb. 2012.
[4] J. Zhang, et al., “Robust Digital VLSI using Carbon Nanotubes,” IEEE Trans.
CAD, vol. 31, no. 4, pp. 453-471, April 2012.
[5] H. Danneels, et al., “A fully-digital, 0.3V, 270nW capacitive sensor interface
without external references,” European Solid-State Circuits Conf., pp. 287-290,
Sept. 2011.
[6] M.M. Shulaker, et al., “Linear Increases in Carbon Nanotube Density Through
Multiple Transfer Technique,” Nano Letters, vol. 11, no. 5, pp. 1881-1886, May
2011.
978-1-4673-4516-3/13/$31.00 ©2013 IEEE
 ISSCC 2013 / February 18, 2013 / 4:45 PM

Figure 6.8.1: Block diagram of the first-order Bang-Bang Phase-Locked Figure 6.8.2: (a) CNFET local back gate geometry (b) typical Id-Vgs and
Loop-based capacitive sensor interface. It consists of a 9-stage sensor- Id-Vds curves for the CNFETs. (c) SEM of single CNFET (d) SEM of four 9-stage
controlled oscillator, a D-latch, and a 9-stage digitally-controlled oscillator ring oscillators stacked vertically, with the 9-stages of inverters cascaded
which function as a PLL to demodulate the sensor-modulated signal. horizontally (e) SEM of D-latch.

Figure 6.8.3: Schematic of (a) delay stage (an inverter) of ring oscillator and Figure 6.8.4: SCO and DCO outputs (and inverted outputs), as well as frequen-
(b) D-latch. The ratio of all pull-up to pull-down transistors is 20:1. cy dependence on Csensor. Both are 9-stage ring oscillators. Both RMS
(c) Imperfection-immune layout of D-latch. The layout and CNT etch ensures nonlinearities are below 2%, and are calculated as the RMS of the differences
correct logic function. (d) SEM of part of D-latch layout. between the measured output and a linear fit of frequency vs. Csensor.

Figure 6.8.6: CNT-based digitized capacitance sensor output. The horizontal

lines give the mean. Simulated (Stanford CNFET SPICE model [4]) and
Figure 6.8.5: Output waveform of D-latch, tested at 1KHz, and all possible measured results show duty-cycle of D-latch increases with increasing
transition states are tested. Csensor (normalized to max. value of Cfixed).

DIGEST OF TECHNICAL PAPERS • 113

 ISSCC 2013 PAPER CONTINUATIONS

Figure 6.8.7: Chip photograph. SEM of segment of individual die shows rows of ring
oscillators, each with various sizing. SEM at the transistor level shows a segment of
an inverter composing one of the ring oscillators.

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