Performance Analysis and Simulation of Two Different Architectures of (6:3)

and (7:3) Compressors Based on Carbon Nano-Tube Field Effect Transistors

Shima Mehrabi1, Keivan Navi2,3, Omid Hashemipour3

1
Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran.
2
Department of Electrical and Computer Engineering, University of California, Irvine, USA
3
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
1
sh.mehrabi@srbiau.ac.ir, 2 navi@sbu.ac.ir, 2 hashemipour@sbu.ac.ir

Abstract partial products. A typical (m:n) compressor takes m equally

In this paper, two different architectures of (6-3) and (7-3)
compressors, including the conventional topology based on
full adder cells with the most interesting of those recently
proposed and XOR/MUX based topology, are analyzed and
compared for speed, power consumption and power-delay
product at transistor-level in Carbon Nano-tube Field Effect
Transistor (CNFET) technology. Simulations are carried out
using Synopsys HSPICE with 32nm CNTFET technology. The
results of simulation demonstrate the superiority of the
XOR/MUX-based structures in terms of PDP and propagation
delay around 9% and 14% respectively.
Keywords: CNFET, Compressor, Exclusive-OR (XOR), Full
Adder, Multiplexer and Nanoelectronics.
Introduction
Since many studies have been accomplished on the
implementation of fast and efficient Adders and Multipliers
which are known as the arithmetic building blocks of
microprocessors and digital signal processors (DSPs),
choosing the appropriate implementation techniques and
technologies are the two major approaches of today’s VLSI
circuit designs. Multipliers play an effective role in the
performance of different practical circuits [1]. Fast multipliers
are generally composed of three sub- functions: partial
product generation, partial product accumulation, and carry-
propagating addition [2, 3]. At the first step, Booth encodings
are often used to reduce the number of partial products. A
summation tree, which is called the Carry Save Adder (CSA),
is used in the second sub-function to further reduce the partial
products to two rows. The last step is normally fulfilled by a
fast carry propagate adder, such as carry look-ahead adder or
carry-skip adder [4].
weighted input bits and produces n-bit binary number [5]. The
simplest and the most widely used one is the (3:2) compressor
(also known as a Full Adder cell) which has 3 inputs to be
summed up and provides 2 outputs. Similarly, a (4:2)
compressor can also be built from two cascaded (3:2)
compressors [6].
In this paper, we analyze two different architectures of
high-speed, low-power (6:3) and (7:3) compressors. The first
circuit implementations designs are utilized of two recent
CNTFET-based Full adder cells and the second
implementation is composed of XOR/MUX gates circuits. To
evaluate the performance of these two different architectural
designs, they have been comprehensively compared at
different voltages, load capacitors and Temperatures.
The rest of the paper is organized as follows: in section II,
conventional design and architecture of (6:3) and (7:3)
compressors are reviewed. Section III, include XOR/MUX
implementation of these two compressors and in section IV,
experimental results, analyses and comparisons are presented
in section V and finally section V concludes the paper.
Architectural Design
A. Conventional (6:3) and (7:3) Compressors Architecture
At present, the most widely used compressors are (3:2) and
(4:2) compressors. In other words, the simplest one is (3:2)
compressor, known as a Full Adder cell. It has 3 inputs to be
summed up and provides 2 outputs. The logic equations of
full adder cell are shown in Eq.(1) and Eq.(2).
ܵ‫ ݉ݑ‬ൌ ‫ܥ ْ ܤ ْ ܣ‬ (1)
‫ ݕݎݎܽܥ‬ൌ ‫ ܤܣ‬൅ ‫ܥ‬ሺ‫ܤ ْ ܣ‬ሻ (2)

To implement fast multipliers, many different architectures
of Processing Elements (PEs) have been presented to perform
arithmetic addition and multiplication. Compressors as one
of the PEs are the fundamental building blocks which are
being used for accumulating partial products during the
multiplication process.
A compressor is a combinatorial device which is mostly used
in multipliers to reduce the operands while adding terms of
Similarly, the (4:2) compressor is simply built by two
cascaded (3:2) compressors. Moreover, as it shown in Fig.1,
the critical path of (3:2) compressor equals 2 XOR gates
delay, and there is no carry on the horizontal path. Also, a
typical (4:2) compressor has a critical path delay of 3 XORs
[7].

978-1-4673-4842-3/13/$31.00 2013
c IEEE 322

Fig. 1 Two fundamental Compressors Architectures
Although, both (3:2) and (4:2) compressors are ideal for
constructing regularly structured Wallace tree with low
complexity [14] but for the compression of a larger number of
bits, higher order compressors are needed. Many researches
show that the multipliers with high order compressors have
better performance [7]. So, the (n:3) compressors together
with Half Adders and Full Adders are utilized in order to
achieve a fast multiplier [8-9]. A (6:3) compressor essentially
comprises of a combinational logic circuit with six inputs and
three outputs. Conventional architecture of high order inputs
compressors such as (6:3) and (7:3) compressors based on the
extended design of a conventional (3-2) compressor are
shown in Fig. 2 (a) and Fig. 2 (b) respectively.
According to Fig.2, the conventional (6:3) and (7:3)
compressors consist of three Full-Adder cells with one Half-
Adder and four Full-Adder cells which are cascaded
respectively. So the critical path of (6:3) consists of two Full-
Adder and one Half-Adder cells. Obviously, the
straightforward implementation of the (7:3) compressor
entails for 6 gate delays.
(a) 6:3 compressor (b) 7:3compressor
Fig. 2 Block diagram of the conventional (6:3) and (7:3)
compressors
B. (6:3) and (7:3) Compressors Architectures Based-on
XOR/MUX Gates
The second compressor structure is focused on the design of
XOR/MUX based (6-3) and (7:3) compressors, attempting to
minimize the stage delays of the conventional structure which
is designed using single bit full adder and half adder
architectures.
By using Eq.(1) and (2) as general representations of the two
outputs of 1-bit Full-Adder cell and suitably rewriting them,
the architecture of the (6:3) compressor has been obtained as
follows (Eq. (3), Eq.(4) and Eq.(5)):
2013 IEEE 5th International Nanoelectronics Conference (INEC)
തതതതതതതതതത
݄Ͳ ൌ ൫‫ݔ‬ ଴ ْ ‫ݔ‬ଵ ൯‫ݔ‬଴ ൅ ሺ‫ݔ‬଴ ْ ‫ݔ‬ଵ ሻ‫ݔ‬ଶ (3)
തതതതതതതതതത
݄ͳ ൌ ൫‫ݔ‬ ଷ ْ ‫ݔ‬ସ ൯‫ݔ‬ଷ ൅ ሺ‫ݔ‬ଷ ْ ‫ݔ‬ସ ሻ‫ݔ‬ହ (4)
݄ʹ ൌ ሺ‫ݔ‬଴ ْ ‫ݔ‬ଵ ْ ‫ݔ‬ଶ ሻሺ‫ݔ‬ଷ ْ ‫ݔ‬ସ ْ ‫ݔ‬ହ ሻ (5)
Based on Eq.(2) it can be found that the second design
uses multiplexer to generate Carry output. Therefore, h0 and
h1 indicate the outputs of multiplexers (MUX0 and MUX1) and
h2 is the AND-gate output. With these 3 equations, the 3
outputs equations would be explored as follows (Eq. (4), (5)
and (6)):
ܱͲ ൌ ‫ݔ‬଴ ْ ‫ݔ‬ଵ ْ ‫ݔ‬ଶ ْ ‫ݔ‬ଷ ْ ‫ݔ‬ସ ْ ‫ݔ‬ହ (6)
ܱͳ ൌ ݄Ͳ ْ ݄ͳ ْ ݄ʹ (7)
ܱʹ ൌ തതതതതതതതതതതതതത
ሺ݄ͳ ْ ݄Ͳሻ݄‫ ݋‬൅ ሺ݄ͳ ْ ݄Ͳሻ݄ʹ (8)
Using the Eq. 6, Eq. 7 and Eq. 8, the architecture of the
(6:3) compressor based on XOR/MUX gates is shown in Fig.
3.
Fig. 3 XOR/MUX based (6:3) compressor Architecture
Similarly, these equations can be simply expandable for (7:3)
compressors as follows to obtain the XOR/MUX based
architecture:
തതതതതതതതതത
݄Ͳ ൌ ൫‫ݔ‬ ଴ ْ ‫ݔ‬ଵ ൯‫ݔ‬଴ା ሺ‫ݔ‬଴ ْ ‫ݔ‬ଵ ሻ‫ݔ‬ଶ (9)
തതതതതതതതതതതതതതതതതതതതതതതതത
݄ͳ ൌ ൫‫ݔ‬ ଴ ْ ‫ݔ‬ଵ ْ ‫ݔ‬ଶ ْ ‫ݔ‬ଷ ൯‫ݔ‬ଷ ൅ ሺ‫ݔ‬ଷ ْ ‫ݔ‬ସ ሻ‫ݔ‬ହ (10)
തതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതതത
݄ʹ ൌ ൫‫ݔ‬ ଴ ْ ‫ݔ‬ଵ ْ ‫ݔ‬ଶ ْ ‫ݔ‬ଷ ْ ‫ݔ‬ସ ْ ‫ݔ‬ହ ൯‫ݔ‬ସ ൅ ሺ‫ݔ‬଴ ْ ‫ݔ‬ଵ ْ
‫ݔ‬ଶ ْ ‫ݔ‬ଷ ْ ‫ݔ‬ସ ْ ‫ݔ‬ହ ሻ‫଺ݔ‬ (11)
where h0, h1 and h2 are the outputs of multiplexers (as the
carry signals of Full-Adder cells). The outputs equations of
XOR/MUX-based (7:3) compressors are the same as the
XOR/MUX-based (6:3) compressor.(Eq.(12),Eq.(13) and
Eq.(14))
ܱͲ ൌ ‫ݔ‬଴ ْ ‫ݔ‬ଵ ْ ‫ݔ‬ଶ ْ ‫ݔ‬ଷ ْ ‫ݔ‬ସ ْ ‫ݔ‬ହ ْ ‫଺ݔ‬ (12)
ܱͳ ൌ ݄Ͳ ْ ݄ͳ ْ ݄ʹ (13)
ܱʹ ൌ തതതതതതതതതതതതതത
ሺ݄ͳ ْ ݄Ͳሻ݄‫ ݋‬൅ ሺ݄ͳ ْ ݄Ͳሻ݄ʹ (14)
323
 Fig. 5 Carbon Nano-Tube Full-Adder (CNTFA) cell design

The Bridge Full Adder cell [14](Fig.6 ) designed by 24

transistors is composed of two modules. The first module
consists of two cascaded high-performance 2-input XOR
circuit to generate the sum and the second one is the
complementary bridge style circuit to generate Cout outputs
with high driving capability.
Fig. 4 XOR/MUX based (7:3) compressor Architecture

As it is evident form Fig.5 and Fig.6, the output of the

compressors require 4 (3 XOR and 1 MUX) and 5 (4 XOR and
1 MUX) gate delays respectively. So the XOR/MUX-based
structures have shorter critical path compared to conventional
structures. Moreover, according to Equation (1) and Equation
(2), the (6:3) compressor requires the use of 7 XOR gates, 7
AND gates and 3 OR gates. Similarly, the (7:3) compressor
requires the 8 XOR gates, 8 AND gates and 4 OR gates for the
straightforward implementation.
The XOR/MUX-based (6:3) compressor requires the use of
7 XOR gates, 1 AND gate and 3 multiplexers, however the
Fig.6Bridge style Full-Adder cell design
XOR/MUX-based (7:3) compressor requires the use of 8 XOR
gates and 4 multiplexers. .With 26-transistors Bridge full adder cell, the conventional
architectures of (6:3) and (7:3) compressors require 92and
104 transistors respectively.
IV. SIMULATION RESULTS In this paper, we use the CNFET-based transmission gate
multiplexer with only six transistors to design the full-swing
A: Performance Analysis and Comparison structure of multiplexer and the full-swing CNFET-based
Since silicon-based microchips will reach the physical pass-transistor XOR gate can be implemented with only eight
limits of miniaturization in the early next decade, CNFET is transistors using pass transistor logic. The two full-swing
one of the most promising devices among emerging circuit design of multiplexer and XOR gates are shown in
technologies [10-12]. Fig.7 (a) and (b) respectively. In order to have inverter gate,
two additional transistors are needed to make an inverter
The 24 transistors Carbon Nano-Tube Full-Adder (CNTFA) signal.
cell is selected as the Full-Adder cell for the comparison
(between conventional and XOR/MUX architecture) due to its
high performance and novel structure [13].As it is depicted in
Fig.5, it is composed of two modules and one sub-module.
The sub-module reduces glitches and power consumption
while the other two modules utilize the full-swing signals of
sub-module to design full-swing low-power high performance
circuits. The second module consists of four Carbon Nano-
tube Transistors, which use no VDD or GND to generate sum
output and the third module consists of eight transistors,
reusing sub-module signals and generating Cout output. With
24-transistors CNTFA, the conventional architectures of (6:3)
and (7:3) compressors require 86 and 96 transistors Fig. 7Circuit design of (a) Multiplexer Gate, (b) XOR Gate
respectively.
Alternatively, the MUX/XOR-based design for (6:3) and
(7:3) compressors with 78 and 88 transistors consumes less
hardware with improvement of 8.3% in transistor count

324 2013 IEEE 5th International Nanoelectronics Conference (INEC)

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Conclusion
In this paper we have carried out a comprehensive analysis
and comparison between two different architectures of (6:3)
and (7:3) compressors and compare them at the transistor
level, including recently XOR/MUX based of full adder cells
and XOR/MUX based architecture. The obtained information
is useful in the early design phases of an adder circuit, since
architectural optimization techniques are based on the
knowledge of the full adder cell used.
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