Design of New Full Adder Cell Using Hybrid-

CMOS Logic Style

Mohammad Javad Zavarei, Mohammad Reza Baghbanmanesh, Ehsan Kargaran,
Hooman Nabovati, Abbas Golmakani
Department of Electrical Engineering, Sadjad Institute for Higher Education, Mashhad, Iran.
m.zavarei231@sadjad.ac.ir

Abstract— In this paper, we propose a novel 1-bit full adder

using hybrid-CMOS logic style. The new full adder is based on
a novel XOR–XNOR circuit that generates XOR and XNOR
full-swing outputs simultaneously and outperforms its best
counterpart showing 28% improvement in power-delay
product (PDP). Design of proposed full adder is based on
improvement in the PDP and it provides full-swing output with
good driving capability. Simulations demonstrate that full
adder successfully operates in the PDP compared to similar
circuits.

I. INTRODUCTION
Full adders are fundamental units in various circuits,
especially in circuits used for performing arithmetic
operations. Circuits like full adders form the building blocks (a)
of many useful operations like multiplication and division.
They are parts of the critical path and thereby influence the
overall performance of entire system. So, enhancing the
performance of the full adders can significantly improve the
system performance.
Many design considerations including the minimum
transistor counts, low power consumption, less delay in
critical path, full-swing output, driving capability, chip area
and layout regularity are focused recently. However, design
of low-power high-speed adder has become one of the most
important and essential researches [1].
Several logic styles have been used in the past to design
full adder cells. Each design style has its own merits and (b)
demerits. Classical designs of full adders normally use only
one logic style for the whole full-adder design. Standard
static CMOS, complementary pass-transistor logic (CPL),
dynamic CMOS logic and transmission-gate full adder
(TGA) are the most important logic design styles in the
conventional adders. The remaining adder designs use more
than one logic style for their implementation. We call this the
hybrid-CMOS logic design style. These designs exploit the
features of different logic styles to improve upon the
performance of the designs using single logic style.
NEW14-T adder [2], hybrid pass logic with static CMOS
output drive full adder [3] (we will use HPSC as an
abbreviation), new-HPSC [4] and new hybrid-CMOS adder
[5] are the examples of adders built with this design style.
Some of them are shown in Fig. 1. (c)

Figure 1. Examples of adder are built with hybrid CMOS design style
(a) HPSC adder [3] (b) NEW-HPSC adder [4] (c) New Hybrid-CMOS [5]

978-1-4577-1846-5/11/$26.00 ©2011 IEEE 451

 In this paper, we proposed a new efficient circuit for the
simultaneous generation of the XOR and XNOR outputs.
We also select the best blocks for output units. The new
adder is optimized for low PDP and is compared with
NEW14T, HPSC, NEW-HPSC and new hybrid-CMOS
adders. The proposed full-adder design exhibits low PDP,
full-swing operation, and good driving capabilities.
II. MAIN STRUCTURE OF FULL ADDER

Generally, hybrid-CMOS full adders are categorized in

three groups depending upon their structure and logical
expression of the Sum output [5]. The first category of full
adders is based on XOR gates and second one is based on Figure 2. Proposed XOR–XNOR circuit as module I
XNOR gates. In Third category, the Sum and Carry outputs
are generated by XOR-XNOR intermediate signals. In this TABLE I. SIMULATION RESULTS FOR XOR-XNOR CIRCUITS IN
0.18µM TECH . AT INPUT FREQUENCY OF 50MHZ, 1.8-V WITH 10FF LOAD
paper, we use the third category for our full adder.
The Sum and Carry (Cout) outputs of a 1-b full adder Circuit Circuit in Circuit in Proposed
in [2,3] [4] [5]
generated from the binary inputs A, B, and Cin can be No of Tr. 6 10 8 10
generally expressed as Power(µW) 12.6 10.52 10.37 7.08
Delay(ps) 370 312 462 362
PDP(e-15) 4.662 3.282 4.79 2.562
Sum = A ⊕ B ⊕ Cin . (1) Improvement(PDP) 82% 28% 87%
Cout = A.B + Cin .( A ⊕ B) . (2)
Owing to the lower power and suitable delay in our circuit,
In third category, the Sum and Carry outputs are there is almost 28% –87% saving in PDP. Since the proposed
generated by the following expression, where H is the XOR circuit has the lowest PDP compared to similar circuits, it
of A and B, and H’ is the complement of H can be used for our full adder.
B. Module II and III
Sum = H ⊕ Cin = H .Cin′ + H ′.Cin . (3) In this section, we choose circuits for module II and III.
Cout = A.H ′ + Cin .H . (4) As shown in (3), we need a 2-to-1 multiplexer with H and
H’ as the select lines for producing the Sum output. We
Generally, this category is divided to three modules. select a circuit for module II. It is shown in Fig. 3(a). This
Module I is a XOR–XNOR circuit producing H and H’ circuit is used in [3-5] as module II and it is similar to our
signals. Module II and III produce Sum and Cout as outputs, proposed circuit for module I. This provides good driving
respectively. Module II and III are 2-to-1 multiplexers with capability due to the presence of the static inverter. This
H and H’ as select lines. The simultaneous generation of H circuit is one of the best performers among all the circuits
and H’ signals is critical in these types of adders because mentioned before in terms of signal integrity and average
they drive the select lines of the multiplexers in the output power-delay product [6].
stage. Otherwise, there may be glitches and unnecessary According to results reported in [4, 5], we select circuit
power dissipation may occur. of Fig. 3(b) as module III for our full adder that produces
A. Module I Carry output. This circuit is based on the static-CMOS logic
style which is presented in [4]. It possesses all the features of
We propose a XOR–XNOR circuit as module I for our
static CMOS logic style such as robustness to voltage scaling
full adder. It is shown in Fig. 2. This circuit produces and good noise margins [5].
intermediate signals (H and H’) simultaneously with full
swing operation. The proposed XOR–XNOR circuit is based III. PROPOSED FULL ADDER
on complementary pass-transistor logic (CPL) and In previous section we introduced the main structure of
transmission-gate logic (TG). Main advantages of TG logic novel full adder. After that the full adder was divided to
are low power consuming and full swing. CPL logic is also three modules. We introduced a circuit for each module.
low power consuming and has a simple design. Fig. 4 shows the proposed full adder. Since the performance
The proposed XOR–XNOR circuit is compared to circuits of the proposed XOR-XNOR circuit is good and we choose
that are used in [2-5]. The simulation results at 1.8-V and the best circuits for module II and III, the performance of
TSMC 0.18µm technology are shown in Table I. this full adder is predicted to be excellent.
Simulation results indicate that the proposed circuit
consumes lower power compared to compared circuits but
the lowest delay is related to XOR_XNOR circuit in [4].

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(a) (b)
Figure 3. (a) The used circuit in [3-5] as module II (b) the used circuit
in [4] as module III
Figure 4. Proposed full adder cell
IV. SIMULATION ENVIRONMENT
A. Simulation Setup
All the circuits are simulated with HSPICE using TSMC
0.18µm technology. To simulate a real environment, input
buffers for all inputs of the test circuit are used. The
transistor sizes of these buffers are chosen such that there is
sufficient signal distortion as expected in an actual circuit
[5]. The used simulation test bench is shown in Fig. 5. For an
accurate result, all the possible input combinations are
considered for all the test circuits. Fig. 6 shows the input
pattern which is used for the full-adder circuits and output
signals of proposed circuit. For the calculation of the power-
delay product, worst-case delay is chosen to be the larger
delay amongst the two outputs.
B. Transistor Sizing
In order to have a fair comparison, all the simulated
circuits are prototyped at optimized transistor sizing values
suggested in [5] to achieve the best PDP. The transistor sizes
of all the simulated circuits have been included in the
figures. In the circuits, the numbers depict the width (W) of
the transistors with the minimum feature size as 2λ. The
proposed circuit has been sized to achieve the best PDP.
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Figure 5. Simulation test bench
Figure 6. The used input pattern for the adder circuits and output signals
of proposed circuit at input frequency of 50-MHz, 1.8-V with 20fF load
V. SIMULATION RESULT AND DISCUSSION
In this section, simulation of full adder cells is presented
under the mentioned conditions in previous sections. The
circuit performance of the test circuits is evaluated in terms
of worst-case delay, power dissipation, and power-delay
product for a range of loads from 10fF to 200fF at 1.8-V
supply voltage. The simulation results are shown in Fig. 7.
Fig. 7(a) indicates the average power dissipation under
different load conditions. Compared to the hybrid-CMOS
full adders, the proposed hybrid-CMOS full adder shows
minimum power dissipation at all loads. Since the proposed
XOR-XNOR circuit as module I dissipates low power,
power dissipation of the new full adder is also low.
The obtained values of delay for considered values of
loads (10fF-200fF) for all the full adders are shown in Fig.
7(b). At lower loads (<50fF), the proposed circuit has
minimum delay compared to other full adders. When the
output load is increased, the NEW hybrid-CMOS [5] and
the proposed full adder have the lowest delay. It means that
under heavy load conditions, adders with driving capability
perform better than those without it. However, at the 200fF
load, the NEW hybrid-CMOS [5] is 18ps faster than the
proposed full adder. New-HPSC adder also performs well
but NEW14T and HPSC adders have high delay compare to
other adders.
The PDP is a quantitative measure of the efficiency of the
 tradeoff between power dissipation and speed, and is
particularly important when low-power operation is needed
[5]. The values of PDP under different output loads are
shown in Fig. 7(c). The values of PDP for the proposed full
adder are least at all loads. While for loads higher than
100fF, NEW hybrid-CMOS adder and the proposed adder
have the same PDP. It means that these adders provide good
driving capability.
Table II indicates the simulation result in 20fF as an
output load. Since the intermediate signals (H and H’) are
produced simultaneously with low power and low delay, the
proposed adder performs well at both power and delay.
Since the module I which is used in HPSC and NEW14T is
very slow and consumes high power, it was predicted that
performance of these adders are poor. As mentioned before,
(a) performance of the NEW Hybrid-CMOS at the loads lower
than 50fF is poor. So, the 20fF as the output load of this
adder has lower speed compared to other adders.

VI. CONCLUSION
In this paper, a hybrid full adder cell consisting of the
XOR/XNOR, sum and carry out sub-circuits, is proposed.
We proposed a new XOR/XNOR circuit based on
complementary pass-transistor logic (CPL) and transmission
gate logic (TG). Both of these logic styles operate in low
power. The new XOR/XNOR circuit has minimum PDP
compared to similar circuits used in recent full adder. We
used this circuit as module I in our full adder. The
Simulation result indicated that the proposed full adder has
minimum PDP under different load conditions. Since the
(b)
performance of the proposed full adder is good, it can
embed as a 4- or 8-b full adder.

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NEW Hybrid-CMOS 24 35.86 527 18.9
NEW-HPSC 26 36.45 498 18.2
Proposed 26 33.48 485 16.2

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