IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO.
12, DECEMBER 2008 1239
Fast Low-Cost Implementation of Single-Clock-Cycle
Binary Comparator
Stefania Perri, Member, IEEE, and Pasquale Corsonello, Member, IEEE
Abstract—This paper presents a new efficient architecture for
the design of fast low-cost single-clock-cycle binary comparators.
The proposed 64-bit circuit requires only 1051 transistors and,
when implemented by using the ST 90-nm 1-V CMOS technology,
it exhibits a running frequency higher than 4 GHz with an average
power dissipation of only 4 mW. Comparison with the fastest
comparator known in the literature demonstrates that, at a parity
of technology used, the novel architecture is 12% faster and
requires 69% less transistors.
Index Terms—CMOS dynamic circuits, comparator, digital
arithmetic, VLSI circuits.
I. INTRODUCTION
N THE LAST few years, the design of high-speed, low-
I power, and area-efficient binary comparators has received
a great deal of attention, since, as is well known, comparison is
a fundamental operation in almost all digital processors. Exam-
ples of efficient architectures of binary comparators are demon-
strated in [1]–[4]. Among hardware implementations existing in
the literature, the latter are very representative solutions. In the
following, these circuits are named full comparators to indicate
that, and being two -bit numbers, they are able to sepa-
rately recognize the three possible conditions in which , sions are drawn.
, and .
In order to reach very high throughput, the approach proposed
in [1] uses two-phase clocking dynamic logic with all-N-tran-
sistor (ANT) blocks. Such a 64-bit comparator requires 1890
transistors and produces the correct result within 3.5 clock cy-
cles.
Single-cycle two-phase clocking architectures are presented
in [2] and [3]. To realize this kind of comparators, a priority
encoding algorithm is used in [2], whereas a parallel MSB
checking method is exploited in [3]. The latter is 22% faster
than [2], but it requires 88% more transistors.
In order to further increase achievable speed, a modifica-
tion of the MSB checking algorithm used in [3] was recently
proposed in [4], where a MUX-based structure specifically
designed for high fan-in comparators is presented. The circuit
demonstrated in [4] exhibits the highest computational speed
but it also requires 3386 transistors to be realized.
Manuscript received April 01, 2008; revised June 20, 2008. Current version
published December 12, 2008. This paper was recommended by Associate Ed-
itor M. Anis.
The authors are with the Department of Electronics, Computer Science and
Systems, University of Calabria, Arcavacata di Rende, 87036 Italy (e-mail:
p.corsonello@unical.it).
Digital Object Identifier 10.1109/TCSII.2008.2008063
1549-7747/$25.00 © 2008 IEEE
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As always happens in the design of digital circuits, achieving
high speed is not the only concern. In fact, also ensuring low-
power consumption and reduced silicon area occupancy is an
important design goal. The novel single cycle comparator pro-
posed in this paper was designed bearing this issue in mind.
A 64-bit comparator designed as described here requires only
1051 transistors, thus reducing the transistor count by about
44%, 36%, 66% and 69% with respect to the circuits described
in [1]–[4], respectively. Moreover, the proposed circuit is 12%
faster than that in [4], which is the fastest single cycle com-
parator known in the literature.
A very important feature of the novel comparator is that its ar-
chitecture can be easily implemented by using both full-custom
and standard-cell-based design approaches. In order to demon-
strate the efficiency of the new circuit, several implementations
were carried out with the STMicroelectronics (ST) 90-nm 1-V
CMOS process and the Austria Micro Systems (AMS) 0.35- m
3.3-V CMOS technology.
The paper is organized as follows. In Section II, a brief back-
ground is given to describe the design principles of existing
comparators; the circuit here proposed is then introduced in
Section III; implementation results and comparisons with ex-
isting comparators are presented in Section IV; finally, conclu-
II. DESIGN PRINCIPLES OF EXISTING BINARY COMPARATORS
Let and be
two 64-bit numbers. As is well known, the comparison between
and can be performed by preliminarily comparing
their corresponding bits. In order to enhance throughput, the ap-
proach proposed in [1] adopts the strategy of comparing two
bits of each input simultaneously through thirty-two 2-bit com-
parators. The results obtained in this way are then input to fur-
ther sixteen 2-bit comparators, and so on till the final result is
produced. The comparator presented in [1] is realized using six
levels of 2-bit comparators and exploiting the half-cycle stealing
of the ANT logic. As a consequence, the comparison between
and is computed within 3.5 clock cycles.
In order to provide the comparison result within only
one clock cycle, the comparator proposed in [2] divides the
logic functions required for comparing and
into two stages. In the first one, eight 8-bit comparators
process eight groups of 8 bits coming from the inputs,
such that the th 8-bit comparator, with , re-
ceives the subwords and
as inputs and produces
three output signals , and to rec-
ognize the cases in which ,
1240 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 12, DECEMBER 2008

and . that, as shown in (3), indicates if the inputs are different. The
Logic equations implemented in this approach are given in signals obtained in this way are input to the priority en-
coder that operates as described by

(4)

The final step of operation is performed by the second stage,

which uses an 8-to-1 multiplexer as the basic component to im-
plement

(5)

Note that and if ,

whereas, when , and .
Finally, both and are equal to 0 if
. Also, in this case, the condition in which
(1)
cannot occur.

where . The signals , III. NOVEL COMPARATOR

and are then sent to the 8-bit comparator used in the The comparison between the two -bit numbers and
second stage that also implements (1), considering , can be performed through an addition operation. In fact,
and in place of , when , the addition between and the
and , respectively. 2’s complement of generates a carry-out signal equal
The approach proposed in [3] determines the location of the to 1, whereas it produces a zero carry-out if .
most significant bit where the inputs are different through a par- Unfortunately, as is well known, low-cost addition architectures,
allel MSB checking method instead of the priority encoder. Also such as ripple-carry, can significantly limit the operating speed.
this technique leads to a two-stage architecture, in which 8-bit On the other hand, high-speed adders, such as the carry-look-
comparators are used as the basic components to implement ahead, can drastically increase the hardware complexity. For
logic equations given in these reasons, the design of efficient comparators known in the
literature does not usually employ addition logic.
The main consideration on the basis of the approach here pro-
posed is that the comparison between and actu-
ally requires a special addition operation that does not produce
the sum bits since only the carry-out signal is necessary to give
the result.
In the following, it is demonstrated how this approach makes
(2) the carry-look-ahead addition (CLA) logic useful to design
high-speed comparators with reduced hardware complexity.

where . Equation (2) leads A. Basic Design Principle

to a full comparator assuring that and In the well-known CLA logic, the basic terms to perform an
if , whereas addition operation are the propagate and the generate signals,
when , and typically computed ORing and ANDing corresponding bits of
. Finally, both and are equal to the input data. These signals are then elaborated to fast compute
0 if . The used logic makes the all intermediate carries and sum bits.
occurrence of the case in which both and are As stated above, a comparison operation requires the addi-
equal to 1 impossible. tion between and the 2’s complement of . The
An alternative high-performance priority encoding algorithm latter can be computed summing 1 to the 1’s complement of ,
was recently proposed in [4] that also presents a two-stage 64-bit which in the following is named . Since
architecture: just the carry-out signal is required to give the result, propagate
and generate terms are not needed for each bit position and, as
(3) an example, they can be computed considering two bits of each
input simultaneously, as shown in

The generic 8-bit comparator used in the first stage performs

logic equations given in (2) and computes a further output signal (6)

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PERRI AND CORSONELLO: FAST LOW-COST IMPLEMENTATION OF SINGLE-CLOCK-CYCLE BINARY COMPARATOR 1241

TABLE I
COMPUTATIONAL STEPS OF COMPARED 64-bit COMPARATORS

where . The signals and can be then makes the occurrence of the case in which
grouped four by four using the CLA logic again, as shown in impossible.1
The novel comparator exploits logic equations completely
different and much simpler than those used in [1]–[4]. There-
fore, it is expected that it will exhibit significantly reduced
hardware complexity. This expectation comes from two basic
considerations: 1) the 32 instantiations of the 2-bit CLA circuits
(7) required to implement (6) are certainly not more complex than
the 64 2-input EXOR (or EXNOR) gates used within conventional
where . The comparison result is finally obtained comparators to compare corresponding bits of the operands
applying and and 2) the eight 4-bit CLA circuits required
to implement (7) are certainly much less complex than the
eight 8-bit comparators used in the conventional implemen-
tations. Simplifications introduced by the novel comparator
can be better appreciated by analyzing the computational steps
required to perform a comparison. In the example reported
in Table I and . For each
(8) computational step elaborated input data and produced output
data are shown. It can be seen that, in comparison with the
approaches [1]–[4] the proposed comparator requires less
It can be seen that can recognize the cases in which computational steps and each step has less input and output
and . In fact, it is equal to signals, thus providing a reduced hardware complexity.
the carry-out signal obtained by summing and .
However, it is not enough to provide the functionality of a full B. Circuit Implementation
comparator. Therefore, the signal is also computed to es- The top-level architecture of the 64-bit comparator here pro-
tablish if . Thus, when , the posed is illustrated in Fig. 1. It uses three levels of operations.
output signals and are both equal to 1, whereas 1This condition differs from existing comparators [2]–[4], in which the case
they are both equal to 0 if . Finally, when Out = Out = 1 cannot occur. However, this does not affect the overall
, is 0 and is 1. The used logic architecture at system level.

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1242 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 12, DECEMBER 2008

Fig. 1. Novel 64-bit comparator.

The first and second levels perform their evaluation phase when
the clock signal is high, whereas they perform the precharge
phase when the clock is low. The third level of the comparator
operates in the opposite manner, thus making the circuit able to
compare two 64-bit inputs within only one clock cycle.
The first stage consists of 32 CLA blocks that generate the
signals and defined in (6). These signals are then
input to the eight 4-bit CLA modules of the second stage, in
which (7) is implemented. Finally, the 8-bit comparator of the
third level completes the comparison operation as given in (8).
Transistor-level implementations of the basic components
used in the novel comparator are depicted in Fig. 2.
It can be seen that both 4-bit and 8-bit CLA blocks exploit
Manchester-Carry-Chain-based architectures. The latter were
chosen to achieve sufficiently high speed with a good time-
area-power tradeoff [5]–[8]. It can also be noted that the output
signals produced by the generic 4-bit CLA block are latched.
Latches are used to make the comparator able to fast operate
within one clock cycle. Remaining modules implemented to
compute the signals , , , , and use
conventional domino circuits. Therefore, their schematics are
not reported here.
In an AMS 0.35- m implementation, nMOS transistors
forming the carry chains depicted in Fig. 2 were progressively
sized using a tapering factor equal to 1.5 and a minimum
transistor width equal to 1 m. Moreover, all of the precharging
transistors are 1.6 m wide. For all other gates, the minimum
sizing approach has been used, thus making the nMOS tran-
sistors in a series m wide. Taking into account the effective
loads on the signals and , the two nMOS
transistors of each latch, used to correctly interface the second
and third stages, are made 6 m wide, whereas a channel
width equal to 4.8 m is set for the pMOS transistor. All level
restorers are minimum sized.
In order to avoid the usage of large transistors, the eight sig-
nals are ANDed through two 4-input AND gates. More-
over, to limit the effects due to the charge sharing occurring in
high fan-in dynamic gates, intermediate nodes of the 4-input
AND gates are also precharged. Simulations demonstrated that
Fig. 2. Transistor-level implementations of the: (a) 4-bit CLA and (b) 8-bit
CLA.
in this case precharging only the central node is enough to re-
move charge sharing. Finally, for the computation of the output
signal defined in (8), a static CMOS 3-input AND gate
is used. The latter was chosen to elaborate simultaneously low-
precharged and high-precharged signals, without requiring any
additional circuitry.
IV. COMPARISON RESULTS
Full-custom implementations of the new 64-bit comparator
were carried out using the AMS 0.35- m 3.3-V CMOS tech-
nology and the commercial ST 90-nm 1-V CMOS process.
Post-layout simulations have been performed considering for
both implementations typical processes and operation condi-
tions (i.e., 25 C and nominal supply voltage). Obtained results,
summarized in Table II, show that the 0.35- m implementation
of the new architecture reaches a maximum running frequency
higher than 720 MHz by dissipating 38 W/MHz. When the
ST 90-nm technology is used, the new comparator achieves a
4.3-GHz running frequency with an average power consump-
tion of only 1 W/MHz. It can be easily verified that the worst
case delay of the proposed comparator occurs when
and (or vice versa), which is the case previously
analyzed in Table I.
The AMS 0.35- m (ST 90 nm) process has a baseline fan-
out-of-4 (FO4) minimum-sized inverter delay of 145 ps (26.8
ps), a silicon area of 36 m (3.3 m ), and a power dissi-
pation of 0.17 W/MHz (0.0027 W/MHz). In Table II, de-
lays normalized to FO4 are also reported for the 0.35- m and

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PERRI AND CORSONELLO: FAST LOW-COST IMPLEMENTATION OF SINGLE-CLOCK-CYCLE BINARY COMPARATOR
TABLE II
RESULTS FOR DYNAMIC FULL-CUSTOM IMPLEMENTATIONS
TABLE III
RESULTS FOR STATIC CMOS STANDARD-CELL-BASED IMPLEMENTATIONS
90-nm implementations. The 0.35- m technology was chosen
for purposes of comparison with the comparators described in
[1]–[4]. In Table II, the two implementations available for the
comparator presented in [2] are named “[2]_C1” and “[2]_C2.”
Analogously, the implementations [3]_C1 and [3]_C2 are ref-
erenced for the comparator described in [3]. Obtained results
demonstrate that the novel circuit improves speed performance
with respect to the fastest comparator described in [4] by 12%
and reduces the transistors count by 69%. Even though av-
erage power consumption of the comparator [4] is not available,
it can be reasonably expected that such a large reduction of tran-
sistors count achieved with the novel circuit also leads to a sig-
nificant reduction of power consumption.
The proposed architecture is found advantageous in terms of
both computational speed and transistors count also over the
comparators presented in [1]–[3]. When compared to [2], the
new circuit is 37% faster and requires 36% less transistors.
Furthermore, it reduces the computational delay and the tran-
sistor count by 20% and 66% with respect to [3].
Equations (6)–(8) discussed in Section III can be imple-
mented in hardware also by using static CMOS standard cells
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1243
instead of the dynamic full-custom cells described above. In
order to do this, Verilog net-list describing the top-level archi-
tecture shown in Fig. 1 was synthesized by the RTL-Compiler
available within the Cadence suite tools [9]. The layout was
then carried out with SOC-Encounter. Obtained characteristics
are summarized in Table III that also gives a comparison with
the synthesizable 64-bit comparator presented in [10]2 and with
a comparator inferred from the Verilog description language
and contained in the Cadence tool library. The static CMOS
90 nm implementation of the novel comparator operates at a
2.7-GHz running frequency dissipating only 4.4 mW.
From Table III, it can be seen that, at a parity of compu-
tational delay, the 90-nm implementation of the novel com-
parator requires 11% and 28% less silicon area than [10] and the
Cadence reference circuit, respectively. Moreover it dissipates
10% and 30% less power. Similar results are achieved also with
the 0.35- m implementation. In this case, 21% and 10% reduc-
tions of the computational time are also achieved with respect
to [10] and the Cadence reference circuit.
V. CONCLUSION
Binary comparison is a fundamental operation for most dig-
ital systems. Therefore, the design of comparators offering good
area-time-power tradeoff is strongly desired.
This paper demonstrates that binary comparators can benefit
from the carry-look-ahead logic to achieve high-speed with rea-
sonable area occupancy and power consumption. Results pre-
sented here demonstrate that the proposed approach can be ef-
ficiently applied to both dynamic full-custom and static CMOS
standard-cell-based implementations.
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2For purposes of comparison, only the portion required for comparing 2’s
complement numbers has been synthesized and laid out.