CONTRIBUTED

P A P E R

Spin-Transfer Torque
Memories: Devices, Circuits,
and Systems
This paper reviews the fundamentals of spin-transfer torque memories and discusses
key experimental breakthroughs before covering the state of the art and the device
design concepts and challenges.
By Xuanyao Fong, Member IEEE , Yusung Kim, Rangharajan Venkatesan, Member IEEE ,
Sri Harsha Choday, Student Member IEEE , Anand Raghunathan, Fellow IEEE , and
Kaushik Roy, Fellow IEEE

ABSTRACT | Spin-transfer torque magnetic memory I. INTRODUCTION

(STT-MRAM) has gained significant research interest due to
its nonvolatility and zero standby leakage, near unlimited en-
durance, excellent integration density, acceptable read and
write performance, and compatibility with CMOS process
technology. However, several obstacles need to be overcome
for STT-MRAM to become the universal memory technology.
This paper first reviews the fundamentals of STT-MRAM and
discusses key experimental breakthroughs. The state of the
art in STT-MRAM is then discussed, beginning with the device
design concepts and challenges. The corresponding bit-cell
design solutions are also presented, followed by the STT-MRAM
cache architectures suitable for on-chip applications.
KEYWORDS | Design of spin-transfer torque MRAM; emerging
nonvolatile memory technology; magnetic tunnel junction;
nonvolatile on-chip caches
Manuscript received January 22, 2015; revised October 16, 2015 and January 13,
2016; accepted January 15, 2016. Date of publication April 7, 2016; date of current
version June 16, 2016. This work was supported in part by C-SPIN, one of six centers
of StarNET, a Semiconductor Research Corporation program sponsored by MARCO
and DARPA,
by the Semiconductor Research Corporation, by the National Science Foundation,
NSSEFF, by Intel Corporation, and by Qualcomm.
X. Fong is with the Institute of Microelectronics, Agency for Science Technology and
Research (A*STAR), Singapore 138634, Singapore (e-mail: fongx@ime.a-star.edu.sg).
Y. Kim is wth Advanced Design, Logic Technology Development,
Intel Corporation, Hillsboro, OR 97124 USA.
R. Venkatesan is with NVIDIA Research, Santa Clara, CA 95050 USA.
S. H. Choday is with Intel Labs, Intel Corporation, Hillsboro, OR 97124 USA.
A. Raghunathan and K. Roy are with the School of Electrical and Computer
Engineering, Purdue University, West Lafayette, IN 47907 USA
(e-mail: raghunathan@purdue.edu; kaushik@purdue.edu).
Digital Object Identifier: 10.1109/JPROC.2016.2521712
0018-9219 Ó 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
The increasing leakage power in on-chip memories as a
result of CMOS technology scaling is a critical problem
that needs to be overcome in future microprocessors.
Proposals for nonvolatile memory technologies that en-
able powered-down operation during “idle mode” can po-
tentially alleviate the leakage problem. Although several
nonvolatile memory technologies have been proposed,
most are not suitable for on-chip cache applications for
a variety of reasons (e.g., poor performance and/or en-
durance, high energy consumption for read/write, poor
reliability, or incompatibility with CMOS fabrication
process).
Furthermore, the integration density of dynamic
RAM (DRAM) and performance of static RAM (SRAM)
are desired for the nonvolatile memory technology to im-
plement highly energy-efficient on-chip caches. A large
on-chip cache capacity reduces the number of off-chip
memory accesses and improves the overall system perfor-
mance. However, there is a tradeoff between the access
latencies of the on-chip cache and the capacity of the
cache [1], [2]. Hence, nonvolatile memory technologies
proposed for on-chip cache applications need sufficient
performance when the cache capacity is large.
Of the nonvolatile memory technologies that have
been proposed, spin-transfer torque magnetic random
access memories (STT-MRAM) have emerged as the
leading candidate for on-chip cache applications. STT-
MRAM can achieve the integration density of DRAM
and potentially match the performance of SRAM. Com-
pared to competing nonvolatile memory technologies,
STT-MRAM is compatible with the CMOS fabrication
Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1449
Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

process and has better combination of retention time,

endurance, and reliability. Although spin-transfer torque
(STT)-based memory is an attractive candidate for uni-
versal memory technology, much research effort is
needed to overcome the key design issues that prevent
widespread adoption of the technology. The key thrust
in the research effort has been to reduce the relatively
high write energy (compared to CMOS on-chip caches)
of STT-MRAM, and to improve their reliability and read
speed.
This paper serves as a review of the state of the art in
STT-MRAM research. Key design challenges that need to
be overcome in STT-MRAM will be presented along with
possible solutions that have been proposed in the litera-
ture. Our discussion begins in Section II with an intro-
duction to the magnetoresistance effect, which was
experimentally observed by Jullière in 1975 [3]. The rest
of Section II discusses the basic device structures that ex-
ploit the giant and tunneling magnetoresistance effects,
the core technology for STT-based memory applications.
We then shift the focus of our discussion to other aspects
of STT-based magnetic devices for memory applications
in Section III. Specifically, we discuss how the device Fig. 1. Physical structure of a vertical spin valve. The type of
may be programmed and the ability of the device to re- magnetoresistance depends on the spacer layer used. The free
layer has an anisotropy energy barrier so that the spin valve is
tain the data stored in it. The concept of energy barriers
in either parallel or anti-parallel configuration. The direction of
and the spin-transfer torque phenomenon are discussed current flow to switch the spin valve configuration is also
in this section as well. The basic design of an STT- shown on top.
MRAM bit-cell is presented in Section IV to show the
design issues and where the inefficiencies in the design
come from. Section V focuses on various device-level de-
sign techniques for improving STT-MRAMs. We first are two types of spin valves depending on the type of
consider two-terminal magnetic tunnel junction (MTJ)- spacer layer used. Spin valves using an insulator spacer
based device structures. Their drawbacks and limitations layer exploit the tunneling magneto-resistance (TMR) ef-
are discussed to motivate the discussion on multiterminal fect discovered by Jullière in 1975 [3]. On the other
device. As we will see in Section V, the high write en- hand, spin valves using a nonmagnetic metal spacer layer
ergy in STT-MRAM poses a significant design challenge. exploit the giant magneto-resistance (GMR) effect dis-
Several alternative physical phenomena, such as spin-orbit covered separately by Fert and Grünberg [4], [5], for
torque and voltage-controlled magnetic anisotropy which they were awarded the Nobel Prize [6]. The key
(VCMA), may be exploited to lower the write energy in characteristic of spin valves is that their conductance de-
STT-MRAMs. The associated device structures are also pends on the relative magnetization directions of the
presented in Section V. The details of the circuit-level magnetic layers (see Fig. 1). The conductance is high
design techniques (or the bit-cells) are presented in and low when the magnetization directions are parallel
Section VI. The STT-MRAM array/architecture level de- (P) and anti-parallel (AP), respectively. A key metric to
sign techniques along with error correction techniques to describe spin valves is the magneto-resistance (MR) ratio
improve reliability and energy consumption are de- given by
scribed in Section VII. Finally, Section VIII concludes
this paper. GP  GAP
MR ¼  100%: (1)
GAP
II. MAGNETORESISTANCE E FFECT
The spin valve structure, as shown in Fig. 1, is the basic In the first experiments, Jullière and Fert measured MR
building block of spin-transfer torque memories. The ratios of 14% and 80% in Fe/Ge-O/Co tunnel junctions
magnetization of a magnetic layer in the absence of ex- [3] and in Fe/Cr superlattices [4], respectively, at
ternal stimulus is engineered to point along a particular T  4:2 K (T is the temperature). Since then, many
direction called its easy axis. Note that the easy axes of studies have been done to understand GMR and TMR
the magnetic layers in the spin valve are collinear. There effects [7]–[18].

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 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Table 1 Comparison of Metrics for GMR and TMR Spin Valves presence of thermal agitations, the stability or lifetime
ðtLIFE Þ of the nano-magnet state is related to EB by [21]


EB
tLIFE ¼ t0 exp (3)
kB T

where kB is the Boltzmann constant, T is the tempera-

The GMR effect may be understood by considering
ture, and t0 is the inverse attempt frequency (1 ns).
the scattering of spin-polarized electrons as it passes
For a nano-magnet with EB  40kB T, tLIFE  7:4 years.
through the spin valve [19]. When the spin valve is in
An MTJ consists of two ferromagnetic layers sand-
the P configuration, the electrons flowing through the
wiching an insulator spacer layer (tunnel oxide layer) as
device experience little scattering. However, electrons
illustrated in Fig. 1. The electrical resistance of the MTJ,
experience a lot of spin scattering when the spin valve is
RMTJ , is low when the MTJ is in the P configuration
in the AP configuration.
(RMTJ ¼ RP ¼ RL or “0” state). On the other hand, RMTJ
The TMR effect may be explained by the spin filtering
is high when the MTJ is in the AP configuration (“1”
effect that arises due to the bandstructures of the constit-
state or RMTJ ¼ RAP ¼ RH ). In order to ensure proper op-
uent layers of the spin valve [19]. As a result, the proba-
eration of the device, one of the ferromagnetic layers is
bility of electrons tunneling across the insulator spacer
used as the reference layer and is magnetically pinned
layer depends on the configuration of TMR-based spin
(called the pinned layer or PL). The magnetization of the
valve. Hence, the TMR-based spin valve can be engi-
other ferromagnetic layer (called the free layer or FL) is
neered to achieve MR ratios far higher than that achiev-
free to rotate and is used to store spin information. As
able by GMR-based spin valves at room temperature.
mentioned earlier, uniaxial anisotropy is engineered into
Together with the fact that the resistance of TMR spin
the FL to create an energy barrier that ensures thermal
valves is much higher than that of GMR spin valves, the
stability.
magnetic configuration of the TMR spin valve may be
The MTJ may be switched between the P and the AP
electrically sensed by CMOS circuits more easily than in
configurations using a magnetic field also known as
the GMR spin valve. These differences are summarized
field-induced magnetization switching (FIMS). For on-
in Table 1, showing that TMR spin valves are more desir-
chip applications, the magnetic field is generated using
able than GMR spin valves for on-chip memory applica-
current carrying wires as in field-switched magnetic
tions. The spin filtering effect may also be exploited for
RAM (MRAM) [22]. The magnetic field, H, generated
manipulating the magnetic configuration of the TMR-
by the current, I, in the wire is given by
based spin valve as we will discuss later on.

I
II I. SPIN-TRANSFER- TORQUE-BASED jHj ¼ (4)
2r
MEMORY DEVICE
The alignment of the magnetization of a nano-magnet,
where r is the distance between the wire and the nano-
m, along its easy axes is retained in the presence of ther-
magnet. This field needs to overcome the critical field
mal agitations by an energy barrier ðEB Þ as shown in
needed to program the magnetic state of the MTJ, which
Fig. 1. Note that higher-order effects have been ignored:
is given by
We are assuming that the EB that needs to be overcome
for switching from 0 to 180 ðEB;1 Þ is identical to that
for switching from 180 to 0 ðEB;2 Þ. Higher-order effects 2EB
may result in EB;1 6¼ EB;2 . When this is the case, the ef- jHj 9 HC ¼ (5)
0 MS V
fective EB is the smaller of EB;1 and EB;2 . The EB in nano-
magnets can be created with uniaxial anisotropy, and it
is related to the volume, V, of the nano-magnet by [20] Hence, the critical current, IC , required to generate the
magnetic field for switching is

0 MS VHC
EB ¼ Ku2 V ¼ (2) 4EB r
2 IC 9 : (6)
0 MS V
where Ku2 is the second-order uniaxial anisotropy
constant, MS is the saturation magnetization of the nano- The volume of FL scales as r2 as the MTJ size is scaled
magnet, and HC is the magnetic anisotropy field. In the down. As a result, the iso-EB switching current increases.

Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1451

Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Furthermore, the applied magnetic field to switch the
MTJ is not well confined and can affect MTJs in close
proximity to the current carrying wires. The magnetic
field from the current carrying wires in FIMS-based
MRAM may accidentally switch the states of these MTJs.
Based on the above considerations, it is widely accepted
that FIMS-based MRAM is not scalable [23].
STT provides an alternative switching mechanism
[14], [24]–[27] that overcomes the scalability issues in
field-switched MRAM. Consider the case when electrons
flow from PL to FL in an MTJ. Since magnetic layers are
polarizers of electron spin, PL strongly polarizes the spin
of incoming electrons in the direction of PL magnetiza-
tion, mP . As the electrons tunnel across the barrier into
FL, they exert a torque that aligns FL magnetization, m,
with mP . On the other hand, when electrons tunnel from
FL to PL, the FL tries to polarize the incoming electrons
with spins in the direction of the FL magnetization, m.
However, electrons with spin in the direction of mP tun-
nel across the barrier easily and are removed from FL.
Electrons with spin opposite to mP cannot tunnel across
the barrier easily and remains in FL, exerting a torque
on m. The torque exerted aligns m opposite to mP . Thus,
the direction of current flow determines the switching
direction (Fig. 1). Also, the IC for parallelizing FL with
PL is lower since the spin of electrons injected into FL
are mostly in the direction of mP . Electrons entering FL
when anti-parallelizing FL with PL are not as well polar-
ized and, hence, a larger IC is needed to anti-parallelize
FL with PL.
A few words are in order so the scalability of STT
may be understood. The magnetization dynamics of a
mono-domain FL in an MTJ may be modeled using the
Landau–Lifshitz–Gilbert–Slonczewski (LLGS) equation [28]


@m @m
¼ jjm  H EFF þ  m  þ STT (7)
@t @t
where  is the gyromagnetic ratio,  is Gilbert’s damping
factor, and H EFF is the effective magnetic field acting on
the nano-magnet. Uniaxial anisotropy and demagnetizing
fields are included in H EFF . Generally, the spin-transfer tor-
que is given by [24], [25], [28]–[30]
  

h  
STT ¼  I m  ðmP  mÞ  0 mP
 (8)
2 eM V 2EB
0 S
where h is the reduced Planck constant, and e is the elec-
tronic charge. Also,  and 0 models the Slonczewski-like
and field-like torques, respectively, and may be functions of
m and mP [29].
Let us first consider the case where FL has only uni-
axial magnetic anisotropy. Let us also simplify (8) by
1452 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
assuming  to be constant and 0 ¼ 0.  describes the
degree to which the current flowing through the MTJ is
spin-polarized and depends on the spin filtering effect
discussed in Section II. To determine the condition for
STT to switch the MTJ configuration, (8) is substituted
into (7) and rearranged. Since only the damping torque
needs to be considered to obtain the condition for STT
to switch the MTJ configuration, the following condition
is obtained:
 
 h 
2 eM V I  HC :
(9)
0 S
Using (5) in (9) and rearranging, the critical current, IC ,
for STT switching is given by
4eEB
IC ¼ : (10)
h
Hence, at iso-EB , IC in STT-based switching can be
constant when the MTJ size is scaled down, whereas it
increases for FIMS-based MRAM. As such, STT-MRAM
is more scalable as compared to FIMS-based MRAM.
The magnetization of the ferromagnetic layers in an
MTJ can be made to have in-plane anisotropy (IMA) or
perpendicular magnetic anisotropy (PMA) [14], [23], [27],
[31]–[37]. As Fig. 2 shows, MTJs with IMA have thin
film ferromagnetic layers whose uniaxial anisotropy easy
axes are in the plane of the thin film layers [14], [31],
[32]. The uniaxial anisotropy easy axes of thin film ferro-
magnetic layers in MTJs with PMA are perpendicular to
the plane of the thin film layers [27], [33]–[35]. The
shape of an MTJ with IMA determines its uniaxial an-
isotropy barrier. Magnetocrystalline anisotropy domi-
nates in MTJs with PMA, and hence, the shape of the
MTJ has less effect on the anisotropy energy. Thus, MTJs
with PMA can have circular cross sections and are pre-
ferred to achieve maximum integration density. Further-
more, the uniaxial anisotropy field and demagnetizing
field are collinear in MTJs with PMA, and the effective
field STT needs to overcome during switching is given by
(5). In MTJs with IMA, STT needs to overcome an effec-
tive magnetic field given by [28]
HDemag
jH EFF j ¼ þ (11)
0 MS V 2
where the last term on the right-hand side models the
demagnetizing field in the out-of-plane direction [28].
Since the effective field that STT needs to overcome dur-
ing switching in MTJs with IMA is higher than that in
MTJs with PMA, the IC of MTJs with IMA are higher
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 2. Geometries of MTJ with IMA and with PMA. The aspect
ratio (AR ¼ LY =LX , LX and LY are the length of the FL in the
x- and y-directions, respectively) of the IMA-based MTJ can be
used to engineer the shape anisotropy of the FL that determines
EB , whereas the thickness of the FL can be used to determine
EB in PMA-based MTJ and the AR can be 1, which is better for
integration density.
than that of MTJs with PMA having the same model
parameters as summarized in Table 2. Hence, MTJs with
PMA are expected to be able to achieve lower switching
energy as compared to MTJs with IMA. Note AR can be
1 for PMJs, making them suitable for higher integration
density.
A. Scalability of MTJs
STT-MRAM implemented using IMA and PMA-based
MTJs were studied in the literature to understand the
impact of scalability of STT-MRAM bit-cells [37], [38].
The STT-MRAM bit-cells compared in [37] and [38]
were designed with the same retention time and EB and
bit-cell layout styles. The bit-cells were also designed
such that their read and write failure rates were approxi-
mately the same. The minimum lateral feature size of
the MTJ is matched to that of the technology of the ac-
cess transistor. The design specifications were also
matched to those listed in the ITRS roadmap [39].
Table 2 Comparison of IC for MTJs With PMA and With IMA
The scaling analysis performed in [37] and [38]
matched the bit-cell write failure rates by ensuring that
the voltage needed to switch IMA and PMA MTJs are
the same. The resistance-area (RA) product of the MTJ,
which corresponds to the thickness of the MTJ tunneling
oxide and the reliability of the MTJ, needed to meet the
design specifications were then determined. It was then
shown that under the assumed design constraints, STT-
MRAM with PMA-based MTJs outperforms STT-MRAM
with IMA-based MTJs when the minimum lateral feature
size is larger than 22 nm. Below that, STT-MRAM
with IMA-based MTJs were shown to be better than their
PMA-based counterparts. In [38], the poor scalability of
MTJs based on interfacial PMA is attributed to the diffi-
culty in engineering the barrier height to meet thermal
stability requirements. Furthermore, the IC of the MTJ is
unaffected by the scaling down of the physical dimen-
sions of the MTJ [37], [40], [41], whereas that of IMA-
based MTJs scale down with the physical dimensions of
the MTJ [37]. Also, due to the larger cross-sectional area
of MTJ with IMA compared to that with PMA, the resis-
tance of the MTJ with IMA is sufficiently small such that
the CMOS access transistors are able to meet the write
current requirements at the corresponding supply
voltage.
However, it was shown in [42] that when IMA-based
MTJs are scaled down at iso-EB , the induced shape an-
isotropy causes the easy axis of the FL to align perpen-
dicular to the substrate plane, just like in PMA-based
MTJ. Although the scaled IMA-based MTJs seem to be
PMA, the thickness of the FL is too large. The mono-
domain assumption may no longer be valid in this case.
When electron current flows in MTJs with very thick FL,
STT occurs mostly at the interface between the FL and
the tunnel oxide. The charge current may completely
lose spin-polarization in the FL, and as a result, STT may
not be exerted on the magnetization of the rest of FL.
Hence, PMA-based MTJs may be the only option for
high-density STT-MRAM with large EB or retention time.
B. Thermal Effects in MTJs
Strictly speaking, IC calculated from (9) is the mini-
mum current required to switch the FL in an MTJ.
However, switching has been observed at currents less
than IC because the switching process is stochastic
[23], [43]–[46]. The randomness of the switching pro-
cess is due to thermal effects that may be modeled as
an effective magnetic field given by [47]–[49]
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2kB T
H Thermal ¼X (12)
jjMS Vt
where X is a vector with components that are indepen-
dent Gaussian random variables, kB is the Boltzmann
Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1453
Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

constant, T is the temperature, and t is the constant I V. DESIGN OF SPIN-TRANSFER

time-step used in the numerical simulation of the switch-
ing process. H Therm affects switching dynamics of MTJs
in two ways. First, it affects the switching process be-
cause it is always present. Second, it affects the initial
relative angle between m and mP . Depending on the op-
erating regime, the impact of each on the switching
process is different.
In the precessional switching regime (switching delay,
tSW  3 ns), the distribution of tSW depends mostly on
the initial angle, , between m and mP . This may be
described by [44]
 
 operation being performed on the STT-MRAM bit-cell.
ln 2
tSW / (13)
I  IC0
T ORQUE M RAM BI T- CEL L S
In this section, we will discuss the design of an STT-
MRAM bit-cell. Its basic operations are presented along
with the design issues that need to be overcome.
A. Basic Bit-Cell Design
The structure of the standard STT-MRAM bit-cell
consists of an MTJ and an access transistor (ATx) con-
nected as shown in Fig. 3 (known as 1T-1MTJ or 1T-1R
STT-MRAM bit-cell) [32], [57]–[61]. The ATx’s allow se-
lective access to the MTJs, the storage elements in the
memory array, as Fig. 3 shows. Let us consider the write
The word line (WL) connected to the bit-cell is charged

where IC0 is the critical switching current at the charac-

teristic switching delay (usually 1 ns). The thermal agita-
tions in  may be modeled as a Boltzmann distribution
[50]–[52]

!
EB cos2 
PðÞ / exp : (14)
kB T

The switching probability, PSW , of the MTJ in the preces-

sional switching regime may be estimated by combining
(13) and (14) to yield [44]



PSW / exp ð1  cos2 Þ ðI  IC0 Þ sin2 (15)
2

where  ¼ EB =kB T, ¼ ð=2Þ expðð2B =eMS VÞðI

IC0 ÞtSW Þ,  is the effective spin polarization of the charge
current, and B is the Bohr magneton. However, in the
thermal activation regime ðtSW  10 nsÞ, PSW is instead
given by [46], [53]

0 1

!
t I
PSW ¼ 1  exp@ exp  1  A (16)

IC0

where
is the characteristic switching time (usually 1 ns).
When current flows through the MTJ, Joule heating in the
MTJ effectively reduces . Hence, thermally assisted
MRAM that uses write current to heat the MTJ and oper-
ate STT-MRAM in the thermal activation regime has been
proposed [54]–[56]. However, thermally assisted MRAM
may be unsuitable for memory applications requiring write
latency shorter than 10 ns.
Fig. 3. (a) STT-MRAM bit-cell may be connected in the
“top-pinned” or “bottom-pinned” configuration. (b) 2  2 array
of bit-cells is shown. A row of cells is selected by charging the
WL along that row to VDD . The MTJs are represented as variable
resistances. (c) Regardless of bit-cell configuration, the access
transistor may become source degenerated during one of the
write operations due to the need for bidirectional write
current flow.

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 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
to VDD so that the ATx of the bit-cell can pass current be-
tween the bit line (BL) and source line (SL) through the
MTJ. If a “0” (or low resistance state, LRS) is to be writ-
ten into the bit-cell, a current is passed from FL to PL so
that the MTJ is programmed into P configuration. BL is
charged to VDD , and that of SL is discharged to GND so
the MTJ is parallelized to P configuration. If instead a “1”
(or high resistance state, HRS) is to be written into the
bit-cell, the direction of current flow is reversed so that
the MTJ is anti-parallelized into AP configuration. SL is
charged to VDD , and that of BL is discharged to GND so
that the current flows from PL to FL. Note that VDD
must be set such that write current flowing through the
MTJ ðIWR Þ is at least the critical currents, IC (‘0’) and
IC (‘1’), needed to write a “0” and a “1,” respectively.
For read operation [62]–[65], the WL connected to
the bit-cell that is selected for reading is charged to VDD .
In voltage sensing scheme, a read current ðIREAD Þ is passed
through the bit-cell so that a voltage develops between
BL and SL ðVCELL Þ. A voltage sense amplifier (VSA) com-
pares VCELL to a reference voltage, VREF . The bit-cell
stores HRS if VCELL 9 VREF , and the VSA outputs a “1.”
Otherwise, the bit-cell stores LRS and the VSA outputs a
“0.” In current sensing scheme, the voltage across the BL
and SL is fixed at a read voltage, VREAD . The current
flowing through the bit-cell ðICELL Þ is compared to a ref-
erence current, IREF , using a current sense amplifier
(CSA). The bit-cell stores an LRS if ICELL 9 IREF , and the
CSA outputs a “0.” Otherwise, the bit-cell stores HRS
and the CSA outputs a “1.” The sensing schemes just dis-
cussed are single-ended in nature. Also, note that current
flows through the MTJ during read operations regardless
of the sensing scheme used. Since write operations also
occur by passing current through the MTJ, the current
through the MTJ during read operations needs to be kept
small to ensure that the bit-cell is not accidentally over-
written during read operations.
B. Design Issues of 1T-1MTJ STT-MRAM Bit-Cell
Just as in FIMS-based MRAM, the endurance and re-
liability of the MTJ is crucial for the functionality and
performance of STT-MRAM. The important reliability is-
sues in the MTJ are mainly due to time-dependent di-
electric breakdown (TDDB) and time-dependent
resistance drift (TDRD) [66]–[69]. Dielectric breakdown
results in a sharp decrease in MTJ resistance and loss of
magneto-resistance. TDDB manifests as an abrupt de-
crease in the MTJ resistance, whereas TDRD exhibits a
gradual decrease in the MTJ resistance [66]. The occur-
rence of either failure leads to decrease in the MTJ resis-
tance, which in turn manifests as stuck-at-P faults. These
reliability issues are mitigated by ensuring that the MTJ
is not overly stressed. Hence, reducing the IC of the MTJ
is desirable for reducing the stress on the MTJ and also
in reducing the write energy consumption of STT-
MRAM. This is also desirable for mitigating
electromigration in the interconnect layers supplying
current to the MTJ.
As the MTJ and the CMOS technology are scaled
down, the magnetic layers of the MTJs are spaced closer
together. Asymmetry may be introduced into the energy
landscape of the free layer of an MTJ due to stray mag-
netic fields from the neighboring MTJs, as mentioned
earlier in Section III. Note that from the perspective of
the FL of the MTJ, the stray field from the PL of the
MTJ may be stronger than stray fields from the neighbor-
ing MTJs due to the close proximity of the PL to the FL
in the MTJ. The effective EB may reduce due to these
stray fields resulting in increased retention failures,
which occur when thermal agitations flip the configura-
tion of the MTJ in the absence of any input stimulus.
The presence of stray magnetic field may also increase
the asymmetry in IC that we discussed in Section III.
Failures in operation of STT-MRAM bit-cell may also
occur due to process variations in the MTJ and the ATx.
Note that the thickness of the tunnel oxide ðtMgO Þ and the
dimensions of FL may vary due to process variations.
These variations lead to variations in the static and dy-
namic behavior of the MTJ and contribute to failures in
STT-MRAM bit-cell operation. These failures may be clas-
sified as write failure, disturb failure, and decision failure
[62], [63]. Write failures occur when IWR G IC . This may
occur when the ATx resistance is too large or when RMTJ
is too large because tMgO is too thick, or when variations
in the MTJ result in a higher-than-expected IC . Since cur-
rent flows through the STT-MRAM bit-cell during the
read operation, thermal effects may lead to disturb fail-
ures. Moreover, disturb failure may occur when the cur-
rent flowing through the MTJ, IMTJ , is more than IC
during the read operation. This may occur due to a lower-
than-expected RMTJ because tMgO is too thin, the variations
in the MTJ causing IC to be lower than expected, or a
lower ATx resistance due to process variations. Decision
failures occur when the sense amplifier incorrectly senses
RMTJ , i.e., LRS is sensed as HRS or HRS is sensed as LRS.
In the current sensing scheme described in Section IV-A,
decision failure occurs when ICELL 9 IREF for a bit-cell
storing HRS and ICELL G IREF for a bit-cell storing LRS.
Decision failure in the voltage sensing scheme occurs
when VCELL 9 VREF for a bit-cell storing an LRS and
VCELL G VREF for a bit-cell storing an HRS. Generally, deci-
sion failures occur because process variations in the bit-
cell lead to lower-than expected bit-cell resistance ðRCELL Þ
when it is storing an HRS, and higher-than-expected RCELL
when it is storing an LRS. Thus, bit-cell parameters (tMgO ,
FL dimensions, VDD , VREAD and IREF or IREAD and VREF ,
ATx width, etc.) must be carefully chosen to minimize
bit-cell failures and to meet design targets.
However, there are many conflicting design require-
ments that STT-MRAM bit-cell designers face. For exam-
ple, if tMgO is increased to improve the distinguishability
between RP and RAP (MR ratio of an MTJ was
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
experimentally observed to increase with tMgO in [14],
[70], and [71]), decision failures would reduce. However,
RMTJ would increase, and as a result, IWR would reduce.
Hence, if VDD is not increased correspondingly, write
failures would increase. Similar tradeoffs in varying the
other bit-cell design parameters mean that the design
space for STT-MRAM bit-cells may become extremely
limited when designing for multiple constraints (power,
performance, reliability, etc.).
The stochastic nature of spin-transfer torque also
poses a design challenge. A relatively large IC is required
to achieve low write error rates even in the absence of
process variations. The need for bidirectional write cur-
rent in standard STT-MRAM bit-cells further exacerbates
the problem. Consider the bit-cell bias for writing a “0”
into the “bottom-pinned” bit-cell as shown in Fig. 3.
Note that the terminal of ATx that is connected to SL is
the source terminal of ATx and, hence, VGS ¼ VDD for
ATx. Now, consider the bit-cell bias for writing a “1”
into the same bit-cell. Since the direction of IWR is re-
versed, the terminal of ATx that is connected to the MTJ
is the source terminal of ATx. Due to the voltage divid-
ing action of the channel resistance of ATx ðRATx Þ and
RMTJ , the voltage of the source terminal of ATx ðVS Þ is in
the range 0 G VS G VDD . Hence, VGS G VDD , leading to a
source degenerated ATx [72]. For proper memory opera-
tion, the bit-cell must be designed to satisfy write failure
requirements for both writing a “0” and writing a “1.”
When the “bottom-pinned” STT-MRAM bit-cell is de-
signed to satisfy the write failure rate for writing a “1,”
there may be excessive IWR flowing through the bit-cell
when writing a “0.” Hence, the reliability of the tunnel
oxide in the MTJ may severely degrade, and excessive
write power may dissipate. Furthermore, the source de-
generation problem may be exacerbated by the asymme-
try in IC of the MTJ. Asymmetry in IC has been observed
in several experiments [33], [58], [73]–[75] and may be
explained in terms of the dependence of spin-
polarization efficiency on the direction of current flow
[76], [77]. A “top-pinned” or “reverse-connected” STT-
MRAM bit-cell, shown in Fig. 3, was proposed to miti-
gate the source degeneration problem [34], [58]–[60].
However, source degeneration is still unavoidable as
Fig. 3 illustrates. Furthermore, the source degeneration
effect becomes more pronounced when the switching
voltage for the MTJ ðIC  RMTJ Þ is increased. Conse-
quently, the source degeneration effect can become a
serious issue when designing high-performance STT-
MRAM with large RMTJ (such as when the MTJ cross-
sectional area is scaled down).
Various research efforts have addressed the aforemen-
tioned design challenges at various levels of design ab-
straction. In the following sections, we present an
extensive survey of the research work that addresses
STT-MRAM design issues at the device, circuit, and
memory architecture levels.
1456 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
V. IMPROVING STT-MRAM AS THE
S T O RA G E DE VI CE
The MTJ stack may be designed to mitigate the design is-
sues in STT-MRAM, which were discussed earlier. In
this section, we will first look at the proposed improve-
ments to the two-terminal MTJ stacks and discuss their
advantages and limitations. This motivates our discussion
on multiterminal MTJ structures, which have most of
the advantages of two-terminal MTJ stacks while over-
coming most of their limitations. We then present sev-
eral physical phenomena that may be exploited to
improve STT-MRAM performance. We will also discuss
multilevel cells (MLCs), which potentially increase inte-
gration density while amortizing the cost per bit. Design
issues of MLCs are also discussed.
A. Improving the Conventional MTJ Stack
As we have discussed earlier, the stray field from the
PL of the MTJ may give rise to asymmetry in EB and IC
of the FL in the MTJ. Note that the PL of the MTJ can
be replaced with a synthetic anti-ferromagnet (SAF)
structure [78]–[80] to reduce the stray field from the PL.
Reducing IC is also highly desirable for improving the
endurance, the reliability, and the write energy con-
sumption. From (10), it is clear that IC may be reduced
by increasing the spin-polarization efficiency  or by re-
ducing the damping factor  or the barrier height EB .
EB is determined by application requirements and is
expected to be equivalent to 10 years retention time for
most memory applications.  may be improved by re-
placing the PL and FL of the MTJ with half-metallic
Heusler alloys in which all conduction electrons are
spin-polarized in one direction. Improved  may also
lead to improved MR ratio [16]. However, it was found
that interfacial states play an important role and may
degrade the MR ratio [17].
An alternative approach to reduce IC is to reduce the
damping factor,  of the FL of the MTJ [23]. Further-
more, the variance of H Thermal is proportional to  as (12)
shows. Thus, reducing  also has the desirable effect of
reducing the variation in IC due to thermal fluctuations
in the FL magnetization. Experimental measurements
[81]–[84] suggest that  of the FL depends on the
thickness of the layer. Note, however, it is challenging
to optimize the thickness of the FL layer to reduce 
while ensuring that other magnetic properties are main-
tained. It has been shown that  can be enhanced with
spin-pumping effect at the interface of FL with the
neighboring capping/seed layer [85]. Insertion of a spin
barrier between FL and the neighboring capping/seed
layer suppresses the spin-pumping effect and may re-
duce  [86]. In the CoFeB/MgO/CoFeB-based MTJ with
interfacial PMA, sandwiching a CoFeB free layer be-
tween MgO layers also increases the strength of interfa-
cial PMA [86], [87]. The desirable effect in such a
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

stack is that thermal stability can be increased without

increase in IC [86].
Other improvements to the MTJ stack have also
been conceptually proposed in the literature. Some of
these structures have been experimentally demonstrated
as well. The following sections present several alterna-
tive MTJ structures that are suitable for memory
applications.

B. Alternative Two-Terminal Devices

Four types of two-terminal MTJ structures for im-
proving the standard STT-MRAM bit-cell were investi-
gated in [88]. These structures may be classified as
single-barrier and double-barrier structures, where the
double-barrier structure consists of two PLs and tunnel-
ing barriers as shown in Fig. 4. The double-barrier struc-
ture enhances the spin filtering effect and results in a
lower IC as compared to the single-barrier MTJ structure
[88]. Note that the PLs in double-barrier structures are
anti-parallel to each other, and since the easy axis of the
FL is collinear with that of the PL, the FL will be parallel
to one of the PLs. If the thicknesses of both tunneling
barriers are the same, the resistance of the double-
barrier structure will be the same regardless of whether
FL is parallel to the top PL or to the bottom PL. Hence,
the thicknesses of the tunneling barriers must be differ-
ent so that the state of the FL may be electrically
distinguished.
The device structures in Fig. 4 may be further clas-
sified into structures with and without synthetic anti-
ferromagnetic FL (SAFF). The SAFF structure consists
of a pair of magnetically coupled ferromagnetic (FM) Fig. 4. Two terminal MTJ stacks that have been proposed in the
literature include (a) the single- and double-barrier stacks,
layers sandwiching a thin paramagnetic (Ru) layer. The
which may have ferromagnetic free layer or synthetic
anti-ferromagnetic (AFM) coupling between FM layers in anti-ferromagnetic free layer, and (b) the MTJ with tilted
SAFF increases the immunity of each FM layer to thermal magnetic anisotropy or the orthogonal MTJ stack.
fluctuations. Furthermore, the IC of SAFF may not in-
crease even though its thermal stability is increased be-
cause each FM layer in the SAFF stack acts as a spin
polarizer for the other FM layer [88]. Consider the flow to thermal fluctuations [23], [89], [90]. When the PL and
of electrons from PL through the tunneling barrier and FL easy axes are close to collinear, the initial torque ex-
then through the SAFF structure. The spin direction of erted on the FL during switching, as given in (8), is very
electrons is initially aligned with the magnetization of small. The FL magnetization has to deviate sufficiently
PL. When they enter FL1, they exert torque on the mag- away from the easy axis before the spin-transfer torque is
netization of FL1 and their spin directions are flipped to able to switch it. To overcome this, MTJ with tilted mag-
the magnetization direction of FL1. The torque exerted netic anisotropy (TMA, Fig. 4), in which the easy axis of
aligns the magnetization of FL1 with that of PL. The elec- the PL is not collinear with that of the FL, was proposed
trons then enter FL2 through the Ru layer and exert tor- [90]. Thus, the initial torque exerted on the FL during
que on the magnetization of FL2. The torque exerted on switching is significantly increased, and the IC is reduced
the magnetization of FL2 aligns the magnetization of FL2 for a fixed switching time. Hence, the write energy per bit
with that of FL1. Hence, the spin torque exerted by the is also reduced. However, the technique may degrade the
electrons on one FL is opposite of that exerted on the MR ratio and, hence, the readability of the MTJ structure.
other FL. RMTJ is given by [91]

1) MTJ With Tilted Magnetic Anisotropy: It was observed

2RAP RP
that the STT-MRAM switching delay distribution in the RMTJ ¼ (17)
precession regime is determined by the initial angle due ðRAP þ RP Þ þ ðRAP  RP Þ cos 

Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1457

Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
where  is the angle between the FL and the PL magneti-
zations. Consider the magnetization of the FL ðmÞ as the
reference, which may be in þb z- or bz-directions. In MTJs
without TMA, the magnetization of PL ðmP Þ is fixed at
say þb z. Hence, m mP ¼ cos  ¼ þ1 or 1, and either
RMTJ ¼ RP or RMTJ ¼ RAP . In MTJs with TMA, mP is not
fixed at þbz or at b
z with respect to the FL magnetization.
Consider if mP is close to but not at þb z. Hence,
m mP G 1 when m ¼ þb z, and m mP 9  1 when
m ¼ b z. This means that in the MTJ with TMA, since
RMTJ 9 RP when m ¼ þb z and RMTJ G RAP when m ¼ b z,
the MR ratio is lower than that in MTJs without TMA.
Furthermore, the lower IC tightens the constraints on read
current to meet sensing speed and read-disturb failure
requirements.
2) Orthogonal MTJ Stack: The orthogonal MTJ stack is
another two-terminal structure that was proposed to re-
duce the IC of the MTJ stack without sacrificing its read-
ability [92]–[95]. The structure, as shown in Fig. 4,
consists of a free layer sandwiched between a tunneling
oxide layer and a metallic spacer layer (Cu). The easy
axis of PL1 is collinear with the easy axis of the FL,
whereas that of PL2 is perpendicular to the easy axis of
the FL. Two sources of torque are exerted on the FL
when current flows through the orthogonal MTJ stack.
Switching of the FL is initiated by the torque acting on
the FL due to PL2 , which is at its maximum initially.
Since PL2 is separated from the FL by a metallic spacer,
electrons passing between FL and PL2 are not strongly
spin-polarized. Hence, the torque exerted due to PL2 is
only able to destabilize the FL to initiate switching, but
unable to fully align the FL magnetization with that of
PL2 . Once the FL is destabilized, the torque exerted by
PL1 increases to a point it is able to align the FL magne-
tization with that of PL1 . Hence, the incubation and
switching delays of the orthogonal MTJ are shorter than
those of MTJs with IMA or PMA [94]. The resistance of
the orthogonal MTJ stack is dominated by the tunneling
resistance across the tunneling oxide barrier. Since the
easy axes of FL and PL1 are collinear, RMTJ is determined
by the relative magnetizations of FL and PL1 . Hence,
RMTJ  RP when m ¼ þb z and RMTJ  RAP when m ¼ b z,
and the degradation in MR ratio is negligible, unlike in
MTJs with TMA. However, just like in MTJs with TMA,
the reduced IC tightens the constraints on read current
to meet sensing speed and read-disturb failure
requirements.
3) Design Issues of STT-MRAM Based on Two-Terminal
Devices: The design of two-terminal spin devices requires
the bit-cell designer to trade off between write, retention,
read-decision, and read-disturb failures. For example, we
may want to reduce IC by reducing EB to improve write
failures. However, lowering EB also increases retention
failures and reduces the allowable IRD to meet read-
1458 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
Fig. 5. Sample of read currents through 104 bit-cells where the
voltage across each memory cell is VREAD . Bit-cell parameters
are shown in the table. Each point shows the read current for a
bit-cell when it is storing AP ðIREAD;AP Þ and when it is storing P
ðIREAD;P Þ normalized to the reference current, IREF . Bit-cells falling
below the red line and to the right of the magenta line cannot be
correctly sensed by the sense amplifier. Self-referencing read
schemes that leverage the correlation of IREAD;AP and IREAD;P are
needed to reduce sensing failures.
disturb failure requirements. A lower IRD may limit the
maximum achievable sensing performance. Alternatively,
tMgO can be reduced to achieve higher IWR . However, re-
duction in tMgO reduces the MR ratio of the MTJ and,
hence, degrades the distinguishability of the bit-cell as
well as the reliability of the tunneling oxide [14], [37].
These design tradeoffs arise because the read and write
current paths are shared in two-terminal STT-MRAM
devices.
The two-terminal nature of the aforementioned STT-
MRAM devices also leads to challenging design issues at
the circuit level. One of the design issues is the source
degeneration problem discussed in Section IV-B. The
single-ended nature of sensing operations is another
critical design issue in STT-MRAM. Consider the scatter
plot shown in Fig. 5, where each point corresponds to
the read current of an STT-MRAM bit-cell when it stores
LRS and when it stores HRS. In single-ended current
sensing, data stored in the STT-MRAM bit-cell is sensed
by comparing the read current through the bit-cell to
IREF as discussed earlier. The cells falling to the right of
the vertical magenta line will always be sensed as LRS or
“0,” and those cells falling below the horizontal red line
will always be sensed as HRS or “1.” Although IREF may
be carefully chosen to minimize sensing failures, sensing
failures may not be completely eliminated unless the
read currents between “0” and “1” are sufficiently sepa-
rated (i.e., a larger MR ratio is needed to compensate for
higher process variations). One way to mitigate this
problem in single-ended sensing is to employ self-
referencing [31], [96]. Self-referencing allows the sensing
scheme to exploit correlations in the bit-cell read cur-
rents to reduce sensing failures. However, as we will dis-
cuss in Section VI-G, self-referenced single-ended
sensing may become ineffective in future STT-MRAM.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 6. DPMTJ-based STT-MRAM bit-cell proposed (a) in [97] and (b) in [98]. (c) Write operations require write current ðIWR Þ through
the write port, whereas (d) read operations occur by passing read current ðIRD Þ through the read port.
Furthermore, complementary data are not available in
every bit-cell and, hence, differential sensing cannot be
used. Unlike single-ended sensing, differential sensing is
able to achieve faster read operation due to larger sens-
ing margins enabled by storing complementary data. An
STT-MRAM design that enables differential sensing is
presented in Section VI-F. However, they are not self-
referencing since separate MTJs are used to store comple-
mentary data. As a result, process variations can lead to
significant read-decision failures. Hence, the lack of vari-
ation tolerant self-referenced differential sensing limits
the readability of two-terminal STT-MRAM devices.
Since the key obstacle is the two-terminal nature of
the STT-MRAM devices, multiterminal devices that are
able to mitigate the read/write stability conflicts have
been proposed. As we will see in the following sections,
STT-MRAM bit-cells based on multiterminal devices may
require multiple access transistors. However, the re-
quirements on the sizing of the access transistors for
multiterminal devices are significantly relaxed. Hence,
the bit-cell layout area for multiterminal devices can be
smaller than those based on two-terminal devices despite
the need for multiple access transistors per bit-cell.
In Section V-C, we explore different genres of multiter-
minal devices and show how they are able to mitigate or
completely avoid the design issues in two-terminal STT-
MRAM devices.
C. Multiterminal Devices
Multiterminal devices mitigate the aforementioned
design issues by decoupling read/write current paths
[97]–[101], avoiding the source degeneration problem
and enabling self-referenced differential sensing opera-
tions [102]–[105].
1) Dual-Pillar MTJ Structure (DPMTJ): Fig. 6 illustrates
the DPMTJ proposed in [97]–[99]. A key feature of the
proposed DPMTJs is that they have separate ports for
read and write.
DPMTJ proposed in [97] looks like a spin-valve and a
tunneling junction with a shared free layer as Fig. 6(a)
shows. It has a single free layer in contact with two me-
tallic contacts (one of which is Cu while the other is
Cr/Au) on the top and a tunneling oxide barrier on the
bottom. A pinned layer sits below the tunneling oxide,
and another pinned layer sits on top of the Cu contact.
Write operations require sufficient current through the
low-resistance path between the Cr/Au electrode and
the spin-valve structure. Read operations involve sensing
current through the high-resistance path between the
Cr/Au electrode and the tunneling junction.
Since the DPMTJ in [97] uses a spin-valve in the write
current path, the spin-polarization efficiency of the write
current is low. Hence, an alternative DPMTJ structure,
which uses a tunnel junction in the write current path,
shown in Fig. 6(b), was proposed [98], [99]. The read and
write operations occur instead by passing current between
BL and RSL and between BL and WSL, respectively.
A key advantage of DPMTJ structures is that their read
and write current paths are separate. Hence, the DPMTJs
may be optimized for read and for write independently.
The resistance of the write current path can be reduced to
mitigate the source degeneration problem discussed in
Section IV-B. This is achieved using a Cu spacer in [97],
and a thin tunnel oxide layer for the write port in [98].
The distinguishability of the stored states in the DPMTJ
can be improved by increasing the thickness of the tun-
nel oxide layer in the read ports shown in Fig. 6. This
may also reduce the amount of read current needed for
sensing the stored state, which helps reduce read disturb
failures. Another advantage of DPMTJ is that the high
write current never flows through the tunnel oxide used
for sensing the DPMTJ state. Hence, the reliability of the
tunnel oxide for sensing the stored state is significantly
improved.
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Fig. 7. DWMTJ state is (a) represented by the magnetization of

the region just under the read port. (b) Read and write current
paths are decoupled just like in the DPMTJ.

2) Domain-Wall-Based MTJ (DWMTJ) as Storage Ele-

ment: The DWMTJ structure is another multiterminal
MTJ structure that has been proposed (Fig. 7) [100],
[101]. It consists of a domain-wall stripe with comple-
mentary polarized pinned layers at the ends (i.e., the
pinned layer magnetizations are completely opposite)
and a free region between the pinned layers. A tunnel
oxide is deposited on top of the free region followed by
another pinned layer.
The current paths for read and write operations are
shown in Fig. 7(b). Write operations require sufficient
current between BL and WSL, whereas read operations
occur by passing current between RSL and BL through
the tunnel oxide. DWMTJ has all the advantages of the Fig. 8. CPMTJ-based STT-MRAM bit-cell using PMA ferromagnetic
DPMTJ—separation of read and write current paths, low layers proposed (a) in [102] and (b) in [103]. (c) Write operations
resistance in write current path to mitigate source degen- occur by steering write current through the complementary
eration, improved distinguishability, read disturb failure, pinned layers via either SLL or SLR. (d) Read operation requires
read currents, IREAD , through both pinned layers and comparing
and tunnel oxide reliability. However, the read opera-
them to determine the state of the stored data.
tions of DPMTJ and DWMTJ are single-ended in nature.
Single-ended read operations sense data stored in multi-
ple cells by comparing with a common reference. The
reference needs to be carefully chosen to optimize sens- structure shown in Fig. 8 [102]–[105]. CPMTJ is similar
ing failures in the presence of process variations. Read to DPMTJ in that they look like two tunnel junctions
operations that use self-referenced differential sensing with a shared free layer. In CPMTJ, the magnetizations
does not require a common reference, and hence are of the pinned layers are complementary. As Fig. 8(c)
more robust than read operations using single-ended shows, write operations require sufficient write current
sensing. A multiterminal MTJ structure that enables self- from BL to either SLL or SLR. Hence, the free-layer
referenced differential sensing for read operations while magnetization is always parallelized with the magnetiza-
preserving most advantages of DPMTJ and DWMTJ is tion of one of the pinned layers. Read operations occur
presented next. by first applying a common voltage to SLL and SLR and
another voltage to BL. The respective currents flowing
3) Complementary Polarizer MTJ (CPMTJ): Another fla- through SLL and SLR are different since the free-layer
vor of multiterminal MTJ structure is the CPMTJ magnetization is parallel to one pinned layer and

1460 Proceedings of the IEEE | Vol. 104, No. 7, July 2016

 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
anti-parallel to the other. Hence, the FL magnetization
may be sensed by comparing the respective currents
flowing through SLL and SLR.
CPMTJ completely avoids source degeneration and
uses only the parallelizing of FL with PL for write op-
erations. Note that such parallelizing operation usually
requires lower IC . Thus, the write power is optimized.
The read operation is also variation-tolerant due to the
self-referencing and differential nature of sensing. Fur-
thermore, latch-based sense amplifiers may be used for
sensing the state of CPMTJ, which improves sensing de-
lay. Reduction in sensing delay also reduces read-disturb
failures.
Although the multiterminal devices presented in this
section mitigate design issues in STT-MRAM by decou-
pling read and write current paths, or avoiding source
degeneration and enabling self-referencing differential
read operations, the write currents are still driven
through a tunneling oxide. Hence, the voltage required
to supply the required IC may still be quite high. This
may lead to reliability issues with the tunnel oxide
barrier in the write current path. Also, the inability to
reduce the voltage needed for write means the write en-
ergy consumption remains relatively high. In the follow-
ing sections, we will present some of the new physical
mechanisms for STT-MRAM write operations, which
may achieve much lower write energy either by reducing
the resistance along the write current path or by elimi-
nating the need for write current.
D. Alternate Physics
As mentioned earlier, the high write energy of two-
terminal STT-MRAM poses a significant design chal-
lenge. Several experiments have revealed new physics
that may be exploited to overcome this design issue. In
this section, we will discuss three of these experiments
and consider STT-MRAM bit-cells that exploit these
physical phenomena.
1) Nonlocal Spin-Transfer Torque: When current flows
between an injector ferromagnetic contact to ground in a
lateral spin valve (LSV) as shown in Fig. 9, one would
expect that the open-circuit voltage, VO , on the detector
ferromagnetic contact is the same as the channel since
no electrical current is being driven through the detec-
tor. However, the experiments in [106] and [107] show
that VO depends on the magnetization direction of the
detector relative to that of the injector. It was further
shown in [106] that at low temperatures, the magnetiza-
tion of the detector may be switched if sufficient current
is injected via the injector. However, the magnitude of
switching current in [106] is insufficient to generate
magnetic fields large enough to switch the detector mag-
netization. It has been theorized that the injection of
charge current into the channel results in a spin accumu-
lation in the channel underneath the injector [108]. The
Fig. 9. (a) Nonlocal spin torque effect was observed in the LSVs.
Injection of charge current via the injection port modulates
the open circuit voltage at the detector port. (b) Nonlocal
spin-transfer torque (NLSTT) MRAM is based on the LSV.
The read current path ðIREAD Þ is separate from the write
current ðICHARGE Þ path.
ferromagnetic nature of the injector filters the spins of
electrons that make up the charge current. When elec-
trons are injected into the channel via the injector, there
is an accumulation of electrons with spin in the same di-
rection as the injector magnetization. Similarly, when
the direction of electron flow is reversed, electrons with
spin in the same direction as the injector are removed
from the channel, leaving an excess of electrons with op-
posite spin. Along the channel, the difference in spin
population decays when measured further and further
away from the injector, which may be modeled as a spin
potential. Valet and Fert modeled the transport of up-
spin and down-spin electrons using the drift-diffusion
equation [108]. It can then be shown that the aforemen-
tioned phenomenon leads to the injection of spin currents
ðI SPIN Þ in the channel, which do not have to coincide
with the direction of charge current flow. The spin cur-
rent interacts with the detector and can exert a nonlocal
spin-transfer torque on its magnetization.
The nonlocal spin-transfer torque MRAM (NLSTT-
MRAM) shown in Fig. 9(b) exploits nonlocal spin-
transfer torque for programming the free layer [109],
[110]. Like DPMTJ, the read and write current paths are
separate as illustrated by Fig. 9(c). The write current
flows between PL0 and PL1 through the metallic channel.
The metallic nature of the write current path effectively
mitigates the source degeneration of the write access
transistor. Consider the case when the write current is
flowing from PL1 to the PL0. Majority of the electrons
Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1461
Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
injected into the metallic channel are spin-aligned with
the magnetization of PL0. Furthermore, electrons that
have spin-aligned with the magnetization of PL1 are easily
removed from the metallic channel. As a result, there is a
large concentration of electrons with spins that are
aligned with the magnetization of PL0. This results in a
large gradient in the concentration of each spin species if
the FL magnetization is aligned with that of PL1. As dis-
cussed previously, this concentration gradient leads to
spin diffusion that has zero charge current flow but a net
spin current flow. The spin current is absorbed by FL,
and a nonlocal spin torque is exerted on FL that aligns its
magnetization with that of PL0. Reversal of the current
direction between PL0 and PL1 reverses the direction in
which the magnetization of FL switches. The magnetiza-
tion of FL is sensed by passing a small read current
through the tunnel junction formed by FL and PL2, as
shown by Fig. 9(d), just as in the read operation of the
1T-1MTJ STT-MRAM bit-cell.
In order to achieve low write energy in NLSTT-
MRAM, one must ensure that the charge to spin current
conversion is sufficiently strong. This requires sufficiently
strong spin filtering effect at the interfaces between PL1
and PL0 with the nonmagnetic metallic channel. Also,
spin scattering effects in the nonmagnetic metallic chan-
nel need to be minimized. These two issues are key in en-
suring that the ratio of majority electron spin to minority
electron spin in the nonmagnetic metallic channel is high
enough, which is required for efficient charge to spin
current conversion and low write energy.
2) Spin-Orbit Torque: Unlike the spin torques discussed
earlier, spin-orbit interaction (SOI) can be much more
efficient at generating spin current from charge current.
For example, it was recently found that spin-orbit torque
(SOT) is exerted on a ferromagnet (FM) deposited on a
heavy metal (HM) when charge current is passed
through the HM layer [111]–[113]. Two possible origins
of SOT are the Rashba field due to structural inversion
asymmetry in FM/HM interfaces [114]–[120] and the
spin Hall effect (SHE) in HM [116], [120], [121]. In the
case of SHE, the spin current flow generated is orthogo-
nal to the current flow, and the spin direction of the
electrons is orthogonal to the direction of spin current
and charge current flow. The spin current may be in-
jected into FM just like in NLSTT. HMs such as -Ta
[111], -W [122], and Pt [123] have been identified as
candidate materials that may be used to generate spin
current via SHE.
Spin current due to SHE may be understood by consid-
ering the illustration in Fig. 10(a). When charge current
flows in HM, SOI causes the accumulation of one type of
electron spin on one surface of HM, whereas the electrons
of the opposite spin accumulate on the opposite surface.
Note that the accumulation is orthogonal to charge cur-
rent flow. SHE generates a spin current that can be
1462 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
Fig. 10. (a) Spin Hall effect, where the electron spin and
magnetization directions of magnetic layers are shown. (b) Basic
SOT-MRAM cell with the magnetization arrows drawn for clarity.
Note that the read and write current paths are also decoupled.
(c) SOT-MRAM bit-cell uses a pair of MTJs to store
complementary data and enable self-referenced differential
read operations.
absorbed by the FL and exerts a torque on the FL magneti-
zation. However, electrons that enter HM from FL experi-
ence strong spin-scattering upon entry. Being close to the
FM/HM interface, these electrons may enter FL after scat-
tering. Fig. 10(a) shows that an electron from FL may
spin-scatter into the opposite spin and go back into FL.
Furthermore, the process can repeat many times along the
direction of charge current flow, and hence, the same
electron can transfer many units of angular momentum to
FL. Thus, the ratio of spin current injected into FM to the
charge current flowing through HM may be significantly
larger than 1 (this ratio is equivalent to the spin-polarization
efficiency in the spin torques exploited in the structures
discussed in Section V-B and C). Hence, materials with
large SOI provide a means to reduce the write energy of
STT-MRAM by enhancing the efficiency of spin current
generation.
The basic structure of the spin-orbit torque MRAM
(SOT-MRAM) is shown in Fig. 10(b) [111], [124]. It con-
sists of an MTJ with its free layer in contact with the HM.
Note that the FM has IMA so that it may be switched using
SOT. However, techniques have been proposed to enable
switching of MTJs with PMA using SOT [125]–[127]. In
Fig. 10, the current flows in the x-direction. The direction
of spins injected into FL is either in þy- or y-direction
depending on the sign of spin Hall angle and direction of
current flow in the HM. Hence, write operations are per-
formed by passing current through the HM. The state of
the MTJ is sensed by the read current through the MTJ as
shown in Fig. 10(b). Note that the reliability of the MTJ is
improved since small read current flows across the tunnel-
ing oxide only during read operations.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Since electron spins accumulate on both sides of the
HM, a pair of MTJs may be switched by the same write
current. Fig. 10(c) shows a memory bit-cell with two
MTJs. In such a bit-cell, the read operation compares
IRD;R to IRD;L so as to determine the stored state, thus en-
abling differential read operation.
Note that SOT may also be used to reduce the write
current of other MTJ structures, such as the DWMTJ
structure discussed in Section V-C.2. A Co domain wall
stripe grown on Pt and capped with AlOx was investi-
gated in [113]. The results corroborate the theory that
the current density needed to move the domain wall in
such multilayers with an HM underlayer is much lower
than without the HM layer [128]–[130]. Furthermore,
the dependence of the domain wall velocity on the direc-
tion of current flow depends on the choice of HM [131].
3) Voltage-Controlled Magnetic Anisotropy (VCMA): It
was experimentally observed that the free layer in a
Ta/CoFeB/MgO/CoFeB/Ta MTJ stack may be switched
by an applied voltage in the presence of a magnetic field
[132]. Furthermore, the current density through the MTJ
at the switching voltage is about 1:2  102 A=cm2 , which
is much smaller than predicted by the Slonczewski
model of spin-transfer torque. Further investigation
found that the magnetic anisotropy field of the MTJ is
modulated by the electric field due to the applied voltage
[133]. Note that the effect was only observed in MTJs in
which the PMA effect is due to interfacial effects at the
oxide-ferromagnet interface [132]. Furthermore, since
the applied electric field only modulates the magnetic an-
isotropy of the ferromagnet, a magnetic field is needed to
deterministically switch the MTJ. This may pose a prob-
lem in dense STT-MRAM arrays where stray fields from
nearby ferromagnetic layers may affect the switching.
4) Strain-Induced Magnetization Change: An alternative
scheme to achieve voltage control of magnetization
without the need for an applied magnetic field uses
strain-induced magnetization reversal [134]–[138]. Some
magnetic materials exhibit the inverse magnetostriction
effect [134], whereby stresses applied to the material
change its atomic structure, which determines the easy
axes of the magnetic material. Since the lattice structure
of piezoelectric materials such as lead-zirconate-titanate
(PZT) may be modulated by an electric field, direct cou-
pling of piezoelectric materials to magnetic materials ex-
hibit inverse magnetostriction effect, enabling voltage
control of magnetization without the need of an applied
magnetic field. Thus, a magnetic storage element exploit-
ing this mechanism may be implemented as an MTJ with
its FL adjacent to a piezoelectric material. The FL mate-
rial needs to exhibit the inverse magnetostriction effect,
and the interface of FL with the tunneling oxide barrier
needs to be engineered to provide good MR ratio. How-
ever, the induced strain only rotates the easy axis of the
magnetic material but not the alignment of its magneti-
zation along the easy axis [134]–[138]. A separate mecha-
nism is required to switch the MTJ between P and AP
configurations. Several proposals that exploit this mecha-
nism for memory applications achieve the desired
switching of the MTJ state by using the strain as an assist
for spin-transfer torque [138] or for current-induced do-
main wall motion [136]. However, it remains unclear
whether the integration of such MTJ structures into the
back-end-of-line (BEOL) of the CMOS fabrication pro-
cess severely degrades the efficacy of strain transfer be-
tween the piezoelectric and magnetic materials.
Nevertheless, the control of magnetization using voltage-
controlled strain is promising for achieving ultra-low
write energy STT-MRAM.
E. Multilevel Cells
The integration density of STT-MRAM may be in-
creased by storing multiple bits in each memory bit-cell.
This may be achieved by including two or more MTJs in
each bit-cell [139]–[142]. The single MTJ in the single-
level cell (SLC)-type STT-MRAM may be replaced by se-
ries or parallel connections of two MTJs, as shown in
Fig. 11, to implement MLC. Each MTJ stores 1 bit of
data, and the structures shown in Fig. 11 enable each
MLC to store 2 bits. However, the dimensions of the
MTJs are deliberately different so that four resistance
states may be achieved. Just as in the SLC, either voltage
or current sensing may be used to determine its resis-
tance state.
The write operation of MLC STT-MRAM is more
complicated than its SLC counterpart. First, the MTJs in
MLC are engineered such that they have different IC ’s.
Consider the operation to store “01.” The MTJ with the
larger IC is programmed first (storing “0” in Fig. 11).
The MTJ with the smaller IC is then programmed in
the second step. Note that the write latency of MLC is
data-dependent and can be larger than that in SLC.
When the MTJ with the larger IC is being written into,
the other MTJ is also written. The write operation may
be terminated after the first step if the final state of both
MTJs matches the data that is to be stored into them.
Otherwise, a second write step is needed to correctly
program the MTJ with the smaller IC .
The MLC bit-cells suffer from the same failures as
their SLC counterpart. In addition, write disturb failure
may occur when the direction of write current needs to
be reversed to program the MLC bit-cell. When the MTJ
with the smaller IC is being programmed in the second
write step, current also flows through the other MTJ and
may overwrite its state, which was programmed in the
first write step. Hence, MLC STT-MRAM needs to be
carefully designed to mitigate write disturb failures.
Moreover, the resistance difference between states needs
to be large enough so that the sensing circuitry is able to
distinguish all four states.
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 11. MLC STT-MRAM bit-cells based on (a) series connection of MTJs, called S-MLC, and on (b) parallel connection of MTJs called
P-MLC. In the first write step, large write current ðIWR Þ is driven through the bit-cell so that identical data are written to both MTJs.
If the data to be written to each bit are different, the second write step is initiated, driving a small write current to write the MTJ
with the smaller IC .
1) Racetrack Memory: Racetrack memory (RTM), pro-
posed in 2008 by IBM, is an MLC based on the domain
wall (DW) physics discussed in Section V-C.2 [143]. Its
key advantage is extreme integration density. It consists
of a write port, a read port, a shift port, and a long do-
main wall stripe, in which DWs are formed to separate
magnetic domains of opposite magnetizations (Fig. 12).
The domain wall stripe (DWS) is segmented so that each
segment has a uniform magnetization, which represents
the data bit stored. A DW is present between neighbor-
ing segments with opposite magnetization directions.
Notches may be used to create regions of strong pinning
potential along the DWS so that DWs can be stabilized
[144]. Neighboring segments store data bits that are
Fig. 12. Schematic diagrams of racetrack memory programmed
using (a) magnetic field and (b) STT. The magnetization of each
segment stores 1 bit of data and DW form between segments
with opposite magnetization. Segments with different colors
have opposite magnetization. SHFT port allows bits to be shifted
in and out of the read and write ports, which are accessed via
RSL and RWL, and WSL, WWL, and WBL, respectively. An MTJ in
the read port allows data to be read out.
1464 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
logically opposite (identical) if a DW is present (absent)
between them.
The write port of the racetrack memory consists of a
nano-wire that overlaps and runs perpendicular to the
domain wall stripe. A current pulse injected through the
write port generates a localized magnetic field, H WR ,
that manipulates the magnetization of the segment of the
DWS overlapping the write port. Alternatively, an MTJ
may also be used to inject spin-polarized electrons into
the DWS so as to manipulate the magnetization of the
segment using STT. A DW may be created or annihilated
at the boundaries of the segment during the writing pro-
cess. On the other hand, the read port consists of an
MTJ formed using a PL, a tunnel oxide, and one segment
of the DWS as shown in Fig. 12. Hence, the resistance of
the read port depends on the magnetic configuration of
the MTJ.
In RTM, the memory address of the data stored in
each segment of the DWS is variable. A shift port placed
at the ends of the DWS controls the sequential shifting
of data bits into and out of the read and write ports.
Current injected through the shift port moves DWs along
the DWS using the STT effect. The number of data bits
that can be stored in the DWS depends on its length. If
vertical integration is possible, large numbers of bits may
be stored in each DWS. Furthermore, only three ATx’s
are needed per RTM bit-cell, and extreme integration
density may be achieved.
An important design issue in RTM is that under pro-
cess variations, it may be very difficult to uniformly
control the motion of all DWs in the DWS [143]. The
functionality of RTM depends on the ability to shift
DWs in unison. Consider the case when a DW is being
shifted in a PMA-type DWS as shown in Fig. 13(a).
Assume that the pinning potential at B is increased due
to process variations. Hence, the shift current needed to
dislodge DW from B is much larger than usual. When
DWs are being shifted in the direction shown by
Fig. 13(a), the separation between DWs is decreased.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 13. Shifting of DWs along a DWS can result in unintentional
(a) annihilation and (b) creation of stored data bits.
Hence, 1 bit of data in the DWS is annihilated. Now con-
sider the case when the direction of DW shifting is re-
versed as shown in Fig. 13(b). The DW at B is too
strongly pinned and remains pinned while the other do-
main wall shifts to A. Since the separation between the
DWs has increased, a logical data bit has been uninten-
tionally created in the DWS. Since the creation and anni-
hilation process can occur simultaneously at multiple
sites within a DWS, the data stored in an RTM bit-cell
may be corrupted during shift operations. Furthermore,
the problem is exacerbated by the fact that the relation-
ship between DW velocity and shift current depends on
many factors [144]–[147]. Moreover, access to individual
memory locations requires the shifting of DWs so that
the corresponding memory location is shifted into the
read port. This requires additional hardware and also in-
troduces variable access latency to RTM accesses.
2) Spin-Orbit Torque-Based MLC: Just as in the SLC
case discussed earlier, spin-orbit torque may be exploited
to reduce the write energy in MLC STT-MRAM. Two
Fig. 14. (a) MLC storage elements using SOT, (b) equivalent circuit network modeling of the storage elements, (c) bit-cell schematics,
and (d) bit-cell bias conditions for read and write operations.
flavors of MLC SOT-MRAM were proposed in [148].
Similar to the MLC STT-MRAM discussed earlier, the
MLC SOT-MRAM may be designed with parallel or se-
ries connected MTJs (called P-MSOT and S-MSOT, re-
spectively) as shown in Fig. 14. Also, the MTJs are
designed with different IC ’s such that the stored states
may be sensed as distinct resistances [148]. A multistep
sensing operation may be needed to read out the data
stored in MLC SOT-MRAM.
Write operations in MLC SOT-MRAM are multistep
in nature just like in MLC STT-MRAM. In the P-MSOT
design, write current is passed through the heavy metal
(HM). Hence, low write energy may be achieved because:
1) the IC ’s are low due to efficient spin-orbit torque gen-
eration; and 2) the voltage needed to induce the write
current in HM is very low due to the high conductivity of
the write current path. In the S-MSOT design, HM is in
contact with the FL of only one of the two MTJs. Write
current needs to flow through the stack of MTJs and
through HM to program both MTJs. As a result, the write
energy may be significantly higher compared to the
P-MSOT design. However, the write current may be
passed through both current paths simultaneously to
achieve single-cycle latency write operation. Hence, the
P-MSOT design is more suitable for cache applications in
which low write energy is crucial, whereas the S-MSOT
design is more suitable for cache applications that require
fast write operations [148]. Furthermore, large write cur-
rents do not flow through the tunnel oxides in the P-SOT
design, which improves the reliability of the MTJs.
3) Multilevel Domain Wall Memory: MLC based on
DWMTJ may be implemented as illustrated in Fig. 15(a)
[149]. Compared to RTM, DWMTJ-based MLC uses two
read ports. Conceptually, its structure consists of three
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 15. (a) Conceptual design of MLC-type DWMTJ and its
corresponding write current path, and (b) a possible
implementation of MLC-type DWM and its corresponding write
current path.
pinned magnetic regions along the stripe: one at each
end of the stripe and one in the middle. The magnetiza-
tions of the pinned region at the ends are the same but
opposite to that of the pinned region in the middle of the
stripe. Note that this may be implemented by connecting
together the ends of two separate DWMTJs as shown in
Fig. 15(b). Data are stored as the location of the DWs
along the stripe(s), similar to the domain wall memory
(DWM) discussed in Section V-C.2. The geometry of the
domain wall stripes are engineered such that the IC ’s to
move the DW in each stripe are different. Also, the stripe
may be deposited on HM to reduce IC by exploiting SOT.
Data stored in MLC-DWM is read out as the resis-
tance formed by the read ports of the domain wall
stripes connected in parallel. Hence, the resistance of
each read port needs to be designed such that the stored
states in the MLC-DWM may be sensed as distinct resis-
tances [149]. The write operations of the MLC-DWM are
also multistep in nature. The cell is programmed by first
writing the bit with the larger IC followed by writing the
bit with the lower IC . The write steps are similar to those
in MLC STT-MRAM and MLC SOT-MRAM.
Compared to RTM, the integration density of
MLC-DWM is much lower, but the access latencies in
MLC-DWM are much more predictable. Furthermore,
additional peripheral circuitry is needed to track the
address of the memory bit in the read and write ports of
RTM. This is not needed in MLC-DWM since both bits
can be accessed simultaneously.
Before discussing circuit and architecture level design
techniques for improving STT-MRAM, let us briefly sum-
marize the STT-MRAM storage device design techniques
1466 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
presented in this section. Table 3 summarizes the key ad-
vantages and disadvantages of the design techniques for
improving the two-terminal MTJ stack. The two-terminal
nature of the MTJ stack is desirable for achieving arrays
with high bit density. The interfacial PMA-based MTJ
with dual MgO/FL interface is promising due to its
enhanced interfacial anisotropy and reduced , which
reduces write energy as well as the randomness of spin-
transfer torque switching. However, the two-terminal
nature of the MTJ does not resolve the conflicting re-
quirements for improving read and write operations.
Multiterminal STT-MRAM storage device structures such
as the DPMTJ, DWMTJ and CPMTJ were proposed to
alleviate this problem. However, the intrinsic IC may still
be high. Alternative physical mechanisms for program-
ming the MTJ, such as nonlocal spin-transfer torque
effect, spin-orbit torque effect, voltage-controlled mag-
netic anisotropy, and strain-induced magnetization
reversal, may be promising solutions for overcoming the
STT-MRAM storage device design issues. Finally, we
discussed multilevel cells, which amortize the implemen-
tation overhead among the total number of bits stored
per bit-cell. Large bit densities may be achievable by inte-
grating RTM in three dimensions. Note that some of these
techniques may be used in conjunction with others—such
as spin-orbit torque with current-induced domain wall
motion—to get improved performance.
VI. CIRCUIT TECHNIQUES FOR
IMPROVING S TT-MRAM
In Section V, various device design techniques were
discussed to address the challenges associated with STT-
MRAM. However, it may be costly and difficult to incor-
porate some of these device design modifications into the
fabrication process. Alternatively, circuit-level design
techniques may be used to alleviate some of the problems
described earlier. In this section, we will present several
circuit-level STT-MRAM design techniques. Some of
these techniques improve STT-MRAM by embedding new
functionality in the STT-MRAM array at near-zero cost.
The other design techniques discussed in this section op-
timize the STT-MRAM bit-cell topology and/or peripheral
circuitry to improve reliability. The attractiveness of
these techniques is that they may be cost-effective since
the basic MTJ structure is not modified. Let us first con-
sider some possibilities of unique functionality that can
be easily added to the STT-MRAM array.
A. Embedding New Functionality in
STT-MRAM Arrays
A unique characteristic of resistive RAM technology,
and especially STT-MRAM, is that the layout of the
memory array can be exploited to embed new function-
ality in the array. For example, an additional bit line
can be added into the STT-MRAM array at no layout
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Table 3 Summary of STT-MRAM Storage Device Design Techniques
area cost. The extra bit line can be utilized to embed
read-only memory (ROM) [150], [151]. In the following
sections, we will briefly discuss three proposals whereby
additional functionality is embedded in the STT-MRAM
array so that it may be used simultaneously as RAM
and as a functional block. The attractiveness of such an
approach is that by implementing the additional func-
tionality in the STT-MRAM array, the system-level cost
of adding the function may be significantly lowered.
1) Embedding Read-Only Memory in STT-MRAM: ROM
functionality may be embedded in an STT-MRAM array
by utilizing an additional bit line [150], [151]. RAM data
are stored as the magnetic configuration of the MTJ in
the bit-cell, whereas ROM data are stored as the connec-
tion of the bit-cell to one of the two available bit lines
(BL0 and BL1, see Fig. 16). If the bit-cell is connected to
BL0, the ROM data stored in it is “0,” and if the bit-cell
is connected to BL1, the ROM data stored in it is “1.”
The peripheral circuitry needs to be modified to support
both RAM and ROM functionality as shown in Fig. 16.
Referring to Fig. 17(a), a pair of pass transistors allow
BL0 and BL1 to be electrically connected for RAM opera-
tions, and electrically decoupled for ROM read opera-
tions. Also, a latch-based sense amplifier may be used to
sense the ROM data as Fig. 17(b) shows.
Note that the additional circuits do not need to con-
sume a significant amount of area. The pass transistors
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 16. Column of STT-MRAM array that has ROM embedded in
it. Additional peripheral circuits needed to support the ROM and
RAM functionality are also shown.
need to be sized so that sufficient current may flow
through the bit-cells during RAM operations. Also, the
sense amplifier for ROM read operations can be very
small due to the large sensing margin for ROM sensing.
As Fig. 17(b) shows, when ROM data are being read,
one of BL0 and BL1 will be floating while the other is
electrically connected to SL via the selected bit-cell.
Hence, the transistors in the ROM sense amplifier may
be minimum-sized. Since the array area increase due to
the additional transistors is aggregated among the bit-
cells connected to the same column, the area penalty is
negligible.
2) STT-MRAM-Based Physically Unclonable Function:
The variations in performance between STT-MRAM bit-
cells may also be exploited to implement a memory-based
Fig. 17. Current paths during (a) RAM operations and during (b)
ROM operations are controlled by the pass transistors as shown.
1468 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
physically unclonable function (MemPUF) [152]–[154].
The input and output of the MemPUF is called its
challenge and response, respectively. When a MemPUF is
presented with a challenge, it produces a chip-unique
response and hence may be used for hardware security
applications. A simple STT-MRAM-based MemPUF may
be implemented as follows. Ordinarily, the STT-MRAM
array functions as RAM. When MemPUF mode is re-
quired, data in the bit-cells selected by the challenge to
generate the response are first copied to a buffer stor-
age. The data in the bit-cells are then overwritten with
identical values. Next, the bit-cells are grouped in pairs.
The bits constituting the response are then generated by
comparing the resistances of the bit-cells in each group.
Due to process variations, the resistance of each bit-cell
is different from each other, and if pairing is done
properly, the result of the comparison in each group is
random between groups (also termed as the randomness
criterion). Since the process variation is unique for each
STT-MRAM array, the response to the challenge is un-
ique to the array (also termed as the uniqueness crite-
rion), and the response to the same challenge is expected
to be repeatable (also termed as the stability criterion).
Fig. 18(a) shows the schematic of an STT-MRAM array
that can also function as a MemPUF. The flowchart in
Fig. 18(b) illustrates the operation flow when the
MemPUF functionality is required.
Several design issues need to be overcome to fulfill
the randomness, uniqueness, and stability criteria for
STT-MRAM-based MemPUFs as discussed in [152]–
[154]. For example, read failures may cause stability is-
sues in an STT-MRAM-based MemPUF. An automatic
writeback scheme was proposed in [153] to improve the
stability of the STT-MRAM-based MemPUF. Interest-
ingly, the proposed MemPUF may also be implemented
in other nonvolatile memory technologies [152].
3) Generating Random Numbers Using STT-MRAM: The
stochastic nature of spin-transfer torque switching in
the MTJ may be used to generate random numbers
[155]–[159]. This is extremely useful not just as a secure
hardware primitive for cryptography and other hardware
security applications, but also for high performance com-
puting applications such as Monte Carlo analysis. Fig. 19
shows the flowchart for an STT-MRAM-based truly ran-
dom number generator (TRNG). In the STT-MRAM ar-
ray that can function as a TRNG, the write drivers are
designed so that the currents supplied to the bit-cells
during the RAM and the TRNG modes are different. In
the RAM mode, the current supplied is large enough so
that the state of the MTJ is deterministically pro-
grammed. When a random number is needed from the
array, the memory switches to the TRNG mode. Data in
a row of STT-MRAM bit-cells is first copied into a buffer
storage. Next, bit-cells in the row storing “0” and “1” are
stochastically overwritten with “1” and “0,” respectively.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 18. (a) Schematic showing how an STT-MRAM array
consisting of a data array and a reference array, which are
identical 1T-1M bit-cell arrays, may be used as a physically
unclonable function (PUF). (b) Flowchart shows how the PUF
functionality may be used without overwriting the data stored in
the STT-MRAM array.
The write current supplied during this time is such
that the probability of overwriting each MTJ is 50%.
After the stochastic write process has completed, the
state of the bit-cells is sensed to determine the random
number. Note that the write current giving exactly
50% probability of switching may be different for every
MTJ under process variations. Strong post-processing
[160]–[162] may be required to relax the design require-
ments on the write drivers while ensuring that the ran-
dom numbers generated by the STT-MRAM are of
sufficiently high quality.
B. Write Assist Techniques
As was shown in [63], the minimum achievable
layout area of STT-MRAM bit-cells may be limited by
the need to meet requirements for successful write oper-
ations. Hence, there is a need for write assist techniques
to improve the write-ability of STT-MRAM with minimal
impact on its readability. Write assist techniques with
Fig. 19. Flowchart illustrating how TRNG functionality may be
realized in an STT-MRAM array.
minimal impact on read failures have been proposed [64].
These techniques either increase the current flowing
through the bit-cell during write operations (write current,
IWR ), or reduce the critical switching current ðIC Þ of the
STT-MRAM bit-cell. IWR may be increased by: 1) increas-
ing the voltage applied to the word line; 2) increasing the
voltage difference between the bit line and the source line
of the bit-cell being written into; and 3) forward biasing
the body of the NMOS access transistor (Tx) to reduce its
threshold voltage, VTN [64]. On-chip current carrying wires
may also be used to generate magnetic fields that can re-
duce the IC of the MTJ [64].
1) Word Line Voltage Boosting: In some transistor tech-
nologies, the gate voltage may be boosted such that
VGS 9 VDD . For bit-cells implemented with such transis-
tor technologies, the word line voltage may be boosted
during write operations to lower the Tx resistance and
increase IWR [163]. In the “bottom-pinned” bit-cell
shown in Fig. 3, the MTJ in AP may have such a large re-
sistance that IWR through the bit-cell falls below IC . By
boosting the word line voltage, IWR can be increased.
This technique is also used to improve the write-ability
of high-performance SRAMs.
Boosting the word line voltage may degrade the reli-
ability of the access Tx. Since write operations in memory
occur infrequently, boosting the word line voltage during
write may have little impact on the reliability of the ac-
cess Tx. An issue with word line boosting in SRAM de-
sign is that SRAM cells in the unselected columns along
the same row are usually put in the half-select mode [164]
and may be susceptible to disturb failures if word line
boosting is implemented. However, STT-MRAMs do not
have such an issue since the bit and source lines of unse-
lected columns may be discharged to GND.
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
2) Transistor Body-Biasing: IWR may be increased
without increasing the width of the access Tx by lower-
ing the threshold voltage ðVT Þ of the Tx. This may be
achieved by applying a voltage to the body of the access
Tx. When interdie variation is the dominant component
of variation, a single bias to the NMOS body can be suffi-
cient in improving the failure probability of bit-cells on
the die. Forward biasing the Tx body may increase the
leakage currents in the cell, resulting in increased power
dissipation. The area penalty for implementing this tech-
nique comes only from circuitry for generation of body
bias and not from the bit-cells. Note, however, if the
body bias is also applied during read operations, the
read-disturb failures may increase. Finally, the effective-
ness of body-biasing to manipulate transistor threshold
voltage has decreased considerably in scaled CMOS tech-
nologies [165].
3) Write Voltage Boosting: As mentioned earlier, write
operations in STT-MRAM bit-cells require voltages to be
applied to the bit, source, and word lines. The word line
controls the gate of the access Tx and controls the cur-
rent flow through the bit-cell. When the access Tx is
turned on, the bit and source line voltages determine the
amount and direction of current flow through the bit-
cell. Hence, IWR may also be increased by increasing
jVBL  VSL j.
In order to implement the boosted jVBL  VSL j, an ad-
ditional voltage plane may be required along with voltage
level converters in the bit and source line drivers. Fur-
thermore, higher write voltage increases electrical stress
on the MgO barrier and may lead to reliability issues
[69], [166], [167]. As was mentioned in Section VI-B.1,
write operations might not occur frequently and, hence,
jVBL  VSL j may be boosted without significantly degrad-
ing the MgO reliability.
4) Applied External Magnetic Field: It was shown that
variations in switching delay of an MTJ may be due to
the thermal fluctuations that cause the magnetization
of the FL to become noncollinear with the magnetiza-
tion of the PL [89], [90]. When the FL and PL magne-
tizations are almost collinear, very little spin-transfer
torque is generated. Thermal fluctuations must perturb
the FL magnetization such that FL and PL magnetiza-
tions are less collinear in order for larger spin-transfer
torque to be generated when current flows through the
MTJ. Hence, there is an incubation delay before the
spin torque exerted on the FL becomes large enough
to switch the FL magnetization.
The incubation period may be reduced by applying a
small magnetic field that tilts the FL magnetization to-
wards its hard axis, as was proposed in [168]–[170].
Compared to Tx body biasing, word line voltage boost-
ing, and write voltage boosting techniques, where IWR is
increased and may degrade the reliability of the MTJ, the
1470 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
applied magnetic field effectively reduces the IC of the
MTJ. However, the strength of the magnetic field re-
quired depends on the critical field of the FL ðHC Þ,
which is given in (5) and (11) for MTJs with PMA and
IMA, respectively. Moreover, on-chip current carrying
wires are required to generate the assist magnetic field,
which may disturb other cells near the wire. Also, as was
found in [64], the timing of the assist magnetic field and
IWR is crucial in reducing IC .
C. Write Current Optimization in STT-MRAMs
As discussed in Section IV, an important design issue
to overcome in STT-MRAMs is the large IC . The stochas-
tic nature of spin-transfer torque switching and the
source degeneration problem exacerbate the problem.
Due to the need for bidirectional write currents, the
width of the access Tx needs to be sized such that the
currents flowing through the MTJ (whether flowing from
BL to SL or from SL to BL) during write operations meet
the corresponding IC . A larger write current needs to be
supplied to overcome the stochastic nature of spin-
transfer torque switching. The source degeneration issue
worsens write energy dissipation. Larger write current
also degrades the reliability of the tunneling oxide in the
MTJ, which is crucial for achieving high MR ratio.
One proposed circuit technique to optimize STT-
MRAM write current pulse is to turn off the pulse once
the write operation is complete [171], [172]. A “self-enable”
circuitry tracks the resistance of the STT-MRAM bit-cell
during write operations. Once the write operation to the
bit-cell is detected to be complete, the circuitry turns off
the write driver. Hence, “just enough” write current is sup-
plied to write data into the STT-MRAM bit-cell.
Alternatively, the write current flowing through the
STT-MRAM bit-cell may be optimized by controlling
VBL  VSL so that just enough current flows from BL to
SL and from SL to BL during write operations. However,
an additional voltage plane may be required. We next
discuss two alternative circuit design techniques that
were proposed in [173] to optimize the write current in
STT-MRAMs.
1) Bit Line Voltage Clamping: The conventional write
drivers in STT-MRAM may use transmission gates to
drive the bit and source lines as shown in Fig. 20. Trans-
mission gates allow the bit and source lines to be driven
close to VDD and to GND. However, write operations re-
quire only the source line to be strongly driven to VDD or
GND. The bit line may be driven to a voltage smaller
than VDD to save write energy. Since VSL is driven to
GND when current flows from BL to SL, the current
flow may be limited by ensuring that VBL is not fully
driven to VDD . This may be achieved by driving the bit
line using a pass Tx instead of a transmission gate (Fig. 20).
Source degeneration of the pass Tx is exploited to limit the
current flow from BL to SL [173]. When current flows from
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Fig. 20. By eliminating the PMOS transistor in the transmission

gate within the bit-line write driver, (a) the bit-line voltage may
still be pulled to GND when current is being passed from SL to BL.
(b) Source degeneration of the pass transistor within the bit-line
write driver may be used to limit the write current and save
write energy.

SL to BL, the pass Tx is not source degenerated, and maxi-

mum write current flows.

2) 2T-1MTJ STT-MRAM Bit-Cell With Dual Source Lines:

Another method to limit the write current flowing
through the MTJ is to use a 2T-1MTJ STT-MRAM bit-cell
topology with dual source lines (Fig. 21). The voltages of
BL, SL1, and WL for write operations are identical to
those of BL, SL, and WL, respectively, of the 1T-1MTJ
STT-MRAM bit-cell topology. When maximum write cur-
rent is required to flow through the MTJ, the voltage of
SL2 is the same as that of SL1. When the current flowing
through the MTJ needs to be limited, the voltage of SL2
is complementary to that of SL1 as Fig. 21 shows. As
Fig. 22. (a) STT-MRAM array is rearranged in (b) the
[173] explains, the transistor M2 serves as a bypass tran- common-source-line scheme so that every column only has its
sistor to limit the write current flowing through the MTJ. own bit line. (c) Timing of the write operation needs to be
modified to occur in two steps. Low and high voltage levels
D. Common-Source-Line and Balanced correspond to GND and VDD , respectively.

Write Design
A 1T-1MTJ STT-MRAM array is usually designed
such that the word line used to control the access Tx of
the bit-cells is shared across the row of bit-cells [174],
[175]. Since there are only two voltage planes (VDD and
GND), every column of bit-cells needs its own set of bit
line and source line drivers so that the data may be
Fig. 21. Using the 2T-1MTJ dual source-line technique, (a) both
transistors are turned on to maximize current flowing through
the MTJ during write operations. (b) M2 allows current to bypass
the MTJ when current is being sinked through SL1.
independently written into the bit-cells in the row.
Hence, additional spacing is needed to separate neigh-
boring columns, which in turn degrades the achievable
integration density of STT-MRAMs. A common-source-line
(CSL) 1T-1MTJ STT-MRAM bit-cell design (Fig. 22) in
which all source lines in the array are electrically con-
nected is proposed in [176] to overcome this limitation.
The CSL design is enabled by the key insight that for
read operations, all source lines in the array are driven
to the same voltage. Furthermore, write operations occur
by applying voltages on the bit line and source line to
pass current through the selected bit-cells. In the CSL
design proposed in [176], read operations are the same
as that in the STT-MRAM design with separate source
lines. The write operation is modified into two steps as
follows (see Fig. 22). During the entire write operation,
the word line is driven to VDD and the bit lines are
driven to VDD or GND depending on the data to be writ-
ten into the corresponding column. During the first step
of the write operation, the common source line is driven

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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Fig. 24. Voltages on the control lines of the conventional 1T-1MTJ

STT-MRAM array (top) and the 1T-1MTJ STT-MRAM array with
Fig. 23. Array layouts using (a) the conventional and (b) the CSL balanced write scheme (bottom), for writing “1” (left bit-cell) and
schemes are illustrated. The bit-cell area for the CSL scheme will “0” (right bit-cell) into two “bottom-pinned” bit-cells in the
be smaller if the width of the access transistor is less than 10.
to GND. Current flows through the bit-cells that are con-
nected to bit lines that are driven to VDD , and the corre-
sponding MTJs in these bit-cells are programmed. Note
that no current flows through the bit-cells connected to
bit lines that are driven to GND. In the second step of
the write operation, the common source line is driven to
VDD instead. During this time, current stops flowing
through the bit-cells that are connected to the bit lines
that are driven to VDD , while it starts flowing through
those that are connected to bit lines that are driven to
GND. Hence, as shown in Fig. 22, the write operation of
the CSL design consists of two steps: First, only the “0”s
are written, followed by a step in which only the “1”s are
written. Note also that the time for each write step is de-
signed to ensure that all bit-cells are successfully written
into.
The area wasted to separate neighboring columns is
significantly reduced in the CSL design as shown in
same selected row. Differences in voltages are highlighted in red
in the tables on the right.
“0” and “1” are equal (hence, balanced write). For the
STT-MRAM technology parameters used in [179], it was
found that the balanced write scheme may achieve 43%
and 67% reduction in write delay and write energy,
respectively.
E. Two-Transistor One-MTJ STT-MRAM Bit-Cell
As discussed earlier, the current flowing through the
STT-MRAM bit-cell has to be smaller than a critical value
during read operations. On the other hand, the bit-cell
current needs to be sufficiently large during write opera-
tions to prevent write failures. For on-chip applications
where the number of supply planes may be limited, the
conflicting requirements on bit-cell currents for read and
write operations place a constraint on the width of the ac-
cess Tx. The two-transistor one-MTJ (2T-1MTJ) bit-cell
structure (Fig. 25) consisting of two access Tx’s con-
Fig. 23. Using -based [177] SCMOS layout rules [178] nected in parallel but with separate gates was proposed to
and a commercially available 45-nm CMOS technology overcome the conflicting design requirement for read and
for analysis, the CSL design can achieve 40% reduction write operations [62], [180]. During write operations,
in bit-cell layout area if the minimum access Tx width is
used to maximize integration density. However, the volt-
age levels may not be optimized for energy efficiency.
Balanced Write proposed in [179] optimizes write op-
eration voltages used in CSL design. By using a negative
voltage plane, the balanced write scheme allows the com-
mon source line to be directly connected to the GND
plane. Hence, the long source lines in the STT-MRAM
array may be completely eliminated and the integration
density of STT-MRAM can be improved. The voltages of
the word line and bit line for writing “0” and for writing
“1” are then optimized (see Fig. 24). The analysis in
[179] shows that the balanced write scheme may be very
effective in mitigating the effects of transistor source de-
Fig. 25. 2T-1MTJ bit-cell topology and corresponding layout for
generation, discussed in Section IV-B. The analysis done achieving maximum integration density. Note that the word lines
in [179] minimizes the STT-MRAM write energy with for M1 and M2 may be separately driven without bit-cell area
the constraint that the MTJ switching delays for writing penalty.

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 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 26. Structures of NV-SRAMs proposed (a) in [181], (b) in
[182], and (c) in [183]. The structure of (d) a volatile 6T SRAM is
also shown for comparison.
both access Tx’s are turned on to maximize current flow-
ing through the bit-cell. During read operations, only one
access Tx is turned on to limit the current flow. Analysis
of the bit-cell layouts in [63] and [174] shows that the lay-
out area penalty is minimal. Note that write, disturb, and
decision failures can be simultaneously minimized if the
access Tx’s are sized differently.
F. Nonvolatile SRAM (NV-SRAM)
Several alternative STT-MRAM bit-cell structures
(Fig. 26) have been proposed in the literature to target
applications that require fast access times [181]–[183].
These bit-cell structures are similar to the conventional
6T SRAM bit-cell. The difference is that a pair of MTJs
is used to skew the cross-coupled inverters in the SRAM
cell to implement an NV-SRAM bit-cell. When the
NV-SRAM cell is powered off, the MTJs are first pro-
grammed with the state of the cell. Note that MTJ0 and
MTJ1 in Fig. 26 store complementary data (i.e., one
stores “0” and the other stores “1”). When the NV-SRAM
is powered back on, the MTJs skew the cross-coupled
inverters so that the state the NV-SRAM returns to is
the state before it was powered off. The advantage of
NV-SRAM is that since the SRAM bit-cell topology
is preserved, only the array peripheral circuitry for
write operations needs to be modified to meet write
requirements. Furthermore, the differential nature of
the bit-cell structure enables self-referenced differential
read operations for fast read access. Self-referenced
read operations do not require a global reference for
sensing operations, which significantly impoves varia-
tion tolerance.
Fig. 27. Peripheral circuit for the destructive sensing scheme
from [31].
Although NV-SRAMs can achieve fast read opera-
tions, their restore operations depend on the ability of
the MTJs to skew the cross-coupled inverters. Hence, the
proposed NV-SRAM bit-cells may be sensitive to mis-
matches in MTJ characteristics. Furthermore, the sizes
of the transistors in the bit-cells shown in Fig. 26 may
need to be enlarged to meet the write current require-
ments. Also, NV-SRAM bit-cells illustrated in Fig. 26
need a significant number of extra transistors as com-
pared to the 1T-1MTJ STT-MRAM bit-cell. Hence, bit-
cells based on some of the device structures presented in
Section V may present a more area efficient approach to
enabling self-referenced differential read operations.
G. Robust STT-MRAM Sensing Schemes
Two circuit-level STT-MRAM sensing techniques
have been proposed to improve the robustness of read
operations in STT-MRAM [31], [96]. The basic concept
underlying these schemes is to exploit specific charac-
teristics of the STT-MRAM bit-cell so as to enable self-
referencing.
1) Destructive Self-Referenced Sensing: The self-referenced
sensing scheme proposed times in [31] achieves self-
referencing by comparing the resistance of the bit-cell
to a known resistance generated from the same bit-cell.
The sensing scheme (Fig. 27) can be illustrated by con-
sidering “1” to be represented by an MTJ in the AP
state, while an MTJ in the P state represents “0.” In
the first step of the sensing operation, a small read cur-
rent, IRD , is passed through the bit-cell to charge the
positive input terminal of a voltage sense amplifier
through the switch shown in Fig. 27. The bit-cell being
sensed is then overwritten with “0.” Next, IRD is passed
through the bit-cell again to charge the negative terminal
of the voltage sense amplifier through the switch. After
the voltages on the input terminals of the sense amplifier
have settled, the difference between them is large if the
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 28. Peripheral circuit for the nondestructive sensing scheme
from [96].
bit-cell originally stored a “1,” and small if it originally
stored a “0.” The voltage output of the sense amplifier is
“1” ðVDD Þ if the voltage difference between its inputs is
large and “0” ðGNDÞ if the difference is small. Since the
data in the bit-cell was overwritten with “0” during sens-
ing, it needs to be written back with “1” if the voltage
sense amplifier senses that it originally stored a “1” prior
to the overwriting step. This sensing scheme is destruc-
tive in that the stored data are overwritten during sens-
ing. Furthermore, the average energy dissipated by read
operations is larger than the average write energy since
every read operation consists of at least one write opera-
tion. Moreover, read accesses require long latencies since
they occur over four steps.
2) Nondestructive Self-Referenced Sensing: The energy
dissipation and destructive nature of the self-referenced
sensing scheme discussed earlier may be improved by
eliminating the need to overwrite and restore the data in
the bit-cell being sensed. This may be achieved by ex-
ploiting a different characteristic of the MTJ [96]. It was
observed that the voltage dependence of the MTJ resis-
tance is very strong when the MTJ is in the AP state, but
very weak when the MTJ is in the P state. Hence, data
may be sensed by sensing the voltage dependence of the
MTJ resistance using the circuit shown in Fig. 28. The
modified sensing operation proceeds as follows. The volt-
age on BL is first biased at VBL1 , and the current flowing
through the bit-cell is passed into the input of a 1 : 1
current mirror with SEL1 and SEL2 charged to VDD and
GND, respectively [96]. The output of the current mirror
charges the negative terminal of a voltage sense ampli-
fier. Next, SEL1 and SEL2 are set to GND, and the volt-
age of BL is charged to VBL2. The current flowing
through the bit-cell during this time is passed into the
input of a 1 : 2 current mirror with SEL1 and SEL2
charged to GND and VDD , respectively [96]. The output
1474 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
of this current mirror charges the positive terminal of
the voltage sense amplifier. If the voltage difference be-
tween the input terminals of the voltage sense amplifier
is large, the MTJ in the bit-cell being sensed is in the AP
state, and the voltage sense amplifier outputs “1” ðVDD Þ.
If the voltage difference between the input terminals of
the voltage sense amplifier is small, the MTJ in the bit-
cell being sensed is in the P state, and the voltage sense
amplifier outputs “0” ðGNDÞ.
The nondestructive sensing scheme greatly reduces
the energy dissipated by the read operation since the
MTJ does not need to be programmed. However, read
accesses still consist of multiple steps and may hence re-
quire more than one cycle. Furthermore, the voltage de-
pendence of the MTJ resistance may diminish as the size
of the MTJ is scaled down as shown in [27]. Hence, the
nondestructive self-referencing sensing may become inef-
fective in scaled MTJ technologies.
The circuit-level design techniques presented in this
section for improving STT-MRAM are summarized in
Table 4. First, techniques for embedding functionality
such as ROM, MemPUF, and TRNG in STT-MRAM ar-
rays with little or no overhead to the bit-cell area were
presented. This leads to significantly lower cost compared
to the case where such functionality is added separately.
Design techniques to optimize write energy efficiency of
STT-MRAM were then presented. Word-line and write-
voltage boosting, transistor body-biasing, and an external
magnetic field may be used to assist spin-transfer torque
during write operations. Techniques such as bit-line volt-
age clamping and the common source line with balanced
write scheme optimize the write energy efficiency of
STT-MRAM. Alternative bit-cell topologies such as the
2T-1MTJ bit-cell and nonvolatile SRAM bit-cells were
also discussed. The 2T-1MTJ bit-cell enables separate op-
timization of STT-MRAM for read and write operations.
The second access transistor may be used to limit or in-
crease the write current flowing through the MTJ, depend-
ing on the requirements. However, these circuit-level
design techniques may not satisfy requirements of applica-
tions that require low write latency. NV-SRAM bit-cells
were proposed for such applications. When power is sup-
plied to NV-SRAM, they function and perform as 6T
SRAM. The data stored in the NV-SRAM are backed up
into the MTJs within the bit-cell before power is removed
so as to save leakage power when the NV-SRAM is idle.
When the data in NV-SRAM are required, power and the
state stored in the MTJs are restored to the bit-cell. Thus,
the NV-SRAM can approach the performance of 6T SRAM
while providing nonvolatility. Although the circuit-level
design techniques presented here are promising for opti-
mizing STT-MRAM, further improvements can be
achieved by considering the architectural aspects of STT-
MRAM. In Section VII, we will discuss architecture-level
design techniques for STT-MRAM that exploit its unique
characteristics.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Table 4 Summary of Circuit-Level Design Techniques to Improve STT-MRAM
VII. IM PROVING S TT- MRAM ARRAY
ARCHITECTURE
The unique characteristics of STT-MRAM lead to a num-
ber of benefits while also posing some key challenges in
the design of memory arrays. For example, just using STT-
MRAM as a drop-in replacement for SRAM in on-chip ca-
ches may give some benefits due to the increase in cache
capacity and nonvolatility. However, the performance may
suffer due to longer access times. Moreover, error rates in
STT-MRAM may be prohibitively high and require array
level design techniques to handle them, thus reducing the
benefits. In this section, we first discuss the various array-
level design considerations and techniques for STT-
MRAM. Thereafter, various architectural optimizations to
maximize the benefits of STT-MRAM are presented.
A. STT-MRAM Array Design
Fig. 29 shows the design of a basic STT-MRAM mem-
ory array. Similar to a traditional SRAM array, the STT-
MRAM array consists of row and column decoders that
are used to select the required bit-cells for access, sense
amplifiers that are used to sense the data during the read
operation, and write drivers to charge the bit and source
lines to appropriate voltages during the write operation.
Furthermore, large STT-MRAM memory arrays can be
organized into banks, sub-banks, mats, and subarrays in
a manner similar to SRAMs in order to reduce the delay
and energy consumption from longer interconnects. A
key difference between SRAMs and STT-MRAMs is in
the idle state. Due to the nonvolatile nature of STT-
MRAMs, the bit and source lines can be grounded in the
idle state. As a result, the leakage energy consumption is
limited to only the peripheral circuits. However, when
the array is accessed to perform a read/write operation,
charging the bit lines or source lines introduces leakage
paths in the unselected cells of the column, leading to
active leakage power consumption. Another major differ-
ence is in the sensing mechanism used for performing
the read operation. The basic STT-MRAM array employs
single-ended sensing, and therefore requires reference
bit-cells as shown in Fig. 29. Sensing is performed by
comparing the current/voltage through/across the se-
lected bit-cells to that of the reference bit-cells. As ex-
plained earlier, this can lead to significant reduction in
the sensing margin under variations. This is further de-
graded by the active leakage current through the unse-
lected cells. For example, consider an array consisting of
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 29. Conventional STT-MRAM array design.
m bit-cells per column. The net current passing through
the bit line during read operation from a bit-cell storing
“0” is given by IRD;0 ¼ ðIon;0 þ ðm  1ÞIoff Þ. Similarly, for
a bit-cell storing “1,” IRD;1 ¼ ðIon;1 þ ðm  1ÞIoff Þ. The ar-
ray MR ratio ðTMRarray Þ is given by
IRD;0  IRD;1
TMRarray ¼
IRD;1
Ion;0  Ion;1
¼ write errors may be introduced during the operation of
Ion;1 þ ðm  1ÞIoff
Ron;1  Ron;0
¼ Roff G TMRbitcell : (18)
Ron;0 þ ðm1Þ
Note that TMRarray is less than the bit-cell-level MR ratio
ðTMRbitcell Þ, and this leads to increased read failures in
the STT-MRAM array [184], especially in on-chip caches
(due to their fast access time requirement).
One approach to address this problem of reduced read
margins is adaptive array design [185], [186] illustrated
in Fig. 30, which uses one or more bit-cells to store a sin-
gle bit of data depending on the read speed and capacity
requirements. When capacity is critical, then each bit is
stored in 1T-1MTJ configuration to maximize array capac-
ity. Next, in order to achieve higher read speed, adjacent
columns are utilized to store a bit and its complement.
The read operation is then performed by comparing the
resistances of these bit-cells to each other using a differ-
ential sensing scheme, thereby enabling faster read opera-
tions. Storing data in a complementary fashion increases
the effective signal difference that needs to be sensed to
read out the stored data while reducing the effective array
capacity. To further improve the read speeds, the effec-
tive signal difference may be further increased by com-
bining adjacent rows as shown in Fig. 30, thereby
utilizing four bit-cells to store a bit of data. Conceptually,
the adaptive array improves sensing performance of STT-
1476 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
Fig. 30. Adaptive STT-MRAM array design: (a) single cell storing
1 bit per 1T-1MTJ, (b) dual cell storing 1 bit in 2T-2MTJ,
(c) quadruple cell storing 1 bit in 4T-4MTJ.
MRAM by sacrificing capacity. This may also be achieved
in the MLC storage device [187]. For example, an array
of MLC bit-cells may be operated in SLC mode to im-
prove sensing operations. In the MLC mode, the possible
data stored in bit-cells are “00,” “01,” “10,” and “11.” In
the SLC mode, the bit-cells store either “00” or “11.” The
difference in resistance of the MLC bit-cell in the SLC
mode can be larger than that in the SLC bit-cells, making
it easier to distinguish between stored resistance states at
the expense of fewer stored data bits.
Another design consideration at the array-level is Error
Correction Codes or ECC, which can be used to tackle bit-
level errors [188], [189]. As described in Section III-B,
STT-MRAM due to thermal effects and process variations.
This presents a tradeoff between write current versus error
rate, which in turn translates to area and energy versus er-
ror tradeoff. Therefore, the use of multibit ECC can im-
prove the energy and density of spin memories by relaxing
the write current requirement [189]. Furthermore, multi-
level ECC can also be used to mitigate the increase in
write current and corresponding increase in area due to
write current variations. In multilevel ECC, data words
that are significantly affected by variations are provisioned
with a second-level ECC to correct the potential errors in
large numbers of bits [188].
Another major concern with STT-MRAM is its write
energy as discussed earlier. The nonvolatile nature of
STT-MRAM presents a unique opportunity to reduce the
write energy required at the array level. For example,
the STT-MRAM array does not suffer from half-select
problem as mentioned earlier, and therefore, the unse-
lected columns of the array can remain in the idle state
[190]. As a result, energy is only dissipated in selected
bit-cells connected to the selected columns. Note that al-
though the write energy for individual STT-MRAM bit-
cells may be high, the write energy consumption at the
array-level may not increase as much since the half-
selected bit-cells do not dissipate energy.
Although the aforementioned array design techniques
may be able to overcome some of the deficiencies of
STT-MRAM, more can be achieved if the architecture is
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
optimized considering unique characteristics associated
with STT-MRAMs. For example, STT-MRAM has high
write energy and latency compared to its CMOS counter-
parts (i.e., SRAM and DRAM). In addition, the asymmetric
nature of write operations STT-MRAM further worsens
the inefficiency in write operations. Some benefits of
STT-MRAM may be recovered when MLCs are used, but
doing so may lead to variable write latencies as we have
shown in Section V-E. Therefore, the array architecture of
STT-MRAM needs to be optimized with careful consider-
ation of the different design tradeoffs. In the following
sections, we briefly survey some of the key architectural
optimizations that have been proposed for STT-MRAM.
B. Hybrid Cache
The motivation for hybrid cache stems from both de-
vice and architectural considerations [191]–[206]. From
the device point of view, different technologies (STT-
MRAM, CMOS memories) have complementary character-
istics (i.e., the strengths and weakness of STT-MRAM and
CMOS memories are mutually exclusive). For instance,
SRAM has high leakage and area but low write energy/la-
tency, whereas STT-MRAM has very low leakage and
high density at the cost of high write energy/latency.
From an architecture perspective, different levels in the
memory hierarchy have different design constraints: 1) L1
cache must have lower access latency and can have small
capacity; 2) Last-Level Cache (LLC) is typically much
larger in capacity and, therefore, requires high density and
low leakage power. In addition, different cache blocks
have different read/write characteristics (read-intensive
versus write-intensive). Based on the above observations,
two different hybrid cache architectures can be imple-
mented viz., Inter-level and Intra-level.
1) Inter-Level Hybrid Cache: Inter-level hybrid cache
architecture uses different memory technologies in dif-
ferent levels of the cache hierarchy to match the design
requirements of each cache level to the memory device
characteristics [191]–[194]. In this approach, the latency-
sensitive L1 cache is designed using bit-cells with fast ac-
cess times like SRAM, whereas capacity-sensitive LLCs
are designed with high-density memory technologies like
STT-MRAM. Furthermore, the inefficiency in write oper-
ations of STT-MRAM-based LLC can be addressed by
modifying the cache management policy to reduce the
number of writes to LLC, e.g., by allocating a cache
block only if its reuse count is predicted to be higher
than a certain threshold [205]. In this way, an inter-level
hybrid cache incorporates the benefits of different tech-
nologies in the design of memory hierarchy.
2) Intra-Level Hybrid Cache: The intra-level hybrid
cache architecture goes further than the inter-level hy-
brid cache architecture by mixing different memory tech-
nologies within each level of cache. This is done in order
Fig. 31. Way-based intra-level hybrid cache architecture.
to match the most suitable technology to the access char-
acteristics of different cache blocks. In order to illustrate
an intra-level hybrid cache, let us consider a design with
STT-MRAM and SRAM [191]–[193], [195], [202]–[204].
Recall that STT-MRAMs have relatively efficient reads,
but have higher write energy and latency than SRAMs.
Therefore, STT-MRAMs are most suitable for storing
read-intensive blocks, while SRAMs are suitable for stor-
ing write-intensive blocks. Note that in practice, most of
the cache blocks are read-intensive in nature, which
enables us to design a large portion of the cache using
STT-MRAMs, thereby exploiting its high density and low
leakage power.
Fig. 31 shows the design of a way-based intra-level
hybrid cache, in which a few cache ways are designed
using SRAM and the remaining cache ways are designed
using STT-MRAM. In order to classify the cache blocks
as read-intensive or write-intensive and direct them to
the appropriate way in the cache, suitable cache manage-
ment policies are used. The tag array stores additional
bits (that constitute a saturation counter) to determine if
the cache block is read- or write-intensive. When a cache
block is first written, its saturation counter is reset and
is incremented on every write operation. During a write
operation to STT-MRAM, its saturation counter is
checked to see if it has reached a threshold. If it has, the
saturation counters in the SRAM ways are checked for
the smallest value. If the value in the saturation counter
for the STT-MRAM way is larger than that for the SRAM
way (i.e., the SRAM way in that cache block is less
write-intensive than the STT-MRAM that was being writ-
ten to), then the cache blocks are swapped. A swap
buffer is added as shown in Fig. 31 to enable swap opera-
tions across ways. In this way, SRAM ways are used to
store cache blocks with high write intensity and mitigate
the impact of inefficient writes in STT-MRAM ways.
However, due to the small number of SRAM ways,
the aforementioned policy can lead to high conflict mis-
ses for write-intensive workloads. An adaptive cache
management policy [206] can be used to address this is-
sue. In this policy, a cache block is evicted to lower-level
memory only if it is predicted to be dead (i.e., the cache
Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1477
Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 32. The large amount of redundant bit writes to L2 in SPEC
2006 benchmark indicates that substantial write energy savings
may be achieved by avoiding redundant bit writes [207].
block is unlikely to be reused). Otherwise, the cache
block is migrated to an STT-MRAM way to eliminate the
overheads associated with conflict misses. In addition,
the cache block allocation policy can be adapted based
on the nature of cache write operations. If the cache
block being written is either unlikely to be reused or
only reused in the near future, then it is stored in SRAM
ways. On the other hand, if the cache block being writ-
ten is not a dead block and is unlikely to be written in
the near future, it is stored in STT-MRAM ways. This
leads to lower conflict misses in SRAM ways, and the
cache performance is improved.
C. Reducing Redundant Writes
Two kinds of write operations occur in caches:
1) write on dirty cache block eviction from higher-level
caches to lower-level caches, and 2) write on cache block
replacement in which a new cache block from lower-level
memory replaces the exiting cache block. In the former, a
cache block is marked dirty even if only one of the words
in the cache block is modified. As such, the write opera-
tion is performed on every bit in the cache block upon
eviction in traditional cache architectures. This may re-
sult in significant amount of redundant writes when very
few words in the cache block are actually dirty. Even
when we consider the cache block replacement, not all
the bits of the cache block are modified during the write
operation. An analysis of the writes to a 16 MB L2 cache
incurred during the execution of SPEC 2006 benchmarks
(Fig. 32) shows that 88% of the bit-level writes are re-
dundant [207]. These redundant write operations can
lead to significant unnecessary energy consumption in
STT-MRAM. In the following sections, we will discuss dif-
ferent techniques to address this issue [190], [207]–[212].
1) Early Write Termination: Early write termination
[207] was proposed to reduce the write energy wasted in
STT-MRAM. It takes advantage of the fact that read op-
erations are significantly faster than write operations in
STT-MRAM. Hence, read operations are performed first
to quickly determine which bits in the word need to be
1478 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
Fig. 33. Partial line update scheme.
overwritten. Only the bits that need to be modified are
written into after the read operation. The redundant
write operations are eliminated as a result, and signifi-
cant write energy savings is achieved.
2) Partial Line Update: Another approach to reduce the
redundant writes on cache block eviction is partial line
update [190]. This scheme is illustrated in Fig. 33 for a
two-level cache hierarchy. Additional dirty bits in the tag
array are used to track the dirty blocks at sub-block gran-
ularity in the L1 cache. When a cache block is evicted
from L1 cache, only the dirty portion of the cache block
is written to L2, thereby eliminating the energy consump-
tion from redundant writes of other sub-blocks.
3) Write Biasing: As discussed earlier, a significant num-
ber of redundant write operations may occur if an evicted
cache block contains very few dirty blocks. Hence, signifi-
cant write energy savings can be achieved if the replace-
ment policy is modified to increase the residency of dirty
blocks in the higher level caches, thereby reducing the
number of dirty block evictions [208]. The objective here
is to accommodate all the writes to a cache block and avoid
premature eviction. In a typical Least Recently Used (LRU)
replacement policy, the most recently accessed block is
placed at the top of stack (TOS) for replacement. This pol-
icy is agnostic to loads and stores as well as dirty and clean
blocks. In order to reduce the eviction of dirty blocks, the
insertion, eviction, and promotion steps of the cache block
replacement policy are modified as follows:
• Insertion policy for Loads: Target cache blocks
are inserted at distance K from TOS if all posi-
tions higher than K are dirty. Otherwise, it is in-
serted at TOS similar to LRU.
• Promotion policy for Loads: Target cache blocks
are promoted to position K if all stack positions
higher than K are dirty. Otherwise, it is promoted
to TOS similar to LRU.
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Fig. 34. As shown in [213], the lifetime of data in L2 cache can be
less than 1 s and, hence, 10-year retention time is probably
excessive for on-chip cache applications.
• Insertion policy for Stores: Target cache blocks
are always inserted at position K. This prevents
one-time stores from occupying positions higher
than K for very long periods unless replaced by
another store operation.
• Promotion policy for Stores: Target cache blocks
of store hits to dirty lines are promoted to TOS.
Store hits to clean blocks are promoted to posi-
tion K.
• Eviction policy: The cache block at the bottom of
the stack is evicted.
The parameter K determines the relative preference given
to the residency of dirty blocks over clean blocks and is
determined based on the configuration and characteristics
of the cache hierarchy.
D. Volatile STT-MRAM
As Fig. 34 shows, the lifetime of the data in the cache
is typically low and, therefore, the cache does not re-
quire very long retention time. Hence, the energy barrier
required for STT-MRAM-based on-chip caches can be
reduced to reduce the retention time and the write
latency (see Table 5) [213]–[218]. Furthermore, differ-
ent levels in the cache hierarchy may also be designed
with different retention times depending on the design
requirements [218]. Even within a single cache level, bit-
cells with different retention times can be used to store
cache blocks with different access characteristics [218].
In order to ensure that data with relatively long lifetime
(large interval between writes) are stored correctly, refresh
Table 5 Retention Time Versus Write Latency for STT-MRAM in [213]
Fig. 35. Conceptual description of the asymmetry-aware write
scheme for STT-MRAM cache.
mechanisms, similar to those used for DRAM, are em-
ployed in volatile STT-MRAM designs [213]–[218].
E. Asymmetry-Aware STT-MRAM
Cache Architecture
As explained earlier, the write operation in STT-MRAM
is asymmetric, i.e., writing from “0” ! “1” (P ! AP)
requires higher latency/energy compared to “1” ! “0”
(AP ! P). As a result, the cache write latency is deter-
mined by the slower “0” ! “1” switching time, resulting
in significantly higher latency and energy. Asymmetry-
aware cache architecture [219], [220] is aimed at ad-
dressing this issue. This technique involves the introduc-
tion of redundant blocks (RBLs), which are preset to “1”
(AP state) as shown in Fig. 35 [219]. During a write op-
eration, the new cache block is written to one of the
Clean RBLs by writing the appropriate bits from “1” !
“0,” resulting in “fast write” operation. The other loca-
tion, which initially stores the cache block (before the
write operation), is marked as a Dirty RBL. If a Clean
RBL is not available during a write operation, then a
higher access latency is incurred (Slow write), and the
write operation is performed on the current cache loca-
tion. Simultaneously, the Dirty RBLs are also pro-
grammed to the “1” state and marked as Clean RBLs.
Note that this eliminates the additional latency penalty
for the preset operation by overlapping it with the slow
writes. Thus, asymmetry-aware architecture reduces the
effective latency of write operations in STT-MRAM ca-
ches by increasing the frequency of fast write operations.
F. Obstruction-Aware Cache Architecture
The long latency of write operations in STT-MRAM-
based last-level caches (LLCs) can obstruct successive
cache accesses and lead to significant performance over-
heads, especially in the context of multicore systems.
Obstruction-aware cache architecture proposes suitable
cache managemement schemes to address this issue
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Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Table 6 Summary of Architecture-Level Design Techniques to Improve STT-MRAM
[209], [221]. It introduces an obstruction-aware monitor
(OAM), which tracks the request-response characteris-
tics of the STT-MRAM cache in terms of miss rate,
read/write latency, etc., for each core. OAM uses these
statistics to estimate the effective latencies of the STT-
MRAM cache if the cache block is written to the cache
(T1) and not written to the cache (T2). If T1 9 T2, this
implies that the process running on that core is write-
intensive and can degrade the performance through cache
obstruction. Such a process is labeled as an obstruction
process. Subsequent write requests from this process are
forwarded to lower-level memory and not written to
STT-MRAM cache. This eliminates obstruction of the
cache from long-latency writes and improves the overall
system performance.
Table 6 summarizes the key architectural-level design
techniques for improving STT-MRAM that we reviewed
in this section. We initially discussed the design of the
conventional STT-MRAM array and the adaptive STT-
MRAM array design, which is able to increase read
margins and performance. We then discussed research
proposing ECC schemes for mitigating the errors, which
may arise due to retention failures, stochastic write pro-
cess, etc. An interesting aspect of the conventional STT-
MRAM array is that unlike its SRAM counterpart, power
is only supplied to the bit-cells being accessed. Thus,
there is no half-select issue in STT-MRAM, and the read
operation can be more energy-efficient than in SRAM.
Next, we discussed hybrid STT-MRAM cache architec-
tures. The strategy employed in the inter-level hybrid
cache is to use SRAM for latency-sensitive levels of the
1480 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
cache hierarchy, and STT-MRAM in the capacity-sensitive
portions. In the intra-level hybrid cache design, SRAM
and STT-MRAM are implemented in the same level of
cache: Some ways are implemented using SRAM, while
the rest are implemented using STT-MRAM. The hybrid
cache design approach mitigates the impact of the long la-
tency write operations in STT-MRAM. Our discussion
subsequently focused on several techniques that reduce
redundant write operations in STT-MRAM to save write
energy. The early write termination technique achieves
this by performing a read operation prior to write so as to
determine the bits that need to be changed in cache. The
partial line update technique uses history bits to track
sub-blocks that have been modified in the cache blocks.
When the cache block is evicted from the higher level of
cache to the lower level, only the sub-blocks that have
been modified are updated in the lower-level cache. The
write biasing technique uses a modified replacement pol-
icy to avoid premature eviction of cache blocks from the
higher levels of cache. The objective is to ensure that as
many bits as possible in the cache block have been modi-
fied before it gets evicted to the lower-level cache. The
next technique discussed to reduce STT-MRAM write en-
ergy is the concept of volatile STT-MRAM. This tech-
nique exploits the fact that the lifetime of data in cache is
usually small. Thus, EB may be lowered to save write en-
ergy. In applications that need a longer retention time
than that supported by the lowered EB , refresh mecha-
nisms similar to those used in DRAM may be used.
Asymmetry-aware and obstruction-aware cache architec-
tures, which mitigate the impact of the long latency
 Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
write operations, were also presented. The asymmetry-
aware cache architecture exploits the asymmetry in
STT-MRAM write operations to reduce the effective write
latency. Finally, the obstruction-aware cache architecture
avoids obstruction of cache accesses by long latency write
operations.
VIII . CONCLUSION AND OUTLOOK
It has been four decades since the discovery of the
tunneling magnetoresistance effect by Jullière. Since
then, many improvements in fabrication techniques as
well as new discoveries have pushed spin-transfer-
torque-based memory technology to become a leading
candidate for future nonvolatile on-chip memory tech-
nology. As we have discussed earlier, STT-MRAM offers
significant benefits over modern SRAMs for last-level
cache applications due to its nonvolatility and high inte-
gration density. However, the benefits can be greater if
not for the conflicting design requirements that STT-
MRAM designers need to overcome to meet read, write,
and reliability design targets. The problem is further
exacerbated by design issues that limit the write energy
efficiency, read performance, and robustness of STT-
MRAM (such as source degeneration of the access
transistor, requirement for bidirectional write currents,
asymmetry in critical write currents, shared read and
write current paths, and single-ended sensing read
operation).
Much research effort has since been placed on over-
coming the challenges associated with STT-MRAM,
pushing it closer towards fulfilling its promise of be-
ing a high-performance, ultra-low-power, nonvolatile,
universal memory technology. The STT-MRAM design
techniques found in the literature may be broadly classi-
fied based on the level of design abstraction that they ad-
dress. At the device level, alternative structures for the
STT-MRAM storage element, the MTJ, have been pro-
posed to give it the desired characteristics. Two terminal
MTJ structures, for example, have been studied to under-
stand the design space available for achieving maximum
STT-MRAM integration density for last-level cache appli-
cations. An important goal in the study of new materials
and two terminal stacks is to reduce the high write en-
ergy of STT-MRAM. In this respect, the MTJ with dual
MgO/free layer interfaces is promising. However, the
two terminal MTJ may be insufficient for achieving STT-
MRAM that performs as well as SRAM. The multitermi-
nal storage elements that were discussed may be needed
for STT-MRAM to be feasible for higher-level cache ap-
plications. Also, new physical phenomena observed in ex-
periments (e.g., domain wall motion and spin-orbit
torque effect) and new materials (e.g., topological insula-
tors and better magnetic materials) provide new avenues
to overcome the design challenges in STT-MRAM. It is
increasingly likely that the STT-MRAM storage device
will depend on the target application. The two terminal
MTJ stacks are more suitable for high-density STT-
MRAM with low performance requirements, whereas
multiterminal devices or devices using new physical phe-
nomena for writing are more suited for high-performance
STT-MRAM. However, experimental data are needed to
verify our understanding of spin-transfer torque (such as
size effects discussed in [40]) and to validate the models
used to study the multiterminal devices discussed in
Section V.
At the circuit-level, STT-MRAM bit-cell design tech-
niques have been developed to extract maximum benefit
from the various device structures. One unique charac-
teristic of STT-MRAM, for example, is that new func-
tionality (e.g., read-only memory, true random number
generator, and physically unclonable functions) may be
embedded within the STT-MRAM array (i.e., the array
functions as nonvolatile RAM as well as the embedded
function) at near-zero cost/penalty. It was also found that
the integration density of STT-MRAM may be improved
by sharing the source lines. Some proposed circuit-level
design techniques seek to improve write energy efficiency
(e.g., “self-enable” write scheme, balanced write scheme,
bit-line clamping, and 2T-1MTJ dual-source-line bit-cell),
while some optimize the design by decoupling design
knobs (e.g., write assist schemes, and 2T-1MTJ bit-cell
with independent word lines). Novel sensing schemes
(e.g., destructive and nondestructive sensing) have also
been proposed to improve the robustness of STT-MRAM
read operations.
Analysis of last-level caches shows that the nonvolati-
lity and higher integration density of STT-MRAM makes
it more suitable than 6T SRAM. Techniques to optimize
the STT-MRAM array design and architecture have also
been explored to extract more benefits out of STT-
MRAM. For example, the cache line update scheme may
be optimized to minimize write energy consumption
and further improve energy efficiency of STT-MRAM.
Conventional ECC schemes have been investigated to
mitigate stochastic effects and process variations in
STT-MRAM. Results show that stronger ECC may be
needed to improve the robustness of STT-MRAM as the
size is scaled down. Since the write energy in STT-
MRAM is significantly higher than SRAMs, the energy
efficiency of STT-MRAM on-chip cache can be im-
proved if write operations to STT-MRAM bit-cells are
avoided (e.g., through hybrid caches, early write termi-
nation, partial line update, and write biasing cache
blocks to avoid premature eviction of cache blocks).
The architecture may also be designed to increase the
frequency of fast write operations such as in the asym-
metry-aware STT-MRAM cache.
It is important to note that device/circuit/array-
architecture co-design techniques have been very effec-
tive in optimizing STT-MRAM. For example, volatile
STT-MRAM exploits the fact that the lifetime of data in
Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1481
Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems

on-chip cache is much shorter than the 10-year lifetime
standard used in the mass storage industry. By relaxing
the retention time requirement, the same write current
programs the STT-MRAM bit-cell in a much shorter
time and gives an opportunity to reduce write latency
and energy consumption. Furthermore, the retention
time requirement is different for different cache levels
and also for different cache blocks within the same
cache level. Hence, the STT-MRAM bit-cells for differ-
ent cache blocks can utilize MTJs with different reten-
tion times. The array architecture must also be designed
to support the partitioning of the caches, and ECC
schemes may need to be implemented to ensure reli-
ability of the volatile STT-MRAM cache. It is possible
that stronger ECC schemes may be able to push the
limit of energy efficiency in STT-MRAM and warrant
further investigation. As interest in STT-MRAM con-
tinues to grow, we expect to see a myriad of STT-
MRAM storage devices suitable for different application
requirements as well as corresponding device/circuit/
array-architecture co-optimization techniques.
Many other challenges in STT-MRAM, including sev-
eral that are beyond the scope of this paper, remain to
be solved. Several material layers are needed to form
MTJs with desirable characteristics [33], [78], [222]. The
synthetic anti-ferromagnetic pinned layer structure,
which is preferred for its small stray field, consists of as
many as 20 layers [223]. The deposited layers may be
damaged during patterning to define the MTJ pillars
[224]. The refinement of MTJ fabrication steps compati-
ble with the CMOS fabrication process will be crucial for
realizing the STT-MRAM devices discussed in Section V.
Advances in STT-MRAM are also crucial to emerging
nonvolatile computation systems [225]–[228]. STT-
MRAM devices have also been explored to realize Bool-
ean logic. While it is an active area of research with
many open challenges [227], [240], [241], we focus on the
prospects and challenges of using STT devices to realize
memory in this work. In Section VI, we showed how the
STT-MRAM memory device may be used as a true ran-
dom number generator. Moreover, it has been shown
that the functionality of STT devices are similar to artifi-
cial neurons and synapses, and thus, these devices can
enable new computation paradigms [228]. Thus, ad-
vances in the fabrication of STT-MRAM memory devices
with low switching energy also aids the development of
energy-efficient neuro-inspired computational systems.
Finally, the ability of STT-MRAM to achieve extreme
integration density in multilevel bit-cells and racetrack
memory is an attractive characteristic that has not been
fully exploited. It is worthy to note that several studies
have explored the system-level benefits of multilevel STT-
MRAM bit-cells [229]–[239]. It has been found that the
variable access latency in multilevel STT-MRAM bit-cells
may be made manageable by suitably engineering the stor-
age device [230]–[234]. At the time of writing, the variabil-
ity in racetrack memory remains the biggest factor limiting
the achievable integration density of STT-MRAM.
Research has begun in earnest to study new material
systems and new phenomena that address the challenges
facing STT-MRAM. These efforts give reason for hope,
and may prove to be the boost required for STT-MRAM
to fulfill its potential as the truly universal next-generation
memory technology. h

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ABOUT THE AUTHORS

Xuanyao Fong (Member, IEEE) received the B.
Sc. and Ph.D. degrees in electrical engineering
from Purdue University, West Lafayette, IN, USA,
in 2006 and 2014, respectively.
From January to August 2007, he was an In-
tern Engineer with Advanced Micro Devices, Inc.,
Boston Design Center, Boxboro, MA, USA. He was
a Research Assistant and then Postdoctoral Re-
search Assistant to Prof. Kaushik Roy with the
Nanoelectronics Research Laboratory, Purdue
University, from August 2007 to May 2015. Currently, he is a Research
Scientist with the Institute of Microelectronics, Agency for Science,
Technology and Research (A*STAR), Singapore. His research interests
include device/circuit/architecture co-design methodologies for Si and
non-Si nanoelectronics; design of high-performance and ultralow
power logic and memory systems using spintronic devices, circuits, and
architectures; and non-Boolean and analog computing paradigms using
emerging technologies.
Dr. Fong received the “AMD Design Excellence Award” at Purdue in
2008, and the best paper award at the 2006 International Symposium
on Low Power Electronics and Design.
Yusung Kim received the B.S. degree in electri-
cal and computer engineering from Rutgers Uni-
versity, Piscataway, NJ, USA, in 2007, and the
M.S. and Ph.D. degrees in electrical engineering
from Purdue University, West Lafayette, IN, USA,
in 2010 and 2015, respectively.
He is currently a Component Design Engineer
with Intel Corporation, Hillsboro, OR, USA. He
was a Research Assistant to Prof. Kaushik Roy
with the Nanoelectronics Research Laboratory,
Purdue University, until 2015. He was a Summer Intern with the Analog
and CMOS Embedded Memory Group, Texas Instruments, Dallas, TX,
USA, in 2012 and 2013. His current research interests include device cir-
cuit codesign for emerging nonvolatile memories.
Dr. Kim was a recipient of the Magoon Award for Excellence in
Teaching from Purdue University in 2010 and the Purdue Research
Foundation Fellowship in Summer 2011.

Vol. 104, No. 7, July 2016 | Proceedings of the IEEE 1487

Fong et al.: Spin-Transfer Torque Memories: Devices, Circuits, and Systems
Rangharajan Venkatesan (Member, IEEE) re-
ceived the B.Tech degree in electronics and com-
munication engineering from Indian Institute of
Technology, Roorkee, India, in 2009, and the Ph.D.
degree in electrical and computer engineering from
Purdue University, West Lafayette, IN, USA, in 2014.
During his Ph.D. studies, he was a research
intern with Intel Corporation, Hillsboro, OR,
USA, from May to September 2012 and June to
September 2013, where he worked on develop-
ing low-power design methodologies for graphics processors and de-
signing circuits for enabling fine-grained power gating. He is currently
a Research Scientist with NVIDIA Corporation, Santa Clara, CA, USA.
His research interests include circuit-architecture codesign for emerg-
ing technologies, neuromorphic hardware architectures, approximate
computing, and variation-aware design methodologies.
Dr. Venkatesan was awarded the Ross Fellowship for the year
2009–2010 and the Bilsland Dissertation Fellowship for the year 2013–
2014 by the Graduate School, Purdue University. He has received the
Best Paper Award in the International Symposium on Low Power Elec-
tronics and Design (ISLPED) 2012 and a Best Paper Nomination in De-
sign Automation Test in Europe (DATE) 2015.
Sri Harsha Choday (Student Member, IEEE) re-
ceived the B.E. degree in electronics and tele-
communication engineering from the University
of Pune, Pune, India, in 2006, the M.S. degree in
electrical engineering from Oklahoma State Uni-
versity, Stillwater, OK, USA, in 2009, and the Ph.D.
degree in electrical engineering from Purdue
University, West Lafayette, IN, USA, in 2014.
He is currently a Research Scientist with Intel
Labs, Intel Corporation, Hillsboro, OR, USA. He
was a Senior Engineer with Qualcomm, Inc., San Diego, CA, USA, and a
summer intern with the Technology Development Group, Open-Silicon,
Inc., Milpitas, CA, USA, in 2014 and 2008, respectively. His current re-
search interests include variation-aware low-power memory design,
spintronics, and thermo-electric device modeling.
Dr. Choday was a student member of the Academic Appeals Panel.
He was a recipient of a Ph.D. Fellowship from Oklahoma State Univer-
sity in 2009.
Anand Raghunathan (Fellow, IEEE) received the
B.Tech. degree in electrical and electronics engi-
neering from the Indian Institute of Technology,
Madras, India, and the M.A. and Ph.D. degrees in
electrical engineering from Princeton University,
Princeton, NJ, USA.
He is a Professor and Chair of VLSI with the
School of Electrical and Computer Engineering,
Purdue University, West Lafayette, IN, USA,
where he leads the Integrated Systems Labora-
tory. He was previously a Senior Research Staff Member with NEC Labo-
ratories America, Princeton, NJ, USA, and has held the Gopalakrishnan
Distinguished Chair with the Indian Institute of Technology, Madras.
He has coauthored a book, High-Level Power Analysis and Optimiza-
tion (Kluwer, 1998), eight book chapters, 21 U.S patents, and over 220
refereed journal and conference papers. His research explores domain-
specific architecture, system-on-chip design, embedded systems, and
heterogeneous parallel computing.
Prof. Raghunathan is a Golden Core Member of the IEEE Computer
Society. He has served on the technical program and organizing com-
mittees of several leading conferences and workshops. He has chaired
the ACM/IEEE International Symposium on Low Power Electronics and
Design, the ACM/IEEE International Conference on Compilers, Architec-
ture, and Synthesis for Embedded Systems, the IEEE VLSI Test Sympo-
sium, and the IEEE International Conference on VLSI Design. He has
1488 Proceedings of the IEEE | Vol. 104, No. 7, July 2016
served as Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED
DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ACM Transactions on Design Au-
tomation of Electronic Systems, IEEE TRANSACTIONS ON MOBILE COMPUTING,
ACM Transactions on Embedded Computing Systems, IEEE Design &
Test of Computers, and the Journal of Low Power Electronics. His publi-
cations have been recognized with eight best paper awards and four
best paper nominations. He received the Patent of the Year Award
(recognizing the invention with the highest impact) and two Technology
Commercialization Awards from NEC. He was chosen by MIT’s Technol-
ogy Review among the TR35 (top 35 innovators under 35 years, across
various disciplines of science and technology) in 2006, for his work on
“making mobile secure.” He was a recipient of the IEEE Meritorious
Service Award in 2001 and Outstanding Service Award in 2004.
Kaushik Roy (Fellow, IEEE) received the B.Tech.
degree in electronics and electrical communica-
tions engineering from the Indian Institute of
Technology (IIT), Kharagpur, India, in 1983, and
the Ph.D. degree in electrical and computer engi-
neering from the University of Illinois at Urbana-
Champaign, Urbana, IL, USA, in 1990.
He was with the Semiconductor Process and
Design Center of Texas Instruments, Dallas, TX,
USA, where he worked on FPGA architecture de-
velopment and low-power circuit design. He joined the Electrical and
Computer Engineering faculty at Purdue University, West Lafayette, IN,
USA, in 1993, where he is currently the Edward G. Tiedemann Jr. Distin-
guished Professor. He has published more than 600 papers in refereed
journals and conferences, holds 15 patents, has supervised 70 Ph.D.
dissertations, and is coauthor of two books on Low Power CMOS VLSI
Design (Wiley & McGraw-Hill). His research interests include spintro-
nics, device-circuit co-design for nano-scale Silicon and non-Silicon
technologies, low-power electronics for portable computing and wire-
less communications, and new computing models enabled by emerging
technologies.
Dr. Roy was a Research Visionary Board Member of Motorola Labs
in 2002 and held the M.K. Gandhi Distinguished Visiting faculty at IIT
Bombay. He has been in the Editorial Board of IEEE Design & Test, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS, IEEE TRANSACTIONS ON VERY LARGE
SCALE INTEGRATION (VLSI) SYSTEMS, and IEEE TRANSACTIONS ON ELECTRON
DEVICES. He was Guest Editor for the Special Issue on Low-Power VLSI
in the IEEE Design & Test (1994) and IEEE TRANSACTIONS ON VERY LARGE
SCALE INTEGRATION (VLSI) SYSTEMS (June 2000), IEE Proceedings Com-
puters and Digital Techniques (July 2002), and IEEE JOURNAL ON EMERG-
ING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS (2011). He received the
National Science Foundation Career Development Award in 1995,
the IBM faculty partnership award, the ATT/Lucent Foundation award,
the 2005 SRC Technical Excellence Award, the SRC Inventors Award, the
Purdue College of Engineering Research Excellence Award, the
Humboldt Research Award in 2010, the 2010 IEEE Circuits and Systems
Society Technical Achievement Award, the Distinguished Alumnus
Award from IIT Kharagpur, the Fulbright-Nehru Distinguished Chair,
the DoD National Security Science and Engineering Faculty Fellow
(2014–2019), the Semiconductor Research Corporation Aristotle award
in 2015; best paper awards at the 1997 International Test Conference,
IEEE 2000 International Symposium on Quality of IC Design, the 2003
IEEE Latin American Test Workshop, the 2003 IEEE Nano, the 2004 IEEE
International Conference on Computer Design, and the 2006 IEEE/ACM
International Symposium on Low Power Electronics & Design; the 2005
IEEE Circuits and System Society Outstanding Young Author Award
(Chris Kim), the 2006 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION
(VLSI) SYSTEMS Best Paper Award, the 2012 ACM/IEEE International
Symposium on Low Power Electronics and Design Best Paper Award,
and the 2013 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS Best Paper Award. He was a Purdue University Faculty Scholar
from 1998 to 2003.