International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
Adiabatic Logic: An Alternative Approach To Low
Power Application Circuits
Preeti Bhati, Navaid Z. Rizvi
School of Information and Communication Technology,
Gautam Buddha University
Greater Noida, India
bpreeti.bhati@gmail.com, navaidrizvi@gmail.com
Abstract—Today’s major concerns in designing VLSI circuits
have been the amount of power dissipated by these circuits. The
Adiabatic logic technique is becoming an answer to the problem
of power dissipation. The term ‘Adiabatic’ refers to the change of
state that occurs without the loss or gain of heat. The adiabatic
switching technique reduces the power dissipation during
switching events. But, adiabatic circuits highly depend upon
power clock and parameter variations. In this paper mux, one bit
sum and carry adder are designed and simulated on cadence
Virtuoso using 180nm technology. In an analysis PFAL is
compared with conventional CMOS logic on the basis of
frequency and supply voltage. The proposed technique shows the
reduction of power dissipation as compared to the conventional
CMOS design style. And results analysis accomplishes that
adiabatic logic can be used for the implementation of relatively
large, complex circuits that dissipate less energy than
conventional CMOS designs.
Keywords— PFAL, VLSI, CMOS Logic, Adiabatic logic, MUX,
Adder.
I. INTRODUCTION
Since the last few decades, the electronics industry has
been growing enormously due to integrated circuit technology.
Now, we have come a long way from the single transistor era
of 1958 to ULSI (Ultra Large Scale Integration) which support
the fabrication of more than fifty million transistors over a
single chip. The increased use of portable electronics devices
has made power dissipation an important design parameter in
modern electronics. Portable devices that work using a battery
have limited energy supplies and thus have a lifespan that are
constrained by their power consumption. Until now, power
consumption was not the greatest concern because of the
availability of large packages and cooling techniques that have
the capability of dissipating the generated heat. However, due
to continuously increasing density as well as the size of the
chips in the system might cause difficulty in providing
adequate cooling and hence, add significant cost to the system.
That is why we need a circuitry which can reduce power
dissipation even if a number of components are integrated
over a single chip. Our objective is to reduce the power
dissipation in digital CMOS VLSI circuits.
The demand, of CMOS technology can be mainly
attributed to lower power dissipation and high levels of
integration. However, the latest trend towards ultra-low power
978-1-4673-9939-5/16/$31.00 ©2016 IEEE
has made researchers search for techniques to recover or
recycle energy from the circuit. In recent days, researchers
largely focused to find the lower bound of energy
consumption. Different methods are commonly used for
reduction of power dissipation in digital circuits, but most of
the energy gets dissipated so, an adiabatic approach is the
solution for the design of power and energy efficient designs.
The amount of energy, recycle depends on fabrication
technology, switching events, and the voltage swing.
This paper has been segmented into five sections. Section
II describes a brief introduction about adiabatic logic. Section
III focuses on logic design and operation. Section IV includes
circuit implementation of digital circuits. Simulation
waveforms and power comparison table explanation is in
section V. and section VI focuses on conclusion.
II. ADIABATIC LOGIC
The term “Adiabatic” has been taken by thermodynamic
means no energy transfer to the environment, so there is no
dissipated energy loss. In real-life computing, because of the
presence of dissipative elements like resistance in a circuit
ideal process cannot be achieved. However, low energy
dissipation can be achieved by slowing down the speed of
operation and only switching transistor under certain
conditions. Adiabatic circuits are low power circuits which
need ‘reversible logic’ to conserve energy [1].
A. Oparation of Adiabatic Logic
Adiabatic offers a way to reuse the energy stored in the
load capacitor, rather than discharging the load capacitor to
the ground and wasting this energy. Operations of adiabatic
logic circuits are based on some basic rules such as never turn
on a transistor when there is a voltage potential between the
source and drain terminals, and never suddenly change the
voltage across any of the transistor [7].
The adiabatic logic is broadly known as ENERGY
RECOVERY CMOS logic as it uses reversible logic to
conserve energy.
Adiabatic logic families can be classified as:-
Partially Adiabatic:- In partially adiabatic or Quasi
adiabatic circuits, some charge gets transferred to the ground
i.e. some heat is dissipated. Hence a part of the energy is only
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being able to recover, but these circuits are easy to implement
as compared to fully adiabatic logic circuits.
Some partially adiabatic logic families are:-
1. Efficient Charge Recovery Logic (ECRL)
2. 2N-2N2P Adiabatic Logic
3. Positive Feedback Adiabatic Logic (PFAL)
4. Clocked Adiabatic Logic
Fully Adiabatic:- In fully adiabatic circuits, all the charges
on the load capacitance gets recovered and feedback to the
power supply. Due to which fully adiabatic circuits become
slower and complex as compared to partial adiabatic circuits
[11].
Some fully adiabatic logic families are:-
1. Pass Transistor Adiabatic Logic (PAL)
2. Two Phase Adiabatic Static CMOS Logic
(2PASCAL)
3. Split-Rail Charge Recovery Logic (SCRL)
B. Adiabatic Switching
An adiabatic switching is an alternative solution to reduce
power dissipation in the digital logic. The energy stored in the
output gets retrieved by reversing the current source direction.
Fig. 1. Adiabatic Switching Circuit.
Here, the constant current source is used to charge the load
capacitance not a constant voltage source as used in the case
of conventional CMOS circuits. Where, R represents the on-
resistance of PMOS network. The constant current power
supply is capable of retrieving the energy back from the
circuit. Thus, adiabatic logic circuits require non-standard
power supplies with time varying voltages such as pulsed
power supplies. Assume, that the capacitor voltage ܸ஼ is zero
initially, the voltage over the switch =IR
P(t) in the switch = ‫ܫ‬ଶ ܴ
Energy during charge = ሺ‫ܫ‬ଶ ܴሻT
E = ሺ‫ܫ‬ଶ ܴሻT = (‫ܸܥ‬Ȁܶሻଶ RT = ‫ ܥ‬ଶ ܸ ଶ /TR (1)
ଶ ଶ
E = ‫ܧ‬ௗ௜௦௦ = (RC/T) Cܸ = (2RC/T) (1/2Cܸ ) (2)
Here,
E = dissipated energy during charging,
Q = charge transfer to the load,
C = load capacitance value,
R = on- resistance of PMOS switch,
V = voltage final value at load,
T = charging time.
Hence, the dissipated energy can be reduced by reducing
the on-resistance of PMOS network and increasing the
charging time.
C. Power Clock Used for Adiabatic Switching
The structure of a power clock generator is a major part of
the whole adiabatic system design. The power clock used here
is a combination of power supply and a clock. Means, it
consists of frequency and voltage levels. The power clock for
an adiabatic circuit is multiphase means, four phases [10].
These phases are different levels at which specific operations
are performed as shown in figure.
Fig. 2. One Cycle of Power Clock.
Power clock consists four intervals these are Evaluate (E),
Hold (H), Recovery (R) and Wait (W). In E interval, the
outputs get evaluated from the stable input signal. During H
interval, the output is kept stable to provide input to the next
stage. Energy gets recovered during R interval and W interval
provides symmetry.
III. LOGIC DESIGN AND OPERATION
POSITIVE FEEDBACK ADIABATIC LOGIC (PFAL)
PFAL so called partial energy recovery circuit as it has a
good robustness against technological variations. It is a dual-
rail circuit. The general schematic of PFAL is as shown in the
figure below.
Fig. 3. Basic PFAL Structure.
PFAL consist of a latch formed by two cross-coupled
inverters to store the output state when input signal are ramped
down. The two n-trees connected in parallel of PMOS realize
the logic functions. The PMOSFET of the adiabatic amplifier
is in parallel to the functional block and form a transmission
gate. It uses four phase clock [6].
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 IV. CIRCUIT IMPLEMENTATION DESIGN AND IMPLEMENTATION OF FULL ADDER
DESIGN AND IMPLEMENTATION OF A 2x1 MUX (SUM)

A. Using CMOS A. Using CMOS

Fig. 6. Schematic of a Full Adder (SUM).

Fig. 4. Schematic of 2x1 MUX.

B. Using PFAL
B. Using PFAL

Fig. 7. Schematic of a Full Adder (SUM).

Fig. 5. Schematic of a 2x1 MUX.

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 DESIGN AND IMPLEMENTATION OF FULL ADDER NMOS transistor width 400nm
(CARRY) NMOS transistor length 180nm
A. Using CMOS Period of pulse 40ns
Rise time 10ps
Fall time 10ps

B. For PFAL Schematics

TABLE II. DESIGN SPECIFICATIONS

Specifications Values
Technology 180 nm
Power Supply 1.8 V
PMOS Transistor width 800nm
PMOS transistor length 180nm
NMOS transistor width 400nm
NMOS transistor length 180nm
Rise time 10ps
Fall time 10ps

Vsin offset voltage 900mV

Vsin amplitude 900mV
Fig. 8. Schematic of a Full Adder (CARRY).
Initial phase for sinusoid -90
B. Using PFAL frequency 200MHz

V. SIMULATION RESULT
In this paper, all the design structures based on
conventional CMOS logic and adiabatic logic are designed
and simulated on cadence virtuoso using 180nm technology.
The comparison is performed using different frequencies and
supply voltages. Power of CMOS and PFAL circuits is
calculated for different frequency and supply voltage. And the
effect of frequency on energy consumption is examined and
compared with the result of conventional CMOS. Transient
analysis results are as shown below.
A. Using CMOS

Fig. 9. Schematic of a Full Adder (CARRY).

A. For CMOS Schematics

TABLE I. DESIGN SPECIFICATIONS

Specifications Values
Technology 180 nm
Power Supply 1.8 V
PMOS Transistor width 800nm
PMOS transistor length 180nm Fig. 10. Transient Analysis of a 2x1 MUX.

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B. Using PFAL A. Using CMOS

Fig. 11. Transient Analysis of a 2x1 MUX. Fig. 14. Transient Analysis of a Full Adder (CARRY).

A. Using CMOS B. Using PFAL

Fig. 12. Transient Analysis of a Full Adder (SUM).

B. Using PFAL Fig. 15. Transient Analysis of a Full Adder (CARRY).

IMPACT OF PARAMETER VARIATIONS ON THE

POWER DISSIPATION
A. MUX COMPARISON
The power dissipation of a 2X1 MUX in conventional
CMOS and in PFAL logic is shown in table 1.

TABLE III. ANALYSIS OF 2X1 MUX

Frequency Supply and Average Average
(MHz) input power(μW) Power(μW)
Voltage(V) (CMOS ) (PFAL)
100 1 1.31 0.166
100 1.8 4.66 0.187
200 1 2.59 0.369

200 1.8 9.25 0.406

Fig. 13. Transient Analysis of a Full Adder (SUM).

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B. FULL ADDER (SUM) COMPARISON The analysis shows that the designs based on adiabatic
The power dissipation of a Full Adder (sum) in logic provide superior performance when compared to
conventional CMOS and in PFAL logic is shown in table 2. conventional CMOS. So, for low power and ultra-low power
requirements adiabatic logic is an effective alternative for
TABLE IV. ANALYSIS OF FULL ADDER traditional CMOS logic circuit designs.
Frequency Supply and Average Average VI. CONCLUSION
(MHz) input power(μW) Power(μW)
Voltage(V) (CMOS ) (PFAL) In this paper comparison between PFAL logic and CMOS
100 1 2.19 0.366 logic is carried out at different frequencies and voltages. And
we conclude that the PFAL circuits dissipate less power than
100 1.8 8.30 0.657
conventional CMOS circuits. From the above tables we
200 1 4.29 0.954 observed that at low frequency and voltage power dissipation
200 1.8 16.40 1.49
is also less. Adiabatic PFAL logic offers a significant power
reduction so, better performance over conventional CMOS
logic. However PFAL suffers from large switching time, so it
is not applicable where, the delay is critical.
C. FULL ADDER (CARRY) COMPARISON
The power dissipation of a Full Adder (carry) in References
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of PFAL circuits.

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