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A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-


SiC 130 nm technology by BSIM3v3 model

Article  in  Journal of Electrical Engineering · April 2019


DOI: 10.2478/jee-2019-0021

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Journal of ELECTRICAL ENGINEERING, VOL 70 (2019), NO2, 145–151

sciendo
PAPERS

A high electrical performance of DG-MOSFET transistors in


4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 Model
∗,∗∗ ∗, ∗∗∗ ∗,∗∗∗∗
Mourad Hebali , Menaouer Bennaoum , Mohammed Berka ,
∗, ∗∗∗∗∗ ∗∗∗∗∗∗
Abdelkader Baghdad Bey , Mohammed Benzohra ,
∗∗ ∗∗
Djilali Chalabi , Abdelkader Saidane

In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies
have been studied by BSIM3v3 model. In which the I–V and gm –V characteristics and subthreshold operation of the DG-
MOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results
so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The
electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and
low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized
by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very
high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively.
These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.
K e y w o r d s: 4H-SiC, 6H-SiC, BSIM3v3, DG-MOSFET, nm technology, 4I-V characteristics, subthresholdoperation

1 Introduction in nanoscale technology [3–5]. Having two gates ensures


excellent control of short channel effects (SCE) and im-
In the last decade, modern technology has been con- proves the capacity of the control of the current through
cerned with the study of mini components electronic at control of the channel.
the nanoscale, especially the Metal-Oxide Semiconductor The DG-MOSFETs transistors in Silicon technology
Field-Effect Transistor (MOSFET) [1]. This is what led to have been shown to be more optimal for ultra-low power
the development of devices and integrated circuits (ICs). circuit design due to the reduced leakage current and the
However, despite all this development, MOSFET transis- improved subthreshold slope compared to bulk CMOS [6].
tors have suffered from the serious effects of the Short In addition, many materials have been proposed to
Channel Effect (SCE) on her electrical behavior [2, 3]; replace silicon technology, among these materials Silicon
this necessarily affects the characteristics of CMOS inte- Carbide (SiC) [7], this is due to their distinctive char-
grated circuits. In order to reduce this influence, Double- acteristics such as wide bandgap, high thermal conduc-
Gate (DG) structure, has been proposed as a promising tivity, high breakdown field and high saturation veloc-
solution to replace the conventional MOSFET structure ity of electrons Table 1 [8]. This is why it is used in

Table 1. Basic parameters of 4H-SiC and 6H-SiC at T = 300 K

Materials 4H-SiC 6H-SiC


Parameters
Eg (eV) Energy gap 3.36 3.02
µe (cm2 /Vs) Electron mobility 1000- 1140 400-800
µh (cm2 /Vs) Hole mobility 115 90
Ni (cm−3 ) Intrinsic carrier concentration 8.2 × 10−9 2.3 × 10−6
Dielectric permittivity ( ε ) 6.63 6.58
Vsat × 107 (cm/s) 2 2
Thermal conductivity K (W m K ) −1 −1
4.9 4.9

* Department of Electrotechnical, University Mustapha Stambouli Mascara, 29000 Mascara, Algeria, hebalimourad@yahoo.fr,
** Laboratory: CaSiCCe, ENP Oran-MA, 31000 Oran, Algeria, *** Laboratoire de matriaux appliqus (AML), Universit Djillali Liabs,
22000 Sidi Bel-Abbes, Algeria, **** Laboratory E.P.O, University of Sidi Bel-Abbes, 22000 Sidi Bel-Abbes, Algeria, ***** Laboratory
AMEL, University of Sidi Bel-Abbes, 22000 Sidi Bel-Abbes, Algeria, ***** Department of Networking and Telecommunications, University
of Rouen, Laboratory LECAP, 7600, France

c 2019 FEI STU


DOI: 10.2478/jee-2019–0021, Print (till 2015) ISSN 1335-3632, On-line ISSN 1339-309X
146 M. Hebali et al : A HIGH ELECTRICAL PERFORMANCE OF DG-MOSFET TRANSISTORS IN 4H-SIC AND 6H-SIC 130NM . . .

S G G1 G2 G1
D S D
+ + + + + +
N N N N N N S D
+ - +
N P N
P-type substrate P-type substrate

(a) (b) Body (c)


Body
G2
Fig. 1. Different structures of transistors: (a) – SG-MOSFET, (b) – series DG-MOSFET, (c) – parallel DG-MOSFET

D
D
D G1

G Body G1
Body G2
G2 Body
(a) S (c) S
(b) S
Fig. 2. (a) – SG-MOSFET transistor, equivalent electronic circuits, (b) – series DG-MOSFET, (c) – parallel DG-MOSFET [20]

D D f (VGS )). Subthreshold operation (To find the different


parameters in this region as ION /IOFF ratio and sub-
ID1 ID1 ID2 threshold slope SS) and gm –V characteristic of our tran-
G
M1 sistors, and then we will carry out a comparative study
G M1 M2 between SG-MOSFET and DG-MOSFETs transistors for
Body 4H-SiC and 6H-SiC technologies. Our work will be carried
ID2 Body for 130nm technology, 1.2 V supply voltage and we will
M2 use the OrCAD(PSpice) software to simulate the different
characteristics of our devices.
S S
(a) (b)

Fig. 3. Drain current of DG-MOSFETS transistors,(a) – series


2 DG-MOSFETs transistors
(model 1), (b) – parallel (model 2) structures and models

Figure 1 shows the different structures of the SG-


the manufacture of electronic devices with high-voltage,
MOSFET and DG-MOSFETs transistors. The series
high-power, high-frequency and which operate within a
topology of a DG-MOSFET transistor (Model 1) is es-
wide range of temperature [9]. The SiC is characterized
sentially a series arrangement of two separate chan-
by many polytypes [8], the most important and most com-
monly used of which in electronic applications are 4H-SiC nels [18–20], with each channel having an independent
and 6H-SiC. In addition to using this technology in the gate connection to control the flow of current as shown
MOSFET transistors, they were also used to manufacture in the Fig. 1(b). For the second DG-MOSFET transis-
the high-voltage and high-power DG-MOSFET transis- tor topology (Model 2) [20], two MOSFET transistors
tors [7, 10, 11] or in the form of SiC/SiO2 layer in these are connected in parallel of the same substrate (Body) as
transistors [12, 13]. In the last few years, research has shown in the Fig. 1(c). Figure 2 shows the two equivalent
shown that the submicron electronic devices in SiC tech- electronic circuits models (series and parallel) of DG-
nology work well in low voltage and low power [14–17]. MOSFET transistor based on the SG-MOSFET tran-
In this paper, we will study and characterize the elec- sistor. As shown in Figs. 2(b) and 2(c), the two mod-
tronic behavior of DG-MOSFETs transistors in 4H-SiC els of DG-MOSFETs transistors are based on the same
and 6H-SiC technologies with submicron scale in or- SG-MOSFET transistor, this transistor carries the fol-
der to operate at low-voltage and low-power. Based on lowing descriptions: length and width of the channel
the Single Gate (SG) MOSFET transistor by BSIM3v3 L = 130 nm and W = 160 nm, respectively, the thick-
Model and using two equivalent electronic circuits of DG- ness of the oxide layer (SiO2 ) Tox = 2.3 nm and using
MOSFET transistor Series and Parallel models, we sim- the same doping value of the source, the drain and the
ulate the different I–V characteristics (Output charac- gate NS = ND = NG = 1020 cm−3 ). The doping of the
teristic ID = f (VDS ) and Transfer characteristic ID = channel and the substrate Nch = 2.3549 × 1017 cm−3 and
Journal of ELECTRICAL ENGINEERING 70 (2019), NO2 147

ID (mA) ID (mA)
10 (a) (b)
32
DG-MOS(4H-SiC) Model 2 28 DG-MOS(6H-SiC) Model 2
8
24
6 20
16
4 SG-MOS(4H-SiC) SG-MOS(6H-SiC)
12
8
2
DG-MOS(4H-SiC) Model 1 4 DG-MOS(6H-SiC) Model 1

0 0.2 0.4 0.6 0.8 VDS (V) 1.2 0 0.2 0.4 0.6 0.8 VDS (V) 1.2

Fig. 4. Output characteristic of SG-MOSFET and DG-MOSFETS transistors in, (a) – 4H-SIC and (b) – 6h-SIC technology

ID (mA) ID (mA)
10 (a) (b)
32
DG-MOS(6H-SiC) Model 2
DG-MOS(4H-SiC) Model 2 28
8
24
6 20
SG-MOS(4H-SiC)
16 SG-MOS(6H-SiC)
4
12
DG-MOS(6H-SiC) Model 1
DG-MOS(4H-SiC) Model 1 8
2
4

0 0.2 0.4 0.6 0.8 VGS (V) 1.2 0 0.2 0.4 0.6 0.8 VGS (V) 1.2

Fig. 5. Transfer characteristic of SG-Mosfet and DG-MOSFET transistors in: (a) – 4h-SiC, and (b) – 6h-SiC technology

Nsub = 6 × 1016 cm−3 , respectively. For the simulation of 3 Results and discussion
the MOS transistor by the model BSIM3v3, must be used
the level 7 in the software OrCAD(PSpice) [15]. 3.1 I–V characteristics
In this work, to study the electrical behavior of the Figure 4. shows the output characteristic ID = (VDS )
different models of the DG-MOSFETs transistors, we will of the SG-MOSFET and DG-MOSFETs transistors in
use polarization symmetry (VGS1 = VGS2 ) in both cases 4H-SiC and 6H-SiC technologies at room temperature.
of constant or variable as shown in Fig. 3. For this characteristic voltage VGS = 1.2 V and VGS1 =
For the series DG-MOSFET transistor, the (Weq /Leq ) VGS2 = 1.2 V for SG-MOSFET and DG-MOSFETs re-
geometric equivalent ratio of the channel given by [21] spectively, the VDS voltage is varied from 0 V to 1.2 V.
Weq /Leq = W/(LG1 + LG2 ) = W/(2L) . (1) The drain current ID expression of a SG-MOSFET
transistor by BSIM3v3 model is given by [22, 23]
So the drain current of this DG-MOSFET transistor
model can be expressed as µeff Cox W  Abulk VDS 
ID = VGS − Vth − VDS (6)

ID(Model 1) = ID(SG-MOSFET) 2 . (2) L + VDS /Esat VDS

According to the equivalent circuit of the parallel DG- where µeff is the effective mobility, Cox is the gate ca-
MOSFET transistor, the drain current expression of this pacitance per unit area, the parameter Esat corresponds
model is given by to the critical electrical field at which the carrier velocity
becomes saturated, and the parameter Abulk is used to
ID(Model 2) = ID1 + ID2 . (3)
take into account the bulk charge effect.
So The different models of DG-MOSFETs transistors
ID(Model 2) = 2ID(SG-MOSFET) . (4) work correctly (Ohmic and Saturation regions) like the
SG-MOSFET transistor in the 1.2 V voltage for the dif-
From (2) and (4), the relation between the drain currents
ferent semiconductor technologies as shown in Fig. 4.
of these models can be expressed as
According to this characteristic (ID = f (VDS )), the tran-
ID(Model 2) = ID(Model 1) /4 . (5) sistors in 4H-SiC technology are characterized by a low
ID drain current compared to the transistors in 6H-SiC
148 M. Hebali et al : A HIGH ELECTRICAL PERFORMANCE OF DG-MOSFET TRANSISTORS IN 4H-SIC AND 6H-SIC 130NM . . .

log (ID) log (ID)


(a) (b)
DG-MOS(4H-SiC) Model 2
DG-MOS(6H-SiC) Model 2
-6
-6
SG-MOS(6H-SiC)
SG-MOS(4H-SiC)
-8 -8

-10 DG-MOS(6H-SiC) Model 1


-10

DG-MOS(4H-SiC) Model 1
-12 -12
0 0.2 0.4 0.6 0.8 1.2 0 0.2 0.4 0.6 0.8 VGS (V) 1.2
VGS (V)

Fig. 6. LOG(ID ) with VGS of SG-MOSFET and DG-MOSFET transistors in, (a) – 4h-SIC, and (b) – 6H-SiC technology

technology for the different models (SG-MOSFET and threshold voltage Vth is given by [22, 23]
DG-MOSFETs) because of the difference of the thresh-
old voltage Vth(6H-SiC) < Vth(4H-SiC) whhich is related to Vth(SG–MOSFET) = Vth(Model 2) =
the energy band-gap Eg(6H-SiC) < Eg(4H-SiC) in Table 1 p p 
VTideal + γ Φs − Vbs − Φs (7)
of these semiconductors except the series DG-MOSFET
transistor in 6H-SiC and Parallel DG-MOSFET tran-
sistor in 4H-SiC which are characterized by saturation where VTideal is the threshold voltage of the long channel
currents IDsat of 8.119 µA and 9.489 µA respectively as device at zero substrate bias, γ is the body bias coeffi-
cient, and Φs is the surface potential.
shown in Table 2.
The results of these characteristics (ID = f (VGS ))
The parallel DG-MOSFET transistor (Model 2) is show that the SG-MOSFET and parallel DG-MOSFET
characterized by a drain current 2 times and 4 times (Model 2) transistors are characterized by the same value
greater than that SG-MOSFET and series DG-MOSFET of the threshold voltage for the different semiconduc-
(Model 1) transistors respectively for 4H-SiC and 6H-SiC tor technologies (4H-SiC and 6H-SiC). The SG-MOSFET
technologies as expected from (2), (4) and (5). The low transistor is characterized by a single Φs surface poten-
drain current of series DG-MOSFET transistor can be at- tial, but the series DG-MOSFET transistor (Model 1) is
tributed to the channel length of this model compared to characterized by two surface potentials following the two
other transistors. In addition, the results of this character- contacts of each gate as shown in the following expres-
istic show that the DG-MOSFETs transistors in 4H-SiC sion [20]
and 6H-SiC technologies work well in low power like the p p 
SG-MOSFET transistor at submicron technology [14], es- Vth(Model 1) = VTideal + γ 2Φs − Vbs − 2Φs . (8)
pecially the series DG-MOSFET transistor which is char-
acterized by an ultra low power compared to other tran- From this, the series DG-MOSFET transistor (Model 1)
sistors. Thus, the DG-MOSFET transistor in series struc- is characterized by a high value of the threshold voltage
ture is very suitable for low power applications. compared to parallel DG-MOSFET and SG-MOSFET
Figure 5 shows the ID current evolution as a function transistors for the different semiconductor technologies
of VGS voltage of the SG-MOSFET and DG-MOSFETs (4H-SiC and 6H-SiC) as shown in Fig. 5.
transistors in 4H-SiC and 6H-SiC technologies at the volt-
3.2 Subthreshold DG-MOSFET operation
age of VDS = 1.2 V and the voltages of VGS1 and VGS2
(VGS1 = VGS2 = VGS ) are varied from 0 V to 1.2 V. Among the features that demonstrate the quality of
The threshold voltage is directly proportional to the the electrical performance of the transistor is its oper-
energy gap Eg and is inversely proportional to the carrier ation in Sub-threshold. Figure 6 shows the evolution of
concentration n and according to the electronic proper- LOG(ID ) as a function of the VGS voltage for the differ-
ent DG-MOSFETs and SG-MOSFET transistors in 4H-
ties of the 4H-SiC and 6H-SiC semiconductors in Table 1.
SiC and 6H-SiC technologies at the voltage of VDS =
This is what makes the SG-MOSFET and DG-MOSFETs
1.2 V.
transistor in 6H-SiC technology are characterized by a low
The ION /IOFF ratio of the SG-MOSFET and DG-
value of the threshold voltage compared to others tran-
MOSFETs transistors by BSIM3v3 model is defined
sistors in 4H-SiC technology as shown in Fig. 5.
by [15]
For SG-MOSFET and parallel DG-MOSFET (Model 2) ION VDD
transistors with uniform substrate doping concentration, = exp (9)
IOFF ηVT
Journal of ELECTRICAL ENGINEERING 70 (2019), NO2 149

gm (mS) gm (mS)
(a) 28 (b)
8 DG-MOS(6H-SiC) Model 2
DG-MOS(4H-SiC) Model 2 24

6 20

16
SG-MOS(4H-SiC) SG-MOS(6H-SiC)
4
12

8 DG-MOS(6H-SiC) Model 1
2 DG-MOS(4H-SiC) Model 1
4

0
0 0.2 0.4 0.6 0.8 VGS (V) 1.2 0 0.2 0.4 0.6 0.8 VGS (V) 1.2

Fig. 7. Transconductance gm with VGS of SG-MOSFET and DG-MOSFET transistors in: (a) – 4h-SiC, and (b) – 6h-SiC technology

where VDD = VDS = 1.2 V is the supply voltage, VT illustrating the speed of the device to open [26], because
is the thermal voltage, and η is the subthreshold swing he is considered an important physical quantity to mea-
parameter. sure the conversion speed of the transistor from the off
Silicon-Carbide (SiC) is semiconductors with very low state to the open state [25, 26]. So that whenever the SS
value for carrier concentration n. This is what makes the is small, the transistor will open faster. According to this,
SG-MOSFET and DG-MOSFETs transistors of this tech- the Series DG-MOSFET (Model 1) transistor is will open
nology are characterized by an ultra low IOFF leakage slow compared to other transistors for different semicon-
current and are characterized by a very high ION /IOFF ductor technologies as shown in our results, and transis-
ratio of order 107 and 106 for the transistors in 6H-SiC tors in 6H-SiC technology are faster ON-OFF switching
and 4H-SiC respectively as shown in Table 1. Accord- compared to the transistors in 4H-SiC technology. That
ing to these results and based on (9), the transistors in is what makes the parallel DG-MOSFET and the tran-
4H-SiC technology are characterized by a high η sub- sistors in 6H-SiC technologies more suitability for digital
threshold swing parameter compared to the transistors applications.
in 6H-SiC technology, This allows it to be more optimal
for the design of electronic devices that operate in sub- 3.3 gm –V characteristic
threshold region. In order to study of a SG-MOSFET and DG-MOSFETs
The simulation results show that the series DG- transistors performances, the transconductance gm must
MOSFET transistor (Model 1) is characterized by an be studied, because it is considered among the most im-
ION /IOFF ratio 10 times lower than that SG-MOSFET portant analog performance parameter [27] and is deter-
and parallel DG-MOSFET (model 2) transistors for 4H- mined by the following relation
SiC and 6H-SiC technologies because it is characterized
by the highest value of the ION current compared to dID
gm = . (11)
other types of transistors as shown in Fig. 6. dVGS
The Subthreshold Slope (SS ) of a MOSFET transis-
tor is defined by the following relation, and is considered According to (11) and based on the drain current (6),
among the most important parameters the transconductance gm as a function of VGS of a SG-
MOSFET transistor for BSIM3v3 model is given by
dVGS
SS = . (10) Cox W VDS Esat  dµeff 
d LOG(ID ) gm (VGS ) = µeff + VGS . (12)
LEsat + VDS dVGS
The results presented in Table 2 show that the transis-
tors SG-MOSFET and DG-MOSFETs are characterized Figure 7 shows the effect of gate voltage VGS variation on
by a high subthreshold slope SS of order 86 mV/dec and transconductance gm evolution VGS of the SG-MOSFET
85 mV/dec for the transistors in 4H-SiC and 6H-SiC re- and DG-MOSFETs transistors in 4H-SiC and 6H-SiC
spectively compared to the ideal 60 mV/dec subthreshold technologies at Drain-Source voltage VDS = 1.2 V.
slope in room temperature [24, 25], this value corresponds The gm –V characteristic is extremely related with the
to the theoretical relationship SS = KB T /q ln(10) [25]. ID –VGS characteristic according to (11), and then both
This proves that these transistors are subject to tunnel characteristics have the same form of evolution, that is
effect in subthreshold operation, particularly the series to say the transconductance value of the parallel DG-
DG-MOSFET transistor (Model 1) to distinguish it with MOSFET transistor is high compared to the other tran-
the greatest subthreshold slope SS compared with the sistors for different semiconductor technologies.
rest of the transistors; this is consistent with the proper- The mobility µeff and derivative of mobility are
ties of the BSIM3v3 model. And since the SS parameter very important parameters that are directly proportional
150 M. Hebali et al : A HIGH ELECTRICAL PERFORMANCE OF DG-MOSFET TRANSISTORS IN 4H-SIC AND 6H-SIC 130NM . . .

Table 2. The different parameters of the SG-MOSFET and DG-MOSFET transistors in 4H-SiC and 6H-SiC technology

4H-SiC technology 6H-SiC technology


Transistors Series Parallel Series Parallel
SG-MOSFET DG-MOSFET SG-MOSFET DG-MOSFET
Electrical parameters (Model 1) (Model 2) (Model 1) (Model 2)
Vth (V) 0.97 1 0.97 0.7 0.78 0.7
IDsat (µA) * 4.7449 2.188 9.489 15.903 8.119 31.806
ION /IOFF ratio 3.92 × 106 1.81 × 106 3.92 × 106 1.31 × 106 6.70 × 106 13.1 × 106
SS (mV/dec) 86.134 87.349 86,134 85.498 86.493 85.498
gm (µS) ** 3.954 1.823 7.908 13.253 6.773 26.505
*( VGS = 1.2 V), **( VGS = VDS = 1.2 V)

to the variation of the VGS voltage in the BSIM3v3 threshold voltage and ultra low power than all other tran-
model [22, 23], and according to the expression of the sistors. As for the DG-MOSFET transistor in structure
transconductance gm (VGS ),this characteristic is increased parallel it is characterized by high ON/OFF ratio of order
by increasing the VGS voltage for the SG-MOSFET and 106 and faster ON-OFF switching like the SG-MOSFET
DG-MOSFETs transistors in 4H-SiC and 6H-SiC tech- transistor, high value of the transconductance and more
nologies as shown in the Fig. 7. efficient amplification compared to other transistors. The
The gm –V characteristic shows that the transconduc- DG-MOSFETs transistors that were studied in this work
tance gm of the different transistors in 4H-SiC technol- showed the high electrical performances in the static char-
ogy is lower and more linear (Above-threshold region) acteristics and in the subthreshold operation. Therefore,
compared to the transistors in 6H-SiC technology except these advantages make these transistors a suitable can-
the Parallel DG-MOSFET transistor in 4H-SiC and se- didate for analog and digital applications in low voltage
ries DG-MOSFET transistor in 6H-SiC which are char- and ultra low power with submicron technology.
acterized by transconductance of 7.908 µS and 6.773 µS
respectively as shown in Table 2. Since the transcon-
References
ductance gm is considered a measure of the amplifica-
tion given by these transistors [27]. That’s what makes
[1] R. S. Jay Hind Kumar Verma Subhasis Haldar, “Modeling Sim-
the transistors in 6H-SiC technologies and Parallel DG- ulation of Subthreshold behaviour of Cylindrical Surrounding
MOSFET transistor in 4H-SiC and 6H-SiC technologies Double Gate MOSFET for Enhanced Electrostatic Integrity, Su-
are characterized by more efficient amplification and more perlattices Microstructures 88, 354-364,.
suitability for analog applications. [2] ??? Ajay Rakhi Narang Manoj Saxena Mridula Gupta (2017),
“Modeling of gate underlap junctionless double gate MOSFET
Table 2 is a performance summary of the SG-MOSFET as bio-sensor, Materials Science in Semiconductor Processing 71,
and DG-MOSFETs transistors with Series and Paral- 240251,.
lel models in 4H-SiC and 6H-SiC technologies at room [3] ??? Edward Namkyu Cho Yong Hyeon Shin Ilgu Yun (2015),
temperature. Table 2 shows a presentation of the differ- “An analytical avalanche breakdown model for double gate
ent electrical parameters of the SG-MOSFET and DG- MOSFET, Microelectronics Reliability 55(1), 3841,.
MOSFETs transistors, and shows the comparison of the [4] D. Munteanu, J. L. Autran, and S. Moindjie (2017), “Sin-
gle-event-transient effects in Junctionless Double-Gate MOS-
electronic behavior between the two models of the DG-
FETs with Dual-Material Gate investigated by 3D simulation,
MOSFETs transistors and consequently the comparison Microelectronics Reliability 7677, 719-724,.
with the SG-MOSFET transistors. [5] ??? Debapriya Roy Abhijit Biswas (2017), “Asymmetric under-
lap spacer layer enabled nanoscale double gate MOSFETs for
design of ultra-wideband cascode amplifiers, Superlattices Mi-
4 Conclusion crostructures 110, 114-125,.
[6] P. Ramesh Vaddi Rajendra and T. Agarwal Sudeb Dasgupta
Tony, “Design Analysis of Double-Gate MOSFETs for Ul-
In this work, the electrical characteristics of series and tra-Low Power Radio Frequency Identification (RFID): Device
parallel DG-MOSFETs transistors in 4H-SiC and 6H-SiC Circuit Co-Design, Journal of Low Power Electronics Applica-
technologies have been investigated using equivalent elec- tions 1(3), 277-302,.
tronic circuits based on a BSIM3v3 model with 130 nm [7] ??? Sudarshana Jilowa Sandeep Singh Gill Gurjot Kaur Walia
technology. The structure type effect on electrical per- (2016), “Design of 3C-SiC Symmetric Asymmetric Double Gate
MOSFET, International Conference on VLSI Systems Architec-
formances of DG-MOSFET transistor have been stud- tures, Technology Applications (VLSI-SATA), 1-5,.
ied and carried out a comparative study between the re- [8] ??? Laurence Latu-romain Maelig Ollivier (2015), Silicon Car-
sults of the DG-MOSFETs and SG-MOSFET transistors. bide One-dimensional Nanostructures Edition 2015- WILEY-
The DG-MOSFET transistor in series structure has high ISTE London, United Kingdom,, 1-148.
Journal of ELECTRICAL ENGINEERING 70 (2019), NO2 151

[9] *. Laurence Latu-romain Maelig Ollivier (2015), “[, Hans-Erik with Silvaco Atlas Crosslight Apsys , Journal of Telecommuni-
Nilsson Kent Bertilsson, Ervin Dubaric, Mats Hjelm (2001) ”Nu- cations & Information Technology 7(3), 93-95,.
merical Simulation of Field Effect Transistors in 4H 6H-SiC” [18] C. A. Abdul Nazar and V. Kannan, “EFFECT OF DUAL GATE
Proceedings of IEEE, 3rd International Conference on Novel Ap- MOSFET ON THE DECODER BASED DEMULTIPLEXER,
plications of Wide Bandgap Layers, 199 200,. Journal of Theoretical Applied Information Technology 65(2),
[10] ??? Yashvir Singh Deepak Dwivedi (2016), “A power dual-gate 589-594,.
laterally-diffused MOSFET on 4HSiC, International Journal of [19] -. Prespice Update, “A SPICE Cookbook, Debuts SPICEMOD
Electronics Letters 5(4), 385-394,. Helps Model Dual-Gate Mosfets, Undocumented ISSPICE Op-
[11] D. Tournier, M. Vellvehi, P. Godignon, X. Jorda, and J. Milln tions (August 1991) http://www, intusoft, com/newsletters,
(2006), “ Double Gate 180V-128mA/mm SiC-MESFET for htm,.
Power Switch Applications, Materials Science Forum 527-529, [20] -. Prespice Update and *. Over 1000 New Models, “[, ] Viran-
1243-1246,. jay M, Srivastava Ghanshyam Singh (2014) ” MOSFET Tech-
[12] ??? Robert Mroczynski Norbert Kwietniewski Piotr Konarski nologies for Double-Pole Four-Throw Radio-Frequency Switch ”
(2017), “Effects of ultra-shallow ion implantation from RF Springer ACSP, Analog Circuits Signal Processing, 1-199,.
plasma onto electrical properties of 4H-SiC MIS structures with [21] R. Jacob Baker (2000), “CMOS Circuit Design, Layout, EEE
SiOx/HfOx SiOxNy/HfOx double-gate dielectric stacks, Micro- Series on Microelectronic Systems,.
electronic Engineering 178, 116121,.
[22] ??? Yuhua Cheng Chenming Hu (2002), “MOSFET MODEL-
[13] S. Suryadeepta Dash, B. Panda, and A. K. Maji, “Comparative ING & BSIM3 USERS GUIDE, University of California Berke-
Thermal Noise Analysis of DG MOSFET Using SiO2, SiC-SiO2, ley,.
Si3N4-SiO2, 2011 International Conference on Communication
[23] ??? Weidong Liu Xiaodongjin (2005), “ BSIM3V3. 3 MOSFET
Industrial Application,.
Users Manual, University of California Berkeley,.
[14] ??? Mourad Hebali Djilali Berbara Mohammed Benzohra Djilali
[24] *. Weidong Liu Xiaodongjin (2005), “[, ] Swagata Bhattacher-
Chalabi Abdelkader Saidane Abdelkader Baghdad Bey (2017),
jee Abhijit Biswas (2008) ”Modeling of threshold voltage sub-
“MOSiC (3C, Journal of Engineering Science Technology Review
threshold slope of nanoscale DG MOSFETs” SEMICONDUC-
10(5), 195-198,.
TOR SCIENCE AND TECHNOLOGY 23(1), 1-8,.
[15] *. Mourad Hebali Djilali Berbara Mohammed Benzohra Djilali
Chalabi Abdelkader Saidane Abdelkader Baghdad Bey (2017), [25] ??? Jean-pierre Colinge Chi-woo Lee Aryan Afzalian Nima De-
“[, ] Mourad Hebali Djilali Berbara, Mohammed Benzohra, hdashti Akhavan Ran Yan Isabelle Ferain Pedram Razavi Bren-
Djilali Chalabi Abdelkader Saidane (2018) ” A Comparative dan Oneill Alan Blake Mary White Anne-marie Kelleher Bren-
Study on Electrical Characteristics of MOS (Si0, 5Ge0, 5) MOS dan Mccarthy Richard Murphy (2010), “Nanowire transistors
(4H-SiC) Transistors in 130nm Technology with BSIM3v3 Model without junctions, Nature Nanotechnology 5(3), 225-229,.
” International Journal of Advances in Computer Electronics [26] ??? Wu Meile Jin Xiaoshi Chuai Rongyan Liu Xi Jong-ho Lee
Engineering, 3(9), 16,. (2013), “ Simulation study on short channel double-gate junc-
[16] ??? Mourad Hebali Djilali Berbara Miloud Abboun Abid Mo- tionless field-effect transistors, Journal of Semiconductors 34(3),
hammed Benzohra Djilali Chalabi Abdelkader Saidane Mo- 034004, 1-8,.
hammed Berka (2018), “ An Ultra Low power High Performance [27] ??? Reza Hosseini (2015), “Analysis Simulation of a Junctionless
of CMOS (6H-SiC) Current Mirrors in BSIM3v3 130nm Technol- Double Gate MOSFET for High-speed Applications, Journal of
ogy , International Journal of Advances in Computer Electronics the Korean Physical Society 67(9), 1615-1618,.
Engineering 3(11), 18,.
[17] L. Jedrzej Steszewski Andrzej Jakubowski Michael, “ Copmari- Received 8 July 2018
son of 4H-SiC 6H-SiC MOSFET I-V characteristics simulated

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