5nm CMOS Production Technology Platform featuring full-fledged EUV, and

High Mobility Channel FinFETs with densest 0.021m2 SRAM cells for
Mobile SoC and High Performance Computing Applications
Geoffrey Yeap, S.S. Lin, Y.M. Chen, H.L. Shang, P.W. Wang, H.C. Lin, Y.C. Peng, J.Y. Sheu, M. Wang, X. Chen, B.R. Yang,
C.P. Lin, F.C. Yang, Y.K. Leung, D.W. Lin, C.P. Chen, K.F. Yu, D.H. Chen, C.Y. Chang, H.K. Chen, P. Hung, C.S. Hou, Y.K.
Cheng, J. Chang, L. Yuan, C.K. Lin, C.C. Chen, Y.C. Yeo, M.H. Tsai, H.T. Lin, C.O. Chui, K.B. Huang, W. Chang, H.J. Lin,
K.W. Chen, R. Chen, S.H. Sun, Q. Fu, H.T. Yang, H.T. Chiang, C.C. Yeh, T.L. Lee, C.H. Wang, S.L. Shue, C.W. Wu, R. Lu,
W.R. Lin, J. Wu, F. Lai, Y.H. Wu, B.Z. Tien, Y.C. Huang, L.C. Lu, Jun He, Y. Ku, J. Lin, M. Cao, T.S. Chang, S.M. Jang

Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. Email: gyeap@tsmc.com

Abstract industry-leading 5nm platform technology is one such

A leading edge 5nm CMOS platform technology has
been defined and optimized for mobile and HPC
applications. This industry-leading 5nm technology
features, for the first time, full-fledged EUV, and high
mobility channel (HMC) finFETs with densest 0.021m2
HD SRAM. This true 5nm CMOS platform technology
is a full node scaling from our successful 7nm node [4] in
offering ~1.84x logic density, 15% speed gain or 30%
power reduction. The 5nm platform technology
successfully passed qualification [3] with consistently
high yielding 256Mb HD/HC SRAM, and large logic test
chip consisting of CPU/GPU/SoC blocks. Currently in
risk production, this true 5nm platform technology is on
schedule for high volume production in 1H 2020.
Introduction
Innovative products have been the driving force behind
the semiconductor industry growth in the past fifty years.
Specifically in the past decade, mobile SoC in 3G/4G
smartphones has driven an explosive growth in the
industry [1]. With 5G deployment starting in 2019,
mobile SoC as an industry driving force will rise to the
next level. Furthermore, with the addition of HPC
applications such as A.I., data center, and block-chain
products, the twin engines of 5G mobile SoC and HPC
Al/Data-center are propelling another period of sustained
growth in the next decade [2]
Advanced CMOS logic technology has been the key
enabler for semiconductor product innovations as shown
in Figure 1. Logic technology such as 28nm and
16/12nm are key enablers for smartphone and 4G. The
ongoing industry growth, powered by 5G mobile and
HPC AI, has ignited the industry with an insatiable
appetite for best-in-class advanced logic technology with
the highest performance and best power efficiency. Our
advanced logic technology. This 5nm platform
technology successfully completed the full 1000 hours of
HTOL qualification with high yielding 256Mb HD/HC
SRAM and large logic test chip [3]. This true 5nm
platform technology is now in risk production going to
mass production in the first half of year 2020.
In this paper, we report how the true 5nm technology
is defined with crucial features like EUV and high
mobility channel transistors, and optimized upfront to
meet the seemingly competing requirements of best
power efficiency by 5G mobile SoC, and high
performance needed by the HPC AI/CPU/GPU products.
5nm Platform Technology Architecture
The 5nm technology is defined and developed to meet
PPACT (Power, Performance, Area, Cost, and Time-to-
market). Design-Technology Co-Optimization (DTCO)
is emphasized with smart hyper scaling features instead
of brute-force scaling of design rules which drastically
increases process cost and causes fundamental yield
issues. Extensive DTCO coupled with smart scaling of
major design rules (e.g. gate, fin and Mx/Vx pitches) was
performed in optimizing this true 5nm technology to
achieve 35%~40% chip size reduction with attractive
PPA values at cost projection and on schedule. Smart
hyper scaling features used include innovative
implementation of gate-contact-over-active and unique
diffusion termination for extra logic density, and EUV
based gate patterning process (see Table 1) for SRAM
cell size reduction and logic density. The 5nm
technology, shown in Figure 2, offers 15% faster speed at
same power or 30% power reduction at same speed with
1.84x logic density of 7nm node [4]. Assuming a mobile
SoC having 60% logic, 30% SRAM and 10% IO/analog,
this 5nm technology scaling is projected to reduce chip

978-1-7281-4032-2/19/$31.00 ©2019 IEEE 36.7.1 IEDM19-879

 size by 35%~40%. Innovative approach of offering up to
seven Vt’s for each transistor type enables product design
to meet the needs of power efficiency in mobile SoC, and
peak speed requirements in HPC. The 5nm platform
technology also offers a set of critical HPC features such
as extremely low Vt (eLVT) for 25% peak speed over
7nm, and HPC 3-fin standard cells for additional 10%
performance gain (see Figure 3).
Full-fledged EUV (i.e., more than ten EUV layers) is
employed to replace at least 4 times more immersion
layers at cut, contact, via and metal line masking steps
for process simplification, faster cycle time and better
reliability & yields. Total mask count is reduced for the
first time in the 5nm node which uses several masks less
than previous 7nm node as seen in Figure 4. Figure 5
shows an example on how one EUV mask replacing five
immersion masks yet producing better patterning fidelity,
shorter cycle time, and less defects.
HMC FinFETs and Backend Interconnect
Four generations of Si finFets have been in use from
16nm node to 7nm. FinFet performance has been
stagnant, and high mobility channel is employed to yield
much needed drive current enhancement. Figure 6 shows
excellent Id-Vg characteristics of HMC finFets. Figure-
of-merit (FOM) ring oscillator standby power also
correlates well to transistor leakages. HMC finFET with
higher mobility is shown to produce ~18% more drive
current than the Si finFET. TEM shows fully-strained
HMC lattice constant interfaced with Si lattice constant.
Diffraction pattern confirmed HMC strain (see Figure 7).
Overall technology performance is also critically
dependent on backend metal RC and via resistance.
Tightest pitch Mx RC and Vx Rc kept relatively similar
to previous 7nm node as shown in Figure 8 by using
EUV patterning, innovative scaled barrier/liner,
ESL/ELK dielectrics, and Cu reflow
SRAM, Logic Test Chip, and Reliability
As sram memory usage is increasing in HPC AI and as
L3/system memory in mobile SoC, SRAM density and
performance/leakage become more crucial. Two basic
SRAM cells such as 0.025m2 high current (HC) and
0.021m2 high density (HD) are offered. Literature
survey in Figure 9 indicates that the 0.021m2 HD
SRAM in this true 5nm technology is the densest one
reported. Two instances of 256Mb HD and HC sram
along with large logic test chip are included in the 5nm
IEDM19-880 36.7.2
qualification vehicle. This 5nm has consistently
achieved very high yield in 256Mb SRAM and logic test
chip: >90% peak yield and ~80% average yield (without
repair) in 256Mb HC and HD sram. Figure 10 indicates
that the ultra-low leakage ULHD may be used to reduce
retention leakage for better power efficiency while higher
speed HSHD sram may be used to replace as many HC
sram as memory speed specification allows for ~22%
memory area reduction. Figure 11 shows the shmoo plot
of 256Mb 0.021m2 HD SRAM with full read/write
function down to 0.4V. Figure 12 shows shmoo plots of
CPU/GPU blocks in the high yielding logic test chip.
Both the 256Mb HD/HC SRAM and logic test chip
passed 1000 hour HTOL qualification. HD/HC SRAM
Vmin exhibits negligible shift at 168 hour, and passed
1000 hour HTOL with ~51mV margin (Fig. 13). Aging
stress data on the 5nm figure-of-merit ring oscillator
made with HMC finFETs shows better aging lifetime
over previous 7nm node.
Additional HPC features such as super high density
(SHD) MiM, which has 4x higher capacitance density
than typical HD-MiM, produces ~4.2% faster Fmax by
minimizing transient drooping voltage, and achieves
~20mV Vmin reduction in a CPU test chip (Figure 15).
Another critical HPC IP such as high speed SERDES
was successfully developed by optimizing finFET
driving strength, and capacitance/resistance by using
special purpose high speed devices. Figure 16 shows that
the PAM 4 transmitter demonstrating highest speed of
130 Gb/s with 0.96pJ/bit and nominal 112Gb/s with 0.78
pJ/bit energy efficiency [5].
Acknowledgement
We would like to thank the close collaboration among
N5PD, ATMD, NPTD, DTP, YEP, Q&R, TMLD, TCAD,
PED and PFD as well as excellent wafer processing
support from RDPC and F12B. Excellent executive
management support from Y.J. Mii, W.J. Lo, Y.P. Chyn,
and Cliff Hou is much appreciated.
References
[1] G. Yeap, IEDM, p.1.3.1, 2013.
[2] “TSMC Expects High Performance Computing to be the
Fastest Growing Segment,” Top500 Supercomputer sites.
[3] “TSMC’s 5nm process is already in risk production. TSMC
and OIP Ecosystem Partners Deliver Industry’s First
Complete Design Infrastructure for 5nm Process
Technology”, TSMC press release on April 3, 2019.
[4] S.-Y. Wu et al., IEDM, p.2.6.1, 2016.
5 W.-C. Chen et al., submitted to ISSCC, 2020.
 Fig.5 One EUV replacing 5 immersion patterning with better
Fig.1 Advanced CMOS technology has been the key enabler patterning fidelity, shorter cycle time and less defects
for innovations: 28nm and 16nm for smartphone and 4G while
7nm and 5nm unleashing product innovations for AI and 5G.

Fig.6 5nm high mobility channel finFETs showing excellent

Fig.2 This true 5nm technology offers 15% speed at same
Id-Vg characteristics. FOM ring oscillator standby power
power or 30% power reduction at same speed with 1.84x
correlated well to transistor leakages.
logic density over 7nm. Up to seven Vt’s to meet max power
efficiency for mobile, and peak speed in HPC. Silicon data
close to fully matching F.O.M. ring speed vs stand-by power

Fig.7 ~18% performance gain with HMC vs Si finFET. TEM

Fig.3 The 5nm also offers a set of critical HPC features. showing fully-strained HMC lattice constant interfaced with Si
Extremely LVT (eLVT) for 25% faster peak speed over 7nm, lattice constant. Diffraction pattern confirmed HMC strain.
and HPC 3-fin standard cell for additional 10% performance.

Fig.8 5nm tightest pitch Mx RC and Vx Rc kept relatively

Fig.4 Total mask count reduction, seen for the first time in
similar to previous 7nm node by EUV patterning, innovative
5nm node, is enabled by full-fledged use of EUV
scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow

36.7.3 IEDM19-881
 Table 1 HD/HC sram with more shrink, and better DIBL/Vt-
sigma (Vmin) enabled by EUV based new process

Fig.13 5nm HD/HC SRAM and logic test chip passed 1000
hour HTOL qualification. SRAM Vmin showing negligible
shift at 168 hour, and passed 1000 hour with ~51mV margin.

Fig.9 0.021m2 HD SRAM in 5nm is the densest one reported

Fig.14 The 5nm HMC FOM ring oscillators showing better

aging lifetime with high Vdd stress than previous 7nm node.

Fig.10 Ultra low leakage ULHD for better power efficiency,

while high speed HSHD to replace more HC sram for better
area scaling. Butterfly curves of HD SRAM down to 0.3V

Fig.15 Super high density (SHD) MiM, which has 4x higher

capacitance density than typical HD-MiM, yields ~4.2% faster
Fmax, and ~20mV Vmin reduction in a CPU test chip

Fig.11 Shmoo plot of 256Mb 0.021m2 SRAM down to 0.4V.

Fig.16 High speed PAM-4 transmitters build in a 5nm test chip

demonstrate highest speed of 130Gb/s with 0.96pJ/bit and
nominal 112Gb/s with 0.78pJ/bit energy efficiency [5]
Fig.12 Shmoo plots of CPU/GPU blocks in a high yielding
large logic test chip in 5nm qualification vehicle.

IEDM19-882 36.7.4