KULLIYYAH OF ENGINEERING

END-OF-SEMESTER EXAMINATION

SEMESTER 2, 2014/2015 SESSION

Programme : CIE & CE Engineering Level of Study : UG 2

Time : 2.30 pm -5.30 pm Date : 23-5-2015
Duration : 3 Hours
Course Code : ECE 2111 Section(s) :1&2
Course Title : Digital Logic Design

This Question Paper Consists of 5 (Five) Printed Pages (Including Cover Page) with 6
(Six) Questions.

INSTRUCTION(S) TO CANDIDATES

DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO

 Total mark of this examination is 100.

 This examination is worth 50 % of the total course assessment.
 There are two sections, answer ALL Questions from Section A and ONLY 1 (one)
Question from Section B.
 Only approved calculator with ‘KoE approved’ sticker is allowed (non-
programmable and non-graphical).
 Marks assigned to each question are listed in the margin.
Any forms of cheating or attempt to cheat is a serious offence which
may lead to dismissal.

All electronics gadgets are prohibited in the exam hall / venue.

(e.g. mobile / smart phones, smart watches, and smart glasses)
Digital Logic Design ECE 2111

Section One (answer ALL questions)

QUESTION 1 (20 marks)

(a) Explain why is it recommended to use standard logic instead of BIT as data type
in VHDL? (3)

(b) Explain what is meant by Test Bench (3)

(c) Convert the number (24CE) 16 to Octal, Decimal, and then code it into BCD. (6)

(d) Write the equivalent decimal for the following numbers (4)

(i) 111011112 (in two’s complement representation)

(ii) 110101012 (in signed-magnitude representation)

(e) Using Boolean algebra, simplify the following terms: (4)

(i) Z = (A/ ( A  B/ )) ( A + ( A  B/))

(ii) F= ( X/.Y/.Z)/ + (X.Y.Z/)/

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Digital Logic Design ECE 2111

QUESTION 2 (20 marks)

(a) Design a logic circuit whose output is HIGH only when a majority of inputs A, B,
and C are LOW. Draw the circuit using all NAND gates. (8)

(b) Describe the internal architecture of a ROM that stores 4K bytes and uses a square
register array. (7)

(c) Using K-map, find a minimal sum of products expression for the following logic
function, indicate the distinguished 1-cells. (5)

F= ∏X, Y, W, Z (4, 6, 7, 12, 14, 15)

QUESTION 3 [20 marks]

(a) Using MUX, design a circuit that has the following min-term: (6)

F = ∑(A,B,C,D) (1,3,4,11,12,13,14,15), use the variables (A, B & C) as the selector.

(b) Assume that we have a counter that resets to 0000 on the tenth pulse and starts
over again. In other words, the output will never represent a number greater than
10012 = 910. Design the logic circuit that produces a HIGH out put whenever the
count is 2,3, 0r 9. Use K-map and take advantage of the don’t-care conditions. (7)

(c) Fig. 3 (c) shows a diagram for an automobile alarm circuit used to detect certain
undesirable conditions. The three switches are used to indicate the status of the
door by the driver’s seat, the ignition, and the headlights, respectively. Design the
logic circuit with these three switches as inputs so that the alarm will be activated
whenever either of the following conditions exits:
 The headlights are on while the ignition is off.
 The door is open while the ignition is on. (7)

Fig. 3 (c)

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Digital Logic Design ECE 2111

QUESTION 4 [20 marks]

(a) Construct the transition output table equivalent to the state diagram shown in
Fig. 4(a) (6)

Fig. 4(a)

(b) Derive the characteristic equation of the K-J flip flop and, Write a VHDL code to
describe its behavior. (6)

(c) Analyze the clocked synchronous state machine shown in Fig. 4 (c). Write the
excitation equations, excitation/transition table, and the state/output table (use
state names A-D for QA QB = 00 – 11). (8)

Fig. 4 (c)

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Digital Logic Design ECE 2111

Section Two (answer ONLY one question)

QUESTION 5 [20 marks]
(a) Consider MOD-16 Asynchronous down counter: (8)
(i) Construct the state transition diagram for this counter.

(ii) If the counter is initially in the 0110 state, what state will it be in after 37
clock pulses?

(b) Analyze the synchronous counter shown in Fig. 5 (b). Construct the state
diagram of the counting sequence of the counter. (12)

Fig. 5 (b)

QUESTION 6 [20 marks]

(a) Construct MOD-17 asynchronous counter. Determine the output frequency if the
input frequency is 30 KHz. If the counter is initially in the 00110 state, what state
will it be after 37 clock pulses? (5)

(b) Assuming the above counter starts in (0) state, what will be the count after 144
input pulses? (3)

(c) Design a 3-bit synchronous counter using D-flip flop that has the counting
sequence shown in Fig. 6 (c). (12)
Unused states
S5 S6
101 110
S4 S7
011 111
S0
000

S3 Main sequence S1
100 001

S2
010
Fig. 6 (c)