Laboratory Manual: Digital Electronics

Enrollment No:
LABORATORY MANUAL
DIGITAL ELECTRONICS
Subject Code: 1330302
Integrated M.Sc. SEM. III (Computer Science), Year 2022-23 (Odd Semester)
DEPARTMENT OF COMPUTER ENGINEERING
Gujarat Power Engineering and Research Institute, Mehsana

(A constituent college of Gujarat Technological University)
Near Toll Booth, Ahmedabad-Mehsana Express way, Village-Mewad
District: Mehsana - 382710 (Gujarat)
Contact No. +91-2762-285875/71
GUJARAT POWER ENGINEERING AND RESEARCH
INSTITUTE, MEHSANA
DEPARTMENT OF COMPUTER ENGINEERING
CERTIFICATE
This is to certify that Mr./Ms.________________________________

Enrollment No. ___________________ of semester _____________________has
satisfactorily completed the laboratory work in the course
_____________________________________ within the four walls of the Institute.
Date of submission:
Faculty In-charge Head of Department

Gujarat Power Engineering and Research Institute, Mehsana
Integrated M.Sc. SEM. III (Computer Science), Year: 2022-23 (ODD Semester)
Subject Name: Digital Electronics, Subject Code: 1330302
INDEX
PAGE
Sr.
TITLE DATE SIGN REMARK
No. FROM TO
Study of the operation of OR, AND, NOT,
1 NAND, NOR, XOR, XNOR gate and to verify
its truth table.
To design NOT, OR, AND Gate using NAND
2
and NOR Gate.
3 To verify De Morgan’s Theorem.
To study and verify Truth Table of Binary

4
Half Adder, Full Adder and Half Subtractor.
To study and verify the truth table of 4-to-1
5 Line Multiplexer and 1-to-4 Line
Demultiplexer.
To study and verify the Truth Table of 8-to-3
6
Line Encoder and 3-to-8 Line Decoder.
Study of 4-bit serial in serial out shift register.
7
Study of 3-bit serial in serial out shift register.
Study of 4-bit serial in parallel out shift
8 register. Study of 3-bit serial in parallel out
shift register.
Study of 4-bit parallel in serial out shift
9 register. Study of 3-bit parallel in serial out
shift register.
Study of 4-bit parallel in parallel out shift
10 register. Study of 3-bit parallel in parallel out
shift register.
Study of 4-bit synchronous binary up counter.
11
Study of 4-bit binary ripple up/down counter.
Logic Gates Trainer
NV6551
Learning Material
Ver 1.1
141-B, Electronic Complex,

Pardeshipura, Indore- 452 010 India
Tel.: 91-731- 4211500
Email: info@nvistech.com
Toll free: 1800-103-5050
NV6551
Logic Gates Trainer

NV6551
Table of Contents
1. Introduction 3
2. Features 4
3. Theory 5
4. Experiments
Experiment 1 11
Study of the operation of OR gate and to verify its truth table
Experiment 2 13
Study of the operation of AND gate and to verify its truth table
Experiment 3 15
Study of the operation of NOT gate and to verify its trurh table
Experiment 4 17
Study of the operation of NAND gate and to verify its truth table
Experiment 5 19
Study of the operation of NOR gate and to verify its truth table
Experiment 6 21
Study of the operation of XOR gate and to verify its truth table
Experiment 7 23
Study of the operation of XNOR gate and to verify its truth table
5. Datasheet 25
6. Warranty 31
7. List of Accessories 31
Nvis Technologies Pvt. Ltd. 2

NV6551
Experiment 1
Objective :
Study of the operation of OR gate and to verify its truth table.
Logic Diagram & Truth Table :
(Logic 1 = +5 V & Logic 0 = GND)
Truth Table :
X Y Z
0 0 0
0 1 1
1 0 1
OR Gate 1 1 1
Figure 4
Circuit Diagram :
Figure 5

NV6551
Procedure:
1. Connect inputs D0 and D1 as inputs of OR gate, A and B, and connect output Y
to the D7 of output section LED.
2. Plug in the +5V DC adaptor into the trainer and switch on the power supply.
3. Now set switch D0 and D1 of input section to OFF, this will show logic 00 and
observe the output Y at D7’s LED.
4. Record your observation into the observation table.
5. Similarly set different combinations of A and B like AB=01, AB=10 and
AB=11 and record the corresponding outputs into the observation table.
Now match your observation table with the Truth table of OR gate.
Observation Table:
A(D0) B(D1) Y(D7)

NV6551
Experiment 2
Objective :
Study of the operation of AND gate and to verify its truth table.
Truth Table X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
Figure 6
Circuit Diagram :
Figure 7

NV6551
Procedure :
1. Connect inputs D0 and D1 as inputs of OR gate, A and B, and connect output Y
to the D0 of output section LED.
5. Similarly set different combinations of A and B like AB=01,AB=10 and AB=11
and record the corresponding outputs into the observation table.
6. Now match your observation table with the Truth table of AND gate.
Observation Table :
A(D0) B(D1) Y(D0)

NV6551
Experiment 3
Objective :
Study of the operation of NOT gate and to verify its truth table.
Logic Diagram & Truth Table:
Truth Table :
X Z
0 1
1 0
Figure 8
NOT Gate :
Circuit Diagram :
Figure 9

NV6551
Procedure :
1. Connect input D0 of input section to the input A of NOT gate, and connect
output Y to the D0 of output section.
3. Now set switch input of NOT gate (D0 of input section) to 0 and observe the
output Y (D0 of output section).
5. Now set input to 1 and observe the output.
6. Now match your observation table with the Truth table of NOT gate.
Observation Table :
A(D0) B(D1) Y(D0)

NV6551
Experiment 4
Objective :
Study of the operation of NAND gate and to verify its truth table.
Truth Table :
X Y Z
0 0 1
0 1 1
.
1 0 1
1 1 0
NAND Gate :
Figure 10
Circuit Diagram :
Figure 11

NV6551
Procedure :
1. Connect inputs D0 and D1 as inputs of NAND gate, A and B, and connect
output Y to the D0 of output section LED.
6. Now match your observation table with the Truth table of NAND gate.
Observation Table :
A(D0) B(D1) Y(D0)

NV6551
Experiment 5
Objective:
Study of the operation of NOR gate and to verify its truth table.
Truth Table:
X Y Z
0 0 1
0 1 0
. 1 0 0
1 1 0
NOR Gate
Figure 12
Circuit Diagram :
Figure 13

NV6551
Procedure :
1. Connect inputs D0 and D1 as inputs of NOR gate, A and B, and connect output
Y to the D7 of output section LED.
6. Now match your observation table with the Truth table of NOR gate.
Observation Table :
A(D0) B(D1) Y(D0)

NV6551
Experiment 6
Objective :
Study of the operation of XOR gate and to verify its truth table.
Truth Table
X Y Z
0 0 0
0 1 1
. 1 0 1
1 1 0
Figure 14
XOR Gate
Circuit Diagram :
Figure 15

NV6551
Procedure :
1. Connect inputs D0 and D1 as inputs of XOR gate, A and B, and connect output
Y to the D0 of output section LED.
6. Now match your observation table with the Truth table of XOR gate.
Observation Table :
A(D0) B(D1) Y(D0)

NV6551
Experiment 7
Objective :
Study of the operation of XNOR gate and to verify its truth table.
Truth Table
X Y Z
0 0 1
0 1 0
XNOR Gate
1 0 0
1 1 1
Figure 16
Circuit Diagram :
Figure 17

NV6551
Procedure :
1. Connect inputs D0 and D1 as inputs of XNOR gate, A and B, and connect
output Y to the D0 of output section LED.
6. Now match your observation table with the Truth table of XNOR gate.
Observation Table :
A(D0) B(D1) Y(D0)

Universal Gates Trainer
NV6552
Learning Material
Ver 1.0
Designed & Manufactured by:
141-B, Electronic Complex, Pardesipura, Indore- 452 010 India, Tel.: 91-731- 4211500,
Telefax: 91-731-4202959, Toll free: 1800-103-5050, E-mail: info@nvistech.com
Website: www.nvistech.com
NV6552
Universal Gates Trainer

NV6552
Table of Contents
1. Introduction 3
2. Features 4
3. Theory 5
4. Experiments
 Experiment 1 6
To design NOT Gate using NAND Gate
 Experiment 2 8
To design AND Gate using NAND Gate
 Experiment 3 10
To design OR Gate using NAND Gate
 Experiment 4 12
To design NOT Gate using NOR Gate
 Experiment 5 14
To design AND Gate using NOR Gate
 Experiment 6 16
To design OR Gate using NOR Gate
5. Datasheet 18
6. Warranty 24

NV6552
Experiment 1
Objective:
To design a NOT gate using NAND gate and to verify its truth table with conventional
NOT gate.
Truth table of a NOT gate:
A Y
0 1
1 0
Circuit diagram:
Fig. 2

NV6552
Procedure:
1. First connect input A of NAND1 to its input B.
2. Now Connect input D0 of input section to either A or B of NAND1.
3. Connect output of NAND1 (Y) to D0 of output section.
4. Plug in the 5V DC adaptor into the trainer and switch on the power supply.
5. Now set D0 of input section to 0.
7. Now set D0 to 1 and record output into the observation table.
8. Now compare your observation table with the Truth table of Conventional NOT gate.
Observation Table:
D0(A/B) Y(D0)

NV6552
Experiment 2
Objective:
To design an AND gate using NAND gates and to verify its truth table with
conventional AND gate.
Truth table of an AND gate:
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Logic diagram:
Fig. 3

NV6552
Procedure:
1. Connect input D0 of input section to input A of NAND2 and D1 to its input B.
2. Connect output of NAND2, which is (A.B)’ to input of NAND3, which is nothing but
a NOT using NAND.
3. Connect output of NAND3(Y) to the D0 of output section.
5. Now set A and B as 00 respectively by switching D0 and D1 to 0.
7. Similarly set other combinations of A and B like 01, 10, 11 and record corresponding
outputs into the observation table.
8. Now compare your observation table with the Truth table of Conventional AND gate.
Observation Table:
A B Y

NV6552
Experiment 3
Objective :
To design an OR gate using NAND gates and to verify its truth table with
conventional OR gate.
Truth table of an OR gate:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Circuit diagram:
Fig. 4

NV6552
Procedure :
1. Connect input D0 of input section to input A of NAND4.
2. Connect input D1 of input section to input B of NAND5.
3. Connect output of NAND4, which is A’ to the first input of NAND6.
4. Connect output of NAND5, which is B’ to the second input of NAND6.
5. Connect output of NAND6 (Y) to the D0 of output section.
10. Now compare your observation table with the Truth table of Conventional OR gate.
Observation Table :
A B Y

NV6552
Experiment 4
Objective :
To design a NOT gate using NOR gate and to verify its truth table with conventional
NOT gate.
Truth table of a NOT gate :
A Y
0 1
1 0
Circuit diagram :
Fig. 5

NV6552
Procedure :
1. First connect input A of NOR 1 to its input B.
2. Now Connect input D0 of input section to either A or B of NOR 1.
3. Connect output of NOR 1 (Y) to D7 of output section.
5. Now set D0 of input section to 0.
7. Now set D0 to 1 and record output into the observation table.
8. Now compare your observation table with the Truth Table of Conventional NOT
gate.
Observation Table :
D0(A/B) Y(D7)

NV6552
Experiment 5
Objective :
To design an OR gate using NOR gates and to verify its truth table with conventional
OR gate.
Truth table of an OR gate :
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Circuit diagram :

NV6552
Procedure :
1. Connect input D0 of input section to input A of NOR 2 and D1 to its input B.
2. Connect output of NOR2, which is (A+B)’ to input of NOR 3, which is nothing but a
NOT using NAND.
3. Connect output of NOR3(Y) to the D7 of output section.
8. Now compare your observation table with the Truth table of Conventional OR gate.
Observation Table :
A B Y

NV6552
Experiment 6
Objective :
To design an AND gate using NOR gates and to verify its truth table with
conventional AND gate.
Truth table of a AND gate:
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Circuit diagram :
Fig. 6

NV6552
Procedure :
1. Connect input D0 of input section to input A of NOR 4.
2. Connect input D1 of input section to input B of NOR 5.
3. Connect output of NOR 4, which is A’ to the first input of NOR 6.
4. Connect output of NOR 5, which is B’ to the second input of NOR 6.
5. Connect output of NOR 6 to D7 of output section.
10. Now compare your observation table with the Truth table of Conventional AND gate.
Observation Table:
A B Y

De-Morgan’s Theorem
NV6553
Learning Material
Ver 1.0

Pardeshipura, Indore- 452 010 India
Tel.: 91-731- 4211500
Email: info@nvistech.com
Toll free: 1800-103-5050
NV6553
De-Morgan’s Theorem
NV6553
Table of Contents
1. Introduction 3
2. Features 4
3. Theory 5
4. Experiments
Experiment 1 13
To verify (A+B)’=A’.B’
Experiment 2 16
To verify (A.B)’=A’+B’
5. Datasheet 19
6. Warranty 24

NV6553
Experiment 1
Objective :
To verify (A+B)’=A’.B’.
Circuit Diagram :
Fig. 18
Procedure :
L.H.S. [(A+B)’]
1. Connect input section’s D0 and D1 as inputs of OR1 gate, A and B.
2. Its output will be (A+B), connect this to the input of NOT1 gate.
3. Connect the final output Y to D0 of output section.
5. Now set switch D0 and D1 of input section to Off, this will show logic 00 and
observe the output Y at D0’s LED of output section.

NV6553
Observation Table :
A(D0) B(D1) Y(D0)
Circuit diagram :
Fig. 19
Procedure :
R.H.S. [A’.B’]
1. Connect D0 of input section to the input of NOT2 as A.
2. Connect D1 of input section to the input of NOT3 as B.
3. Connect output of NOT2, which is A’ to the first input of AND1.
4. Connect output of NOT3, which is B’ to the second input of AND1.
5. Connect output of AND1 Y to the D0 of output section.

NV6553
6. Now initially set both A and B to 00 respectively i.e. both the switches will be
off.
7. Observe the output Y at D0 and record it into the observation table.
8. Similarly set different combinations of A and B like 01, 10 and 11, record
corresponding outputs in each case.
9. Now compare the tables of L.H.S and R.H.S, since output column of both the
tables is same hence the given expression is verified.
Observation Table :
A(D0) B(D1) Y(D0)

NV6553
Experiment 2
Objective :
To verify (A.B)’=A’+B’.
Circuit diagram :
Fig. 20
Procedure :
L.H.S. [(A.B)’]
1. Connect input section’s D0 and D1 as inputs of AND2 gate, A and B.
2. Its output will be (A.B), connect this to the input of NOT4 gate.
3. Connect the final output Y to D7 of output section.
observe the output Y at D7’s LED of output section.
7. Similarly set different combinations of A and B like AB=01,AB=10 and AB=11
and record the corresponding outputs into the observation table.

NV6553
Observation Table :
A(D0) B(D1) Y(D7)
Circuit diagram :
Procedure :
R.H.S. [A’+B’]
1. Connect D0 of input section to the input of NOT5 as A.
2. Connect D1 of input section to the input of NOT6 as B.
3. Connect output of NOT5, which is A’ to the first input of OR2.
4. Connect output of NOT6, which is B’ to the second input of OR2.
5. Connect output of OR2 Y to the D7 of output section.

NV6553
6. Now initially set both A and B to 00 respectively i.e. both the switches will be
off.
7. Observe the output Y at D7 and record it into the observation table.
8. Similarly set different combinations of A and B like 01, 10 and 11, record
corresponding outputs in each case.
Observation Table :
A(D0) B(D1) Y(D7)

Adders and Subtractors Trainer
NV6554
Learning Material
Ver 1.0

Pardesipura, Indore- 452 010 India
Tel.: 91-731- 4211500
E-mail: info@nvistech.com
Toll free No. : 1800-103-5050
NV6554
Adders and Subtractors Trainer

NV6554
Table of Contents
1. Introduction 3
2. Theory 4
3. Experiments
Experiment 1 5
Study of Binary Half Adder
Experiment 2 8
To study and verify Truth Table of Binary Full Adder
Experiment 3 10
Study and verify Truth Table of Binary Half Subtractor
4. Datasheet 13
5. Warranty 17

NV6554
Experiment 1
Objective:
To study and verify Truth Table of Binary Half Adder.
(Logic 1 = +5 V & Logic 0=GND)
Figure 1
X Y Ch Sh
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

NV6554
Circuit Diagram:
Figure 2
Procedure:
1. First make sure that switches of input and output sections are Off.
2. Connect +5 V adaptor on the DC socket provided on the trainer.
3. Connect bits D0 and D1 of input section to the inputs of Half Adder 1 as A and B.
4. Connect Sum of Half adder1 at D0 of output section and Carry to the D1 of output
section.
5. Switch On the power supply.
6. Initially since both of the inputs D0 and D1 of input section are at Off position i.e.
input is A=0 and B=0. In this case observe the output (Sum and Carry) and record
in observation table.
7. Now switch on D1 which will set B as 1 hence, the input will be A=0 and B=1
again observe the output and record it in observation table.
8. Similarly make 10 and 11 configurations for input and observe the outputs.
Record all the observations in given observation table and compare with the Truth
Table of Half adder.

NV6554
Observation Table:
X Y Ch Sh
0 0
0 1
1 0
1 1

NV6554
Experiment 2
Objective:
To study and verify Truth Table of Binary Full Adder (using two half adders).
Truth Table & Logic Diagram:
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Figure 3

NV6554
Procedure:
3. Connect bits D0 and D1 of input section to the inputs of Half Adder1 as A and B
and connect D2 to the input A of Half Adder 2 this will work as third input bit or
Cin.
4. Connect Sum of Half Adder 1 at the input B of Half Adder 2 and carry of Half
Adder1 to the A input of OR gate.
5. Now connect sum of Half Adder2 at the output section LED D6 and carry of Half
Adder2 at the input B of OR gate.
6. Now connect output of OR gate which will be the carry of Full Adder circuit or
Cout, to the output LED D7.
8. Initially since all the three inputs D0 and D1 of input section are at Off position
i.e. input is A=0, B=0 and C=0. In this case observe the output (Sum and Carry)
and record in observation table.
9. Now set A=0, B=0 and C=1 and observe the output. Similarly record outputs for
all the possible combinations of ABC. Compare this with the given observation
table for Full Adder.
Observation Table:
A B Cin S Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

NV6554
Experiment 3
Objective:
Study and verify Truth Table of Binary Half Subtractor
Truth Table and Logic diagram:
X Y Bh Dh
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Binary Half Subtractor

Figure 4

NV6554
Circuit Diagram:
Figure 5
Procedure:
3. Connect bits D0 and D1 of input section to the inputs of Half Subtractor as A and B.
4. Connect Difference of Half Subtractor at D6 of output section and Borrow at the
D7 of output section.
6. Initially since both of the inputs D0 and D1 of input section are at Off position i.e.
input is A=0 and B=0. In this case observe the output (Difference and Borrow)
and record in observation table.
7. Now switch on D1 which will set B as 1 hence the input will be A=0 and B=1
again observe the output and record it in observation table.
8. Similarly make 10 and 11 configurations for input and observe the outputs.
Record all the observations in given observation table and compare with the truth
table of Half Subtractor.

NV6554
Observation Table:
A B Difference Borrow
0 0
0 1
1 0
1 1

.
Multiplexer and Demultiplexer Trainer
NV6556
Learning Material
Ver 1.1
NV6556
Multiplexer and Demultiplexer Trainer

NV6556
Table of Contents
1. Introduction 3
2. Features 4
3. Technical Specifications 5
4. Theory 6
5. Experiments
• Experiment 1 9
To study and verify the truth table of 4-to-1 Line Multiplexer
• Experiment 2 10
To study and verify the truth table of 1-to-4 Line Demultiplexer
6. Datasheet 11
7. Warranty 14

NV6556
Experiment 1
Objective:
To study and verify the truth table of 4-to-1 Multiplexer
Procedure:
1. First make sure that toggle switches of input section are Off (i.e. in downward direction).
2. Connect bits I0, I1, I2, I3, I4 and I5 of Input Section to the inputs D0, D1, D2, D3 and selection
lines S1 and S2 of 4-to-1 Line Multiplexer respectively.
3. Connect outputs of the Multiplexer Y to O1 or any other terminal of the Output Section.
4. Connect +5V adaptor on the DC socket provided on the trainer.
6. Now using toggle switches of Input Section provide input to the multiplexer as per below
truth table. (In the observation table)
7. Observe the outputs, record it in observation table and verify & compare the outputs of this
truth table with table 1 (at page no. 6)
Note:
• When the toggle switch is in the upward direction, LED will glow which represents the
Logic 1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which represents
the Logic 0 (i.e. 0V).
Observation Table:
Inputs Output
D0 D1 D2 D3 S1 S0 Y
1 0 1 0 0 0
0 1
1 0
1 1
Here if you give Inputs D0D1D2D3 = 1010 to multiplexer & make the different combinations of
selection lines S1 & S0 then you will get outputs according to Table 1 at Output Section.

NV6556
Experiment 2
Objective:
To study and verify the Truth Table of 1-to-4 Line Demultiplexer
Procedure:
1. First make sure that toggle switches of input section are Off (i.e. in downward direction).
2. Connect bits I0, I1 and I2 of Input Section to the inputs E, S1 and S0 of 1-to-4 Line
Demultiplexer respectively.
3. Connect outputs of the Demultiplexer D0, D1, D2 and D3 to O1, O2, O3 and O4 of the Output
Section.
6. Now using toggle switches of Input Section provide input to the demultiplexer as per below
truth table. (In the observation table)
7. Observe the outputs, record it in observation table and verify & compare the outputs of this
truth table with table 2 (at page no. 8)
Note:
• When the toggle switch is in the upward direction, LED will glow which represents the
Logic 1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which represents
the Logic 0 (i.e. 0V).
Observation Table:
Inputs Outputs
E S1 S2 D0 D1 D3 D4
1 X X
0 0 0
0 0 1
0 1 0
0 1 1

Encoder and Decoder Trainer
NV6557
Learning Material
Ver 1.1
NV6557
Encoder and Decoder Trainer

NV6557
Table of contents
1. Introduction 3
2. Features 4
3. Technical Specifications 5
4. Theory 6
5. Experiments
• Experiment 1 9
To study and verify the Truth Table of 8-to-3 Line Encoder
• Experiment 2 10
To study and verify the Truth Table of 3-to-8 Line Decoder
6. Data Sheet 11
7. Warranty 12

NV6557
Experiment 1
Objective:
To study and verify the Truth Table of 8-to-3 Line Encoder
Procedure:
1. First make sure that toggle switches of input section are ‘Off’ (i.e. in downward
direction).
2. Connect 0, 1, 2, 3, 4, 5, 6 & 7 of Input Section to the inputs D0, D1, D2, D3, D4, D5,
D6 & D7 of 8-to-3 Line Encoder respectively.
3. Connect outputs of the Encoder X, Y & Z to O0, O1 & O2 of the Output Section
respectively.
5. Switch ‘On’ the power supply.
6. Now using toggle switches of Input Section provide input to the Encoder as per its
truth table (Table No.1).
Note:
• When the toggle switch is in the upward direction, LED will glow which
represents the Logic 1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which
represents the Logic 0 (i.e. 0V).
7. Observe the output, record it in observation table and verify the truth table.
Observation Table:

NV6557
Experiment 2
Objective:
To study and verify the Truth Table of 3-to-8 Line Decoder
Procedure:
1. First make sure that toggle switches of input section are ‘Off’ (i.e. in downward
direction).
2. Connect 0, 1 & 2 of Input Section to the inputs X, Y & Z of 3-to-8 Line Decoder
respectively.
3. Connect outputs of the Decoder D0, D1, D2, D3, D4, D5, D6 & D7 to O0, O1, O2, O3
O4, O5, O6 and O7 of the Output Section respectively.
5. Switch ‘On’ the power supply.
6. Now using toggle switches of Input Section provide input to the Decoder as per
the truth table. (Table No.2).
Note:
• When the toggle switch is in the upward direction, LED will glow which represents
the Logic 1 (i.e. +5V).
• When the toggle switch is in the downward direction, LED will not glow which
represents the Logic 0 (i.e. 0V).
7. Observe the output, record it in observation table and verify the truth table.
Observation Table:

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DEPARTMENT OF COMPUTER ENGINEERING

Gujarat Power Engineering and Research Institute, Mehsana

DEPARTMENT OF COMPUTER ENGINEERING

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Faculty In-charge Head of Department

3 To verify De Morgan’s Theorem.

To study and verify Truth Table of Binary

141-B, Electronic Complex,

Logic Gates Trainer

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A(D0) B(D1) Y(D0)

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Universal Gates Trainer

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141-B, Electronic Complex,

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A(D0) B(D1) Y(D0)

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141-B, Electronic Complex,

Adders and Subtractors Trainer

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Binary Half Subtractor

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