Datasheet DRAM Asincrona

16Mb: 1 MEG x16
EDO DRAM
EDO DRAM
MT4C1M16E5 1 Meg x 16, 5V

MT4LC1M16E5 1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/sdramds.html
FEATURES
JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
High-performance CMOS silicon-gate process
Single power supply (+3.3V 0.3V or 5V 10%)
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
BYTE WRITE access cycles
1,024-cycle refresh (10 row, 10 column addresses)
Extended Data-Out (EDO) PAGE MODE access
5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
Voltages 1
3.3V
5V
LC
C
Refresh Addressing
1,024 (1K) rows
E5
Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
DJ
TG
Timing
50ns access
60ns access
-5
-6
Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
None
S2
Operating Temperature Range

Commercial (0oC to +70oC)
Extended (-20oC to +80oC)
None
ET
PIN ASSIGNMENT (Top View)

44/50-Pin TSOP
50
49
48
47
46
45
44
43
42
41
40
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
1 MEG x 16 EDO DRAM PART NUMBERS

PART NUMBER
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-x S
MT4LC1M16E5TG-x
MT4LC1M16E5TG-x S
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
Vcc REFRESH PACKAGE REFRESH

3.3V
1K
400-SOJ Standard
3.3V
1K
400-SOJ
Self
3.3V
1K
400-TSOP Standard
3.3V
1K
400-TSOP
Self
5V
1K
400-SOJ Standard
5V
1K
400-TSOP Standard
NOTE: -x indicates speed grade marking under timing

options.
Part Number Example:
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
NOTE: 1. The third field distinguishes the low voltage offering: LC designates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
KEY TIMING PARAMETERS

tRC
tRAC
tPC
tAA
tCAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
15ns
17ns
8ns
10ns
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
1
2
3
4
5
6
7
8
9
10
11
NOTE: The "#" symbol indicates signal is active LOW.
MT4LC1M16E5TG-6
SPEED
-5
-6
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
42-Pin SOJ
2001, Micron Technology, Inc
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16Mb: 1 MEG x16

EDO DRAM
GENERAL DESCRIPTION (continued)
of the two signals results in a BYTE WRITE cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are
entered 10 bits (A0-A9) at a time. RAS# is used to latch
the first 10 bits and CAS#, the latter 10 bits. The CAS#
function also determines whether the cycle will be a
refresh cycle (RAS# ONLY) or an active cycle (READ,
WRITE or READ-WRITE) once RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions like the single CAS# input
on other DRAMs. The key difference is each CAS# input
(CASL# and CASH#) controls its corresponding eight
DQ inputs during WRITE accesses. CASL# controls
DQ0-DQ7, and CASH# controls DQ8-DQ15. The two
CAS# controls give the 1 Meg x 16 both BYTE READ and
BYTE WRITE cycle capabilities.
RAS#
CASL#/CASH#
ADDR
A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS# (CASL# or CASH#), whichever occurs last. An
EARLY WRITE occurs when WE is taken LOW prior to
either CAS# falling. A LATE WRITE or READ-MODIFYWRITE occurs when WE falls after CAS# (CASL# or
CASH#) was taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READMODIFY-WRITE cycles, OE# must be taken HIGH to
disable the data outputs prior to applying input data.
If a LATE WRITE or READ-MODIFY-WRITE is attempted
while keeping OE# LOW, no WRITE will occur, and the
data outputs will drive read data from the accessed
location.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
The 1 Meg x 16 DRAM must be refreshed periodically in order to retain stored data.
V IH
V IL
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
VALID DATA (A)
VALID DATA (A)
OE#
VALID DATA (D)

tOD
tOD
tOES
COLUMN (D)
VALID DATA (C)
VALID DATA (B)
tOD
V IH
V IL
COLUMN (C)
tOEHC
tOE
tOEP
The DQs go back to

Low-Z if tOES is met.
The DQs remain High-Z

until the next CAS# cycle
if tOEHC is met.
The DQs remain High-Z

until the next CAS# cycle
if tOEP is met.
DONT CARE
UNDEFINED
Figure 1
OE# Control of DQs
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16Mb: 1 MEG x16

EDO DRAM
PAGE ACCESS
Page operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The page cycle is always initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
RAS# HIGH terminates the page mode of operation,
i.e., closes the page.
while RAS# remains LOW, data will transition to and

remain High-Z (refer to Figure 1). WE# can also perform
the function of disabling the output drivers under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire
ORd, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after
tOFF, which is referenced from the rising edge of RAS#
or CAS#, whichever occurs last.
EDO PAGE MODE

BYTE ACCESS CYCLE
The 1 Meg x 16 provides EDO PAGE MODE, which is

an accelerated FAST-PAGE-MODE cycle. The primary
advantage of EDO is the availability of data-out even
after CAS# returns HIGH. EDO provides for CAS#
precharge time (tCP) to occur without the output data
going invalid. This elimination of CAS# output control
provides for pipelined READs.
FAST-PAGE-MODE DRAMs have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE# is
pulsed while RAS# and CAS# are LOW, data will toggle
from valid data to High-Z and back to the same valid
data. If OE# is toggled or pulsed after CAS# goes HIGH
RAS#
V IH
V IL
CASL#/CASH#
V IH
V IL
ADDR
V IH
V IL
DQ V IOH
V IOL
ROW
The BYTE WRITEs and BYTE READs are determined

by the use of CASL# and CASH#. Enabling CASL# selects a lower BYTE access (DQ0-DQ7). Enabling CASH#
selects an upper BYTE access (DQ8-DQ15). Enabling
both CASL# and CASH# selects a WORD WRITE cycle.
The 1 Meg x 16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the exception of the CAS# inputs. Figure 3 illustrates the BYTE
WRITE and WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
COLUMN (A)
OPEN
COLUMN (B)
COLUMN (C)
VALID DATA (A)
VALID DATA (B)
V IH
V IL
OE#
V IH
V IL
INPUT DATA (C)

tWHZ
tWHZ
WE#
COLUMN (D)
tWPZ
The DQs go to High-Z if WE# falls, and if tWPZ is met,

will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DONT CARE
UNDEFINED
Figure 2
WE# Control of DQs
1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
16Mb: 1 MEG x16

EDO DRAM
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
distributed CBR REFRESH. This refresh rate can be

applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving
RAS# HIGH for a minimum time of tRPS. This delay
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence,
all 1,024 rows must be refreshed within the average
internal refresh rate, prior to the resumption of normal
operation.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within tREF (MAX), regardless of sequence.
The CBR, EXTENDED and SELF REFRESH cycles will
invoke the internal refresh counter for automatic RAS#
addressing.
An optional self refresh mode is available on the S
version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW
for the specified tRASS. The S option allows the user
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125s per row, when using a
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
WORD WRITE
LOWER BYTE WRITE
RAS#
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
UPPER BYTE
(DQ8-DQ15)
OF WORD
STORED
DATA
1
1
0
INPUT
DATA
0
0
1
1
1
STORED
DATA
0
0
1
STORED
DATA
0
0
1
INPUT
DATA
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
X
X
X
X
1
0
1
0
1
0
1
0
X
X
1
0
1
0
1
0
X
X
1
0
X
X
1
1
X
X
1
1
1
1
1
1
1
1
1
1
X
X
X
X
1
1
1
1
0
0
0
INPUT
DATA
ADDRESS 0
INPUT
DATA
STORED
DATA
1
1
0
ADDRESS 1
X = NOT EFFECTIVE (DON'T CARE)
Figure 3
WORD and BYTE WRITE Example
1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
16Mb: 1 MEG x16

EDO DRAM
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
DATA-IN BUFFER
CAS#
CASH#
DQ0
16
NO. 2 CLOCK
GENERATOR
10
DQ15
DATA-OUT
BUFFER
COLUMNADDRESS
BUFFER
10
COLUMN
DECODER
OE#
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1,024
REFRESH
CONTROLLER
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
1,024 x 16
10
RAS#
ROWADDRESS
BUFFERS (10)
10
ROW
DECODER
10
NO. 1 CLOCK
GENERATOR
1,024
1,024 x 1,024 x 16
MEMORY
ARRAY
VDD
VSS
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
16Mb: 1 MEG x16

EDO DRAM
*Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Pin Relative to VSS
3.3V ......................................................... -1V to +4.6V
5V ............................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to Vss:
3.3V ......................................................... -1V to +5.5V
5V ............................................................... -1V to +7V
Operating Temperature
TA (commercial) .................................. 0C to +70C
TA (extended) ................................... -20C to +80C
Storage Temperature (plastic) ........... -55C to +150C
Power Dissipation ........................................................ 1W
Short Circuit Output Current ................................ 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1; notes appear on pages 10-11)
PARAMETER/CONDITION
SYMBOL
3.3V
MIN
MAX
5V
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
VCC
3.0
3.6
4.5
5.5
INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC
VIH
2.0
5.5
2.4
VCC + 1
INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC
VIL
-1.0
0.8
-0.5
0.8
II
-2
-2
OUTPUT HIGH VOLTAGE:

IOUT = -2mA(3.3V), -5mA(5V)
VOH
2.4
2.4
OUTPUT LOW VOLTAGE:

IOUT = 2mA(3.3V), 4.2mA(5V)
VOL
0.4
0.4
IOZ
-5
-5
INPUT LEAKAGE CURRENT:

Any input at VIN (0V VIN VIH[MAX]);
All other pins not under test = 0V
OUTPUT LEAKAGE CURRENT:

Any output at VOUT (0V VOUT 5.5V);
DQ is disabled and in High-Z state
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
16Mb: 1 MEG x16

EDO DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 8; notes appear on pages 10-11); (VCC[MIN] VCC VCC[MAX])
PARAMETER/CONDITION
3.3V
5V
STANDBY CURRENT: TTL

(RAS# = CAS# = VIH)
ICC1
ALL
mA
STANDBY CURRENT: CMOS (non-S version only)

(RAS# = CAS# = other inputs = VDD - 0.2V)
ICC2
ALL
500
500
STANDBY CURRENT: CMOS (S version only)

(RAS# = CAS# = other inputs = VDD - 0.2V)
ICC2
ALL
150
150
OPERATING CURRENT: Random READ/WRITE

Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC3
-5
-6
180
170
190
180
mA
OPERATING CURRENT: EDO PAGE MODE

Average power supply current (RAS# = VIL, CAS#,
address cycling: tPC = tPC [MIN])
ICC4
-5
-6
140
130
150
140
mA
REFRESH CURRENT: RAS#-ONLY

(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
ICC5
-5
-6
180
170
190
180
mA
REFRESH CURRENT: CBR

(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC6
-5
-6
180
170
180
170
mA
7, 9
REFRESH CURRENT: Extended (S version only)

Average power supply current: CAS# = 0.2V or CBR cycling;
RAS# = tRAS (MIN); WE# = VDD - 0.2V; A0-A10, OE# and
DIN = VDD - 0.2V or 0.2V (DIN may be left open); tRC = 125s
ICC7
ALL
300
300
7, 9
REFRESH CURRENT: Self (S version only)

Average power supply current: CBR with RAS# tRASS (MIN)
and CAS# held LOW; WE# = VDD - 0.2V; A0-A10,
OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open)
ICC8
ALL
300
300
7, 9
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
SYMBOL SPEED
UNITS NOTES
16Mb: 1 MEG x16

EDO DRAM
CAPACITANCE
(Notes: 1, 2, 3, 5, 8; notes appear on pages 10-11)
PARAMETER
SYMBOL MAX UNITS NOTES
Input Capacitance: Addresses
CI1
pF
Input Capacitance: RAS#, CASL#,CASH#, WE#, OE#
CI2
pF
Input/Output Capacitance: DQ
CIO
pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (VCC[MIN] VCC VCC[MAX])
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to Dont Care during Self Refresh
CAS# hold time (CBR Refresh)
Last CAS# going LOW to first CAS# to return HIGH
CAS# to output in Low-Z
Data output hold after next CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
-5
OE# HIGH hold from CAS# HIGH

OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
SYMBOL
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLCH
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEH
MIN
tOEHC
5
5
4
0
tOEP
tOES
tOFF
-6
MAX
25
12
38
0
0
42
MIN
NOTES
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
5
0
ns
ns
ns
ns
18
15
45
0
0
49
13
8
8
15
8
5
0
3
8
10,000
15
10
10
15
10
5
0
3
10
28
5
38
5
28
8
8
0
0
MAX
30
12
12
12
10,000
35
5
45
5
35
10
10
0
0
15
15
15
25
25
13
14, 25
25
27
7, 26
28
26
15, 30
26
26
26
7, 25
13, 25
26
16, 25
16, 25
17
18
20, 26
16Mb: 1 MEG x16

EDO DRAM
AC ELECTRICAL CHARACTERISTICS (continued)
(Notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (VCC[MIN] VCC VCC[MAX])
AC CHARACTERISTICS
PARAMETER
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
-5
EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE#
WRITE command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
SYMBOL
tORD
MIN
0
tPC
20
47
tPRWC
tRAC
tRAD
tRAH
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
30
5
90
0
13
116
67
13
2
8
38
0
0
5
10
8
8
MAX
25
56
10,000
125,000
60
12
10
60
60
100
104
14
0
0
16
128
tREF
tRP
MIN
0
50
9
9
50
50
100
84
11
0
0
tREF
tRPC
-6
MAX
50
12
10,000
125,000
16
128
40
5
105
0
15
140
79
15
2
10
45
0
0
5
10
10
10
50
15
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31
31
19
21
22, 25
23, 27
25
23
32
13
32
13, 25
16Mb: 1 MEG x16

EDO DRAM
NOTES
1. All voltages referenced to VSS.
2. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0C TA 70C for
commercial) and (-20C TA 80C for extended)
is ensured.
3. An initial pause of 100s is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
4. NC pins are assumed to be left floating and are
not tested for leakage.
5. ICC is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
9. AC characteristics assume tT = 2.5ns.
10.VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between VIH and VIL (or
between VIL and VIH).
11.In addition to meeting the transition rate
specification, all input signals must transit
between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
12.Measured with a load equivalent to two TTL gates
and 100pF; and VOL = 0.8V and VOH = 2V.
13. tWCS, tRWD, tAWD, and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and
tRWD tRWD (MIN), tAWD tAWD (MIN) and
tCWD tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW results in a LATE
WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD
and tAWD are not applicable in a LATE WRITE
cycle.
14.Assumes that tRCD tRCD (MAX).
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
15.If CAS# is LOW at the falling edge of RAS#, Q will

be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for tCP.
16.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
17.If OE# is tied permanently LOW, LATE WRITE, or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, WE# must be pulsed during CAS#
HIGH time in order to place I/O buffers in High-Z.
18.LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after tOEH is met. If CAS# goes HIGH prior to
OE# going back LOW, the DQs will remain open.
19.Assumes that tRCD < tRCD (MAX). If tRCD is
greater than the maximum recommended value
shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively
by tAA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC, and tCAC
must always be met.
22.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively
by tCAC (tRAC [MIN] no longer applied). With or
without the tRCD limit, tAA and tCAC must always
be met.
23.Either tRCH or tRRH must be satisfied for a READ
cycle.
24.The first CAS#x edge to transition LOW.
25.Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and
DQ8-DQ15 by CASH#.
10
16Mb: 1 MEG x16

EDO DRAM
NOTES (continued)
26.Each CAS#x must meet minimum pulse width.
27.The last CAS#x edge to transition HIGH.
28.Last falling CAS#x edge to first rising CAS#x edge.
29.Last rising CAS#x edge to first falling CAS#x edge.
30.Last rising CAS#x edge to next cycles last rising
CAS#x edge.
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
31.Last CAS#x to go LOW.

32.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
11
16Mb: 1 MEG x16

EDO DRAM
READ CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tRCD
tCRP
CASL#/CASH#
tRRH
tCLCH
tCAS
V IH
V IL
tAR
tRAD
tRAH
tASR
tASC
tCAH
tACH
ADDR
V IH
V IL
ROW
ROW
COLUMN
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OE#
OPEN
VALID DATA
tOE
tOD
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
MIN
-5
-6
MAX
25
MIN
MAX
30
SYMBOL
UNITS
ns
MIN
tOE
ns
ns
ns
tOFF
tASC
15
45
0
tRAD
tASR
ns
ns
tRAH
9
50
ns
ns
ns
tRC
ns
ns
tRCS
ns
ns
tRRH
tCAC
tCAH
tCAS
tCLCH
tCLZ
tCRP
tCSH
tOD
13
8
8
5
10,000
0
5
38
0
15
10
10
5
10,000
0
5
12
45
0
15
MIN
12
12
38
0
tAR
-6
MAX
tRAC
tRAS
tRCD
tRCH
tRP
tRSH
12
50
MAX
ns
15
60
ns
ns
ns
12
10,000
10
60
UNITS
15
10,000
ns
ns
84
11
0
104
14
0
ns
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
12
16Mb: 1 MEG x16

EDO DRAM
EARLY WRITE CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCRP
CASL#/CASH#
tCAS
tAR
tASC
tCAH
tCLCH
V IH
V IL
tRAD
tASR
ADDR
tRCD
V IH
V IL
tACH
tRAH
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCH
tWCS
tWP
WE#
V IH
V IL
tDS
V
DQ V IOH
IOL
OE#
tDH
VALID DATA
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
MIN
-6
MAX
MIN
-5
MAX
UNITS
SYMBOL
12
38
0
15
45
0
ns
ns
ns
tRAD
0
8
0
10
ns
ns
tRC
ns
ns
ns
tRP
tCSH
38
45
ns
tWCH
tCWL
8
8
0
10
10
0
ns
ns
ns
tWCR
tDS
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
10,000
tRCD
tCRP
tDH
10
5
5
tRAS
8
5
5
tCLCH
10,000
tRAH
tRSH
tRWL
tWCS
tWP
13
MIN
-6
MAX
9
9
50
84
11
MIN
MAX
12
10
10,000
60
104
14
UNITS
ns
ns
10,000
ns
ns
ns
30
13
40
15
ns
ns
13
8
38
15
10
45
ns
ns
ns
0
5
0
5
ns
ns
16Mb: 1 MEG x16

EDO DRAM
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
RAS#
V IH
V IL
tCRP
CASL#/CASH#
tCSH
tRSH
tCAS, tCLCH
tRCD
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
tRP
V IH
V IL
tASC
tCAH
ROW
COLUMN
tRCS
WE#
tACH
ROW
tRWD
tCWD
tCWL
tRWL
tAWD
tWP
V IH
V IL
tAA
tRAC
tCAC
tDS
tCLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
tOE
OE#
tDH
VALID D IN
tOD
OPEN
tOEH
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
tAR
tASC
tAWD
tASR
MIN
tCWL
tDH
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
MAX
MIN
0
MAX
UNITS
ns
12
12
15
15
ns
ns
60
ns
ns
ns
0
49
0
ns
ns
ns
tOEH
tRAD
ns
ns
tRAH
9
50
ns
ns
ns
tRCD
13
15
10
10,000
10
5
0
10,000
tOE
tRAC
tRAS
tRCS
tRP
5
38
5
45
ns
ns
tRSH
28
8
35
10
ns
ns
tRWD
10
ns
tWP
tRWC
tRWL
14
-6
MIN
0
0
42
0
8
5
0
tCWD
SYMBOL
tDS
tOD
tCAS
tCSH
UNITS
ns
ns
ns
tCRP
-5
MAX
30
15
45
tCAH
tCLZ
MIN
12
38
tCAC
tCLCH
-6
MAX
25
10
50
12
10,000
10
60
10,000
ns
ns
11
0
30
14
0
40
ns
ns
ns
13
116
15
140
ns
ns
67
13
79
15
ns
ns
ns
16Mb: 1 MEG x16

EDO DRAM
EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tRP
tCAS, tCLCH
tRCD
tPC
tCP
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
V IH
V IL
tAR
tACH
tRAD
tRAH
tASR
ADDR
V IH
V IL
tACH
tASC
ROW
tCAH
tASC
COLUMN
tACH
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCS
WE#
tRCH
V IH
V IL
tAA
tRAC
tAA
tCPA
tCAC
tCAC
DQ
V OH
V OL
VALID
DATA
OPEN
tOFF
tOEHC
VALID
DATA
tOE
OE#
tCAC
tCLZ
tCOH
tCLZ
VALID
DATA
OPEN
tOE
tOD
tOES
V IH
V IL
tRRH
tAA
tCPA
tOD
tOES
tOEP
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
45
0
ns
ns
tOEP
tASC
38
0
tASR
ns
ns
ns
tOFF
ns
ns
tRAD
ns
ns
ns
tRASP
ns
ns
tRCS
ns
ns
tRRH
tCAC
tCAS
8
5
tCLZ
tCOH
tCP
tCSH
38
0
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
15
10
10,000
10
5
10,000
0
3
10
28
tCRP
MAX
30
0
3
8
tCPA
tOD
MIN
13
tCAH
tCLCH
MAX
25
-5
UNITS
ns
ns
tAR
MIN
35
5
12
45
0
15
SYMBOL
tOE
tOEHC
tOES
tPC
MIN
5
10
UNITS
ns
ns
5
4
5
5
ns
ns
0
20
tRAC
tRAH
tRCD
tRCH
tRP
tRSH
15
-6
MAX
12
12
MIN
0
25
50
9
9
50
11
0
MAX
15
15
60
12
10
125,000
60
14
0
ns
ns
ns
ns
1ns
125,000
ns
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
16Mb: 1 MEG x16

EDO DRAM
EDO-PAGE-MODE EARLY WRITE CYCLE
tRP
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tRCD
tCAS, tCLCH
tPC
tCP
tCAS, tCLCH
tAR
tASR
V IH
V IL
tACH
tACH
tASC
tRAH
ROW
tACH
tASC
tCAH
COLUMN
tCAH
tASC
COLUMN
tCWL
tWCH
tWCS
tCAH
COLUMN
tCWL
tWCH
tWCS
tWP
WE#
tWCS
tWP
ROW
tCWL
tWCH
tWP
V IH
V IL
tWCR
tDS
V
DQ V IOH
IOL
OE#
tCP
V IH
V IL
tRAD
ADDR
tRSH
tCAS, tCLCH
tCP
tRWL
tDH
tDS
VALID DATA
tDH
tDS
VALID DATA
tDH
VALID DATA
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCLCH
tCP
tCRP
tCSH
tCWL
tDH
tDS
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
MIN
12
38
0
0
8
8
-6
MAX
10,000
MIN
15
45
0
0
10
10
-5
MAX
10,000
UNITS
ns
ns
SYMBOL
tPC
-6
MAX
MIN
125,000
25
12
10
60
MAX
UNITS
125,000
ns
ns
ns
ns
tRASP
20
9
9
50
tRCD
11
14
ns
tRP
30
13
13
40
15
15
ns
ns
ns
8
38
10
45
ns
ns
0
5
0
5
ns
ns
tRAD
ns
ns
ns
ns
tRAH
5
8
5
10
ns
ns
tRSH
5
38
8
5
45
10
ns
ns
ns
tWCH
8
0
10
0
ns
ns
tWP
tRWL
tWCR
tWCS
16
MIN
16Mb: 1 MEG x16

EDO DRAM
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CASL#/CASH#
tPRWC NOTE 1
tPC
tRCD
tCP
tCAS, tCLCH
tRSH
tCP
tCAS, tCLCH
tCP
tCAS, tCLCH
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
tRP
V IH
V IL
tASC
tCAH
ROW
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
WE#
tCWL
tWP
tAWD
tCWD
tAA
tAA
tDH
tCAC
tCLZ
V IOH
V IOL
tAA
tDH
tCPA
tDS
tCAC
tCLZ
tOE
tDS
tCAC
tCLZ
VALID VALID
D OUT D IN
VALID VALID
D OUT D IN
VALID VALID
D OUT D IN
OPEN
tDH
tCPA
tDS
tOD
OE#
tWP
tAWD
tCWD
V IH
V IL
tRAC
DQ
tRWL
tCWL
tCWL
tWP
tAWD
tCWD
tOD
tOD
tOE
tOE
OPEN
tOEH
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
tAWD
MIN
tCAS
tCLCH
tCLZ
tCP
MIN
MAX
30
SYMBOL
UNITS
ns
tDS
ns
ns
tOD
0
42
0
49
tOEH
15
ns
ns
ns
tRAC
10,000
ns
ns
tRAD
ns
ns
ns
tRAH
9
50
tRCS
13
8
8
10,000
5
0
8
10
10
5
0
10
35
tPC
8
20
tPRWC
47
tRASP
tRCD
tCRP
tCSH
38
28
45
35
ns
ns
tRSH
8
8
10
10
ns
ns
tRWL
tDH
28
tOE
ns
ns
tCWL
0
0
45
0
tCPA
tCWD
MIN
38
0
tCAC
tCAH
-5
-6
MAX
25
tRP
tRWD
tWP
-6
MAX
12
12
MIN
0
0
MAX
UNITS
15
15
ns
ns
ns
10
25
ns
ns
56
50
60
12
125,000
10
60
125,000
ns
ns
ns
ns
ns
11
0
30
14
0
40
ns
ns
ns
13
67
15
79
ns
ns
13
5
15
5
ns
ns
NOTE: 1. tPC is for LATE WRITE cycles only.

1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
17
16Mb: 1 MEG x16

EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
tPC
tCRP
CASL#/CASH#
t RCD
t CAS, tCLCH
tRSH
tPC
t CP
t CP
t CAS, tCLCH
t CP
t CAS, tCLCH
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
t ACH
tRAH
tASC
ROW
tCAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
ROW
tWCS
tWCH
tAA
tAA
tCPA
tRAC
tCAC
tCAC
tCOH
DQ V IOH
V IOL
t CAH
COLUMN (N)
tRCH
tRCS
WE#
tASC
OPEN
VALID DOUT
t DS
t DH
t WHZ
VALID
DOUT
VALID DIN
tOE
OE#
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
-6
MAX
MIN
UNITS
SYMBOL
30
tDS
MIN
tACH
12
15
ns
ns
tAR
38
0
0
45
0
0
ns
ns
ns
tPC
tRAD
ns
ns
tRAH
9
50
ns
ns
ns
tRCD
ns
ns
tRP
ns
ns
ns
tWCH
tASC
tASR
25
-5
MAX
tCAC
13
tCAH
tCAS
tCOH
8
5
3
tCP
tCLCH
tCPA
tCRP
tCSH
tDH
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
15
10
10,000
10
5
3
10
28
5
38
8
10,000
35
5
45
10
tOE
tRCH
tRCS
tRSH
tWCS
tWHZ
18
MIN
MAX
UNITS
15
ns
ns
0
12
20
tRAC
tRASP
-6
MAX
25
50
60
12
125,000
10
60
125,000
ns
ns
ns
ns
ns
11
0
0
14
0
0
ns
ns
ns
30
13
40
15
ns
ns
8
0
0
10
0
0
ns
ns
ns
12
15
16Mb: 1 MEG x16

EDO DRAM
READ CYCLE
(with WE#-controlled disable)
RAS#
V IH
V IL
tCSH
tRCD
tCRP
CASL#/CASH#
tCAS, tCLCH
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCS
WE#
tRCH
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tCLZ
V
DQ V OH
OL
tWHZ
OPEN
OPEN
VALID DATA
tOE
OE#
tCLZ
tOD
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
38
0
0
tCAC
tCAS
8
5
0
tCLZ
tCP
tCRP
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
MIN
8
5
-5
MAX
30
45
0
0
13
tCAH
tCLCH
-6
MAX
25
15
10
10,000
10
5
0
10
5
10,000
UNITS
ns
SYMBOL
tCSH
ns
ns
ns
tOD
ns
ns
tRAD
ns
ns
ns
tRCD
ns
ns
tWHZ
MAX
MIN
45
MAX
UNITS
ns
12
12
50
15
15
60
ns
ns
ns
tOE
tRAC
tRAH
tRCH
tRCS
tWPZ
19
-6
MIN
38
9
9
12
10
ns
ns
11
0
0
14
0
0
ns
ns
ns
0
10
12
0
10
15
ns
ns
16Mb: 1 MEG x16

EDO DRAM
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DONT CARE)
tRC
tRAS
RAS#
tRP
V IH
V IL
tRPC
tCRP
CASL#/CASH#
V IH
V IL
tASR
ADDR
V IH
V IL
tRAH
ROW
ROW
V
Q V OH
OL
OPEN
CBR REFRESH CYCLE

(Addresses and OE# = DONT CARE)
tRP
tRAS
tRP
NOTE 1
tRAS
V IH
V IL
RAS#
tRPC
tCP
CASL#/CASH#
V IH
V IL
DQ
V OH
V OL
tCSR
tCSR
tCHR
OPEN
tWRP
WE#
tRPC
tCHR
tWRH
tWRP
tWRH
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tASR
tCHR
tCP
tCRP
tCSR
tRAH
MIN
-6
MAX
MIN
-5
MAX
UNITS
SYMBOL
tRAS
tRC
0
8
0
10
ns
ns
8
5
10
5
ns
ns
tRP
5
9
5
10
ns
ns
tWRH
tRPC
tWRP
MIN
50
84
-6
MAX
10,000
MIN
60
104
MAX
10,000
UNITS
ns
ns
30
5
40
5
ns
ns
8
8
10
10
ns
ns
NOTE: 1. End of first CBR REFRESH cycle.

1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
20
16Mb: 1 MEG x16

EDO DRAM
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
tRC
tRAS
RAS#
tRAS
V IH
V IL
tCRP
CASL#/CASH#
tRP
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tCAC
tCLZ
DQx
V IOH
V IOL
tOFF
OPEN
VALID DATA
OPEN
tOE
OE#
V IH
V IL
tOD
tORD
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
-6
MIN
-5
38
45
UNITS
ns
ns
0
0
0
0
ns
ns
tORD
tRAD
tCAC
MAX
25
MIN
tOE
tOFF
0
0
tRAC
0
5
ns
ns
tRCD
tCRP
0
5
tRP
50
11
30
tOD
ns
tRSH
13
tCLZ
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
12
15
tRAS
21
MIN
12
0
0
50
10
10
tRAH
-6
MAX
12
8
8
tCHR
15
SYMBOL
ns
ns
ns
tCAH
13
MAX
30
9
9
MAX
ns
15
ns
ns
ns
60
12
10
10,000
60
14
40
15
UNITS
15
ns
ns
10,000
ns
ns
ns
ns
16Mb: 1 MEG x16

EDO DRAM
SELF REFRESH CYCLE
(Addresses and OE# = DONT CARE)
RAS#
V IH
V IL
V IH
V IL
DQ
V OH
V OL
WE#
((
))
tRPC
tCSR
tRPS
NOTE 2
tRPC
((
))
tCP
CASL#/
CASH#
NOTE 1
tRASS
tRP
((
))
tCP
tCHD
((
))
((
))
((
))
tWRP
OPEN
tWRP
tWRH
tWRH
((
))
((
))
V IH
V IL
DONT CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tCHD
tCLCH
tCP
tCSR
tRASS
MIN
15
5
8
5
100
-6
MAX
MIN
15
5
10
5
100
-5
MAX
UNITS
ns
ns
ns
ns
s
SYMBOL
tRP
tRPC
tRPS
tWRH
tWRP
MIN
30
5
90
8
8
-6
MAX
MIN
40
5
105
10
10
MAX
UNITS
ns
ns
ns
ns
ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
22
16Mb: 1 MEG x16

EDO DRAM
44/50-PIN PLASTIC TSOP (400 mil)
.828 (21.04)
.822 (20.88)
SEE DETAIL A
.029 (0.75) TYP
50
.467 (11.86)
.459 (11.66)
.402 (10.21)
.398 (10.11)
25
.007 (0.18)
.005 (0.13)
PIN #1 INDEX
.031 (0.80)
TYP
.018 (0.45)
.012 (0.30)
.010 (0.25)
.004 (0.10)
.047 (1.20)
MAX
SEATING PLANE
.008 (0.20)
.002 (0.05)
DETAIL A
.024 (0.60)
.016 (0.40)
.032 (0.80)
TYP
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
1 Meg x 16 EDO DRAM

D52_B.p65 Rev. B; Pub. 3/01
23
16Mb: 1 MEG x16

EDO DRAM
42-PIN PLASTIC SOJ (400 mil)
1.079 (27.41)
1.073 (27.25)
.405 (10.29)
.399 (10.13)
.445 (11.30)
.435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP

1.000 (25.40)
.148 (3.76)
.138 (3.51)
.032 (0.81)
.026 (0.66)
.095 (2.40)
.080 (2.02)
SEATING PLANE
.037 (0.94) MAX
DAMBAR PROTRUSION
.020 (0.51)
.015 (0.38)
.380 (9.65)
.360 (9.14)
.030 (0.76)
MIN
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and the M logos are trademarks of Micron Technology, Inc.
1 Meg x 16 EDO DRAM
D52_B.p65 Rev. B; Pub. 3/01
24

Datasheet DRAM Asincrona

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Datasheet DRAM Asincrona

Uploaded by

Copyright:

Available Formats

16Mb: 1 MEG x16

MT4C1M16E5 1 Meg x 16, 5V

Operating Temperature Range

PIN ASSIGNMENT (Top View)

1 MEG x 16 EDO DRAM PART NUMBERS

Vcc REFRESH PACKAGE REFRESH

NOTE: -x indicates speed grade marking under timing

Part Number Example:

KEY TIMING PARAMETERS

1 Meg x 16 EDO DRAM

NOTE: The "#" symbol indicates signal is active LOW.

2001, Micron Technology, Inc

16Mb: 1 MEG x16

A logic HIGH on WE# dictates read mode, while a

VALID DATA (A)

VALID DATA (A)

VALID DATA (D)

VALID DATA (C)

VALID DATA (B)

The DQs go back to

The DQs remain High-Z

The DQs remain High-Z

1 Meg x 16 EDO DRAM

16Mb: 1 MEG x16

while RAS# remains LOW, data will transition to and

EDO PAGE MODE

The 1 Meg x 16 provides EDO PAGE MODE, which is

The BYTE WRITEs and BYTE READs are determined

VALID DATA (A)

VALID DATA (B)

INPUT DATA (C)

The DQs go to High-Z if WE# falls, and if tWPZ is met,

WE# may be used to disable the DQs to prepare

16Mb: 1 MEG x16

distributed CBR REFRESH. This refresh rate can be

LOWER BYTE WRITE

X = NOT EFFECTIVE (DON'T CARE)

16Mb: 1 MEG x16

1 Meg x 16 EDO DRAM

16Mb: 1 MEG x16

ABSOLUTE MAXIMUM RATINGS*

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

INPUT HIGH VOLTAGE:

INPUT LOW VOLTAGE:

OUTPUT HIGH VOLTAGE:

OUTPUT LOW VOLTAGE:

INPUT LEAKAGE CURRENT:

OUTPUT LEAKAGE CURRENT:

1 Meg x 16 EDO DRAM

16Mb: 1 MEG x16

STANDBY CURRENT: TTL

STANDBY CURRENT: CMOS (non-S version only)

STANDBY CURRENT: CMOS (S version only)

OPERATING CURRENT: Random READ/WRITE

OPERATING CURRENT: EDO PAGE MODE

REFRESH CURRENT: RAS#-ONLY

REFRESH CURRENT: CBR

REFRESH CURRENT: Extended (S version only)

REFRESH CURRENT: Self (S version only)

1 Meg x 16 EDO DRAM

16Mb: 1 MEG x16

SYMBOL MAX UNITS NOTES

Input Capacitance: Addresses

Input Capacitance: RAS#, CASL#,CASH#, WE#, OE#