1) Design and Verification of High speed Bulk transaction in USB

using Verilog
USB Speeds
High Speed - 480Mbits/s
Full Speed - 12Mbits/s
Low Speed - 1.5Mbits/s
USB supports Control, Interrupt, Bulk and synchronous transfers. While we will look at the other
transfer modes later, Isochronous allows a device to
reserve a defined about of bandwidth with guaranteed latency.

2)Implementing interchip communication through SPI using

Verilog
The Serial Peripheral Interface is a serial, synchronous communication protocol that
requires a
minimum of 3 wires. Enhancements to the original interface include a wider
supported operating frequency range, 4 entries deep read and write FIFOs, and
programmable transfer count dependent interrupt generation

3)Design and implementation of I2S protocol using VHDL

Many digital audio systems are being introduced into the consumer
audio market, including compact disc, digital audio tape, digital
sound processors, and digital TV-sound. The digital audio signals in
these systems are being processed by a number of (V)LSI ICs,
such as:
• A/D and D/A converters;
• digital signal processors;
• error correction for compact disc and digital recording;
• digital filters;
• digital input/output interfaces.
Standardized communication structures are vital for both the
equipment and the IC manufacturer, because they increase system
flexibility. To this end, we have developed the inter-IC sound (I2S)
bus – a serial link especially for digital audio.

4) Designing Philips Serial I2C protocol using verilog

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices. It is most suitable for applications requiring occasional
communication over a short distance between many devices. The I2C standard is a true
multi-master bus including collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously.
The interface defines 3 transmission speeds:
- Normal: 100Kbps
- Fast: 400Kbps
- High speed: 3.5Mbps

5)Design and Verification of AMBA master Bus using verilog

The AMBA AHB is for high-performance, high clock frequency system modules.
The AHB acts as the high-performance system backbone bus. AHB supports the
efficient connection of processors, on-chip memories and off-chip external memory
interfaces with low-power peripheral macrocell functions. AHB is also specified to
ensure ease of use in an efficient design flow using synthesis and automated test
techniques.

6) Implementing Pseudo Random number generator for CDMA

using verilog
Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system.
Many PN generators are required within Code Division Multiple Access (CDMA) base
stations.
PN generators are used to implement synchronization and uniquely code individual user
signals across the transmission interface
Code Division Multiple Access (CDMA) systems are based upon several forms of spread
spectrum techniques, the most popular being Direct Sequence Spread Spectrum (DS-SS).
Within a DS-SS system, the data being transmitted is spread across a wide radio spectrum
using a pseudo random binary sequence unique to each user. Every data bit of a user
signal is
multiplied by many bits of a pseudo random binary sequence. This sequence is created by
a
PN generator and often referred to as a PN-Code.

7) Design and verification of CAM in atm protocol using VHDL

Content Addressable Memory (CAM) or associative memory, is a storage device, which
can be
addressed by its own contents. Each bit of CAM storage includes comparison logic. A
data
value input to the CAM is simultaneously compared with all the stored data. The match
result is
the corresponding address. A CAM operates as a data parallel processor. CAMs can be
used
to design Asynchronous Transfer Mode (ATM) switch

8) Design and implementaion of Asynchronous FIFO using

verilog
FIFOs are often used to safely pass data from one clock domain to another asynchronous
clock domain. Using a
FIFO to pass data from one clock domain to another clock domain requires multi-
asynchronous clock design
techniques. There are many ways to design a FIFO wrong. There are many ways to
design a FIFO right but still make
it difficult to properly synthesize and analyze the design.
This paper will detail one method that is used to design, synthesize and analyze a safe
FIFO between different clock
domains using Gray code pointers that are synchronized into a different clock domain
before testing for "FIFO full"
or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog
model (FIFO Style #1) is
included.

9) Implementing Barrel shifters using multipliers using verilog

A barrel shifter is simply a bit-rotating shift register. The bits shifted out the MSB end of
the
register are shifted back into the LSB end of the register. In a barrel shifter, the bits are
shifted
the desired number of bit positions in a single clock cycle. For example, an eight-bit
barrel
shifter could shift the data by three positions in a single clock cycle. If the original data
was
11110000, one clock cycle later the result will be 10000111.
Functionally, since any bit can end up in any bit position, multiplexers are used to place
the bits
correctly for proper storage. Thus, a barrel shifter is implemented by feeding an N-bit
data word
into N, N-bit-wide multiplexers. An eight-bit barrel shifter is built out of eight flip-flops
and eight
8-to-1 multiplexers; a 32-bit barrel shifter requires 32 registers and thirty-two, 32-to-1
multiplexers, and so on

10) Hilbert Transform for brain waves

The Hilbert Transform is an important component in communication systems, e.g.
for single sideband modulation/demodulation, amplitude and phase detection, etc. It
can be formulated as filtering operation which makes it possible to approximate the
Hilbert Transform with a digital _fillter. Due to the non-causal and infinite impulse
response of that filter, it is not that easy to get a good approximation with low
hardware resource usage. Therefore, different filters with different complexities have
been implemented.

11) Implement Cellular automata arithmetic core using verilog

A cellular automata (CA) is a discrete model that consists of a grid (1D, 2D, 3D ) with
objects called cells. Each cell can be in one of a
given finite set of states (on and off, different colours etc). Each cell has a set of cells in
close proximity called neighbours. Given the
current internal state of a cell, the states of the cells in the close proximity and a given set
of update rules the next state of a cell can
be determined

12) Implementing Error Correction control using verilog

The design detects and corrects all single bit errors (in a codeword consisting of either
64-bit data and 8 parity bits, or
32-bit data and 7 parity bits), and it detects double bit errors in the data. This design
utilizes Hamming code, a simple yet powerful method for ECC operations.
As a result, this design offers exceptional performance and resource utilization. Error
detection and correction is found in many high-reliability and performance applications.
For example, in enterprise data storage systems, memory caches are utilized to improve
system reliability. The cache is typically placed inside the controller between the host
interfaces
and the disk array. A robust cache memory design often includes ECC functions to avoid
single point of failure losses of customer data. ECC becomes an important feature for
many
communication applications, such as satellite receivers; it is more performance and cost
efficient to correct an error rather than retransmit the data.

13)Design and verification of quantization in MPEG video using

verilog
Quantization is the process of selectively discarding visual information without a
significant loss in the visual effect. Quantization reduces the number of bits needed to
store an integer value by
reducing the precision of the integer. Each discrete cosine transform (DCT) component is
divided by a separate quantization coefficient, and rounded to the nearest integer. The
larger
the quantization coefficient (i.e., coefficient weighting), the smaller the resulting answer
and associated bits needed to express the DCT component. In the reverse process, the
fractional
bits are "rounded" and are recovered as zeros, constituting a precision loss from the
original number.

14) Implementing Huffman coding in MPEG using verilog

Huffman coding is used to code values statistically according to their probability of

occurence. Short code words are assigned to highly probable values and long code words
to less probable
values. Huffman coding is used in MPEG-2 to further compress the bitstream
15) Design and verification of VLC (Variable Length coding) in
MPEG –encoder using verilog

This application note describes the implementation of Variable Length Coding (VLC) on
Xilinx devices. Zig-zag coding and run length coding are done in an MPEG-2 encoder.
The zig-zag
coding arranges the DCT coefficients in the order of increasing frequency. These
coefficients are then coded as a run-length pair where run is the number of occurrences of
a value and the
length is the amplitude

16) VLSI implementation of a soft bit-flipping decoder for PG-

LDPC codes using verilog -ieee
Low-density parity-check (LDPC) code, a very promising near-optimal error correction
code (ECC), is being widely considered in next generation industry standards. The
VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper
presents the construction of a new class of implementation-oriented LDPC codes, namely
shift-LDPC
codes. With girth optimization, this kind of codes can perform as well as computer
generated random codes. More importantly, the decoder can be efficiently implemented
to obtain very high
decoding speeds. In addition, more than 50% of message memory can be generally saved
over conventional partially parallel decoder architectures. We demonstrate the benefits of
the proposed
techniques with an application-specific integrated circuit (ASIC) design (in 0.18- m
CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15
iterations.

17) VLSI Implementation of a 4×4 MIMO-OFDM transceiver with

an 80-MHz channel bandwidth using verilog-ieee
VLSI Implementation for a 4x4 multiple-input multiple-output orthogonal frequency
division multiplexing (MIMO-OFDM) transceiver is described that targets 1-Gbps
data transmission for next-generation wireless LAN systems. The IEEE802.11 Very High
Throughput (VHT) Study Group concluded that a signal bandwidth of more than 80 MHz
is
needed to achieve 1-Gbps throughput in the MAC layer. The proposed architecture is
suitable for VLSI implementation that meets this specification and enables real-time
processing in a 4x4
MIMO-OFDM configuration. It incorporates a minimum meansquare error (MMSE)
MIMO detector that drastically shortens processing latency. Evaluation of a MIMO-
OFDM transceiver
implemented in CMOS with 128, 256, or 512 OFDM subcarriers showed that the power
dissipation ranged from 451 to 577 mW.