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EC 306 EMBEDDED
SYSTEMS
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Types of AMBA:
The advanced high-performance bus (AHB)
AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2
published by ARM Ltd company.
In addition to previous release, it has the following features:
large bus-widths (64/128/256/512/1024 bit).
A simple transaction on the AHB consists of an address phase and a subsequent data phase
(without wait states: only two bus-cycles). Access to the target device is controlled through
a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time.
AHB-Lite is a subset of AHB formally defined in the AMBA 3 standard. This subset simplifies the
design for a bus with a single master.
The advanced system bus (ASB)
The ASB is a simplified version of the AHB and offers high performance for 16- and 32-bit
systems. Many of the same signal on an AHB are used for the ASB aside from certain control
signals that allow for split transactions.
The operation of the ASB starts with a master requesting access to the bus from the arbiter. The
arbiter grants the request and the transfer begins, the decoder decodes the address placed on
the bus and selects a slave. The slave responds back to the master and the data transfer takes
place.
The advanced peripheral bus (APB)
APB is designed for low bandwidth control accesses, for example register interfaces on system
peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low
complexity signal list (for example no bursts).
-It is interface for a low frequency system
The AMBA extensible interface (AXI)
AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at
high performance, high clock frequency system designs and includes features that make it
suitable for high speed sub-micrometer interconnect:
separate address/control and data phases
support for unaligned data transfers using byte strobes
burst based transactions with only start address issued
issuing of multiple outstanding addresses with out of order responses
easy addition of register stages to provide timing closure.