1766 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.

11, NOVEMBER 1997

A 1-V Programmable DSP for

Wireless Communications
Wai Lee, Member, IEEE, Paul E. Landman, Member, IEEE, Brock Barton, Shigeshi Abiko,
Hiroshi Takahashi, Associate Member, IEEE, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro,
Masahiro Fusumada, Luat Pham, Frederic Boutaud, Member, IEEE, Emmanuel Ego,
Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar,
Robert H. Eklund, Member, IEEE, and Ih-Chin Chen, Senior Member, IEEE

Abstract— In an effort to extend battery life, the manufac-

turers of portable consumer electronics are continually driving
down the supply voltages of their systems. For example, next-
generation cellular phones are expected to utilize a 1-V power
supply for their digital components. To address this market, an
energy-efficient, programmable digital signal processing (DSP)
chip that operates from a 1-V supply has been designed, fab-
ricated, and tested. The DSP features an instruction set and
micro-architecture that are specifically targeted at wireless com-
munication applications and that have been carefully optimized
to minimize power consumption without sacrificing performance.
The design utilizes a 0.35-m dual-Vt technology with 0.25-m
minimum gate lengths that enables good performance at 1 V.
Specifically, the chip dissipates 17 mW at 1 V, achieving 63-MHz
operation with a power-performance metric of 0.21 mW/MHz. Fig. 1. Use of DSP in a cellular phone application.
Index Terms—CMOS digital integrated circuits, computer ar-
chitecture, flip-flops, integrated circuit design, low-power circuits, demodulation, and equalization. These functions require a DSP
low-power CMOS, phase-locked loops, semiconductor memories, that offers a high computational throughput. However, this
Viterbi decoding, wireless communications.
requirement is often at odds with the goal of minimizing power
consumption. This paper describes a fixed-point programmable
DSP designed for wireless communication applications that
I. INTRODUCTION addresses these dual constraints of lower power and higher
throughput [1]. This is achieved by operating at low voltage
T HE portable consumer electronics market is currently
undergoing a period of rapid growth. Wireless communi-
cation devices, such as cellular phones, represent an important
(1 V) while using a dual- process to maintain high perfor-
mance. The use of multiple threshold voltages to maintain
segment of this market. One of the keys to success in this a balance between speed and standby current is not new.
highly competitive arena is to keep products lightweight and Several processors have been designed which incorporate both
small. This places tight constraints on the size of the batteries high and low threshold voltage transistors on a single chip
that can be used and makes it extremely important to employ [2], [3]. Relative to the DSP presented here, however, these
energy-efficient circuits in the design of these products. As earlier low-power DSP’s have either incorporated much less
shown in Fig. 1, wireless systems rely heavily on embedded functionality ( 70 K transistors) [2] or have had higher power
digital signal processors (DSP’s) to perform critical commu- per unit throughput, in the range of 2 mW/MHz [3]. The chip
nication functions such as speech coding, channel coding, described in this paper has a power-performance metric of
0.21 mW/MHz and is a full-feature, 1.6-million transistor DSP
Manuscript received April 1997; revised June 3, 1997. with a large amount of on-chip memory and a rich set of
W. Lee, P. E. Landman, B. Barton, H. Tran, C. Lemonds, A. Shih, M. peripherals for interfacing to external devices.
Nandakumar, R. H. Eklund, and I.-C. Chen are with Corporate R&D, Texas The design of this DSP is described in several sections.
Instruments Incorporated, Dallas, TX 75243 USA.
S. Abiko, H. Takahashi, H. Mizuno, S. Muramatsu, K. Tashiro, and M. First, Section II describes the architecture. Next, Section III
Fusumada are with Texas Instruments Japan Ltd., Tokyo, 108 Japan. presents the implementation of the design, describing the
L. Pham is with Texas Instruments Incorporated, Stafford, TX 77477 USA. power management strategy and detailing the design of key
F. Boutaud was with Texas Instruments France, 06271 Villeneuve Loubet
Cedex, France. He is now with Analog Devices, Wilmington, MA 01887 circuits such as the clock generation and distribution network,
USA. the multiply-accumulate unit, and the memory subsystem.
E. Ego is with Texas Instruments France, 06271 Villeneuve Loubet Cedex, The multithreshold process that enables low voltage operation
France.
G. Gallo is with Texas Instruments Italia, 67051 Avezzano, Italy. is then described in Section IV. Finally, Sections V and VI
Publisher Item Identifier S 0018-9200(97)07855-4. present measured results and concluding remarks.
0018–9200/97$10.00  1997 IEEE
LEE et al.: 1-V PROGRAMMABLE DSP FOR WIRELESS COMMUNICATIONS
Fig. 2. High-level block diagram of DSP architecture.
II. ARCHITECTURE
The CPU uses a modified Harvard architecture as shown
in Fig. 2. In order to maximize throughput and energy ef-
ficiency, the architecture relies heavily on both pipelining
and parallelism [4]. For example, the CPU employs a six-
stage instruction pipeline divided as follows: 1) program
prefetch, 2) program fetch, 3) instruction decode, 4) operand
address generation, 5) operand read, and 6) execute/write.
Three separate data buses and one program bus coupled with
two data address generators and one program address generator
facilitate a high degree of parallelism. For instance, two reads
and one write operation can be performed in a single cycle.
This exploitation of concurrent processing techniques results
in a highly efficient instruction set, which in turn increases the
energy efficiency of the processor [5].
The CPU contains a 40-b arithmetic logic unit (ALU),
which can selectively feed one of two 40-b accumulators.
The accumulators are divided into three parts: a 16-b low-
order word, a 16-b high-order word, and eight guard bits.
By setting a status register bit, the ALU can function as
a single unit or as two 16-b ALU’s operating in parallel.
This dual 16-b mode is especially useful for the Viterbi
add/compare/select operation, as described in detail later in
this section. Furthermore, one of the ALU inputs can be
taken from a 40-b barrel shifter, allowing the processor to
perform numerical scaling, bit extraction, extended arithmetic,
and overflow prevention. Together with the exponent detector,
the shifter enables single-cycle normalization of values in an
accumulator.
The CPU also features a multiply-accumulate block capable
of a 17 17-b two’s-complement multiplication and a 40-b
addition in a single instruction cycle. The multiplier and ALU
can operate in parallel, allowing simultaneous execution of
multiply-accumulate (MAC) and arithmetic operations.
The DSP has a rich instruction set including single-
instruction repeat and block repeat operations, block memory
move instructions, instructions with two- or three-operand
reads, conditional store instructions, and arithmetic instruc-
tions with parallel load and store. To improve performance
and power on typical DSP algorithms, several dedicated
instructions are available including euclidean distance
1767
Fig. 3. Architectural components supporting compare, select, and store op-
eration used in Viterbi algorithm.
Fig. 4. State transition diagram and corresponding DSP code for a Viterbi
butterfly operation. The DADST and DSADT are the double 16-b add/subtract
instructions. CMPS is the compare/select/store instruction. k in the comment
section means two operations are done in parallel in the same clock cycle.
calculation, as well as finite impulse response (FIR) and
least mean square (LMS) filtering operations.
In addition to these built-in filtering instructions, the DSP
also contains a compare, select, and store unit (CSSU) which
accelerates the Viterbi computation required by many commu-
nication algorithms [6]. The hardware components that support
the Viterbi operator are shown in Fig. 3. This diagram is
best understood by examining the code for a Viterbi butterfly
operation, which is given in Fig. 4 along with the correspond-
ing state transition diagram. In this example, two old states
transition to two new states. For each new state, the objective
is to find which of two possible routes results in the maximum
path metric. By configuring the ALU in dual 16-b mode
using the C16 bit in Fig. 3, the four add/subtracts required
to calculate the candidate path metrics can be performed in
only two cycles. The results of the add/subtract operations are
stored in the two 40-b accumulators, A and B, and are fed to
the CSSU. In a single cycle, the CSSU is able to compare the
two 16-b words stored in one of the two accumulators, as well
as select and store the largest of these two words using the
result bus EB. In the same cycle, the decision is recorded in
the test/control (TC) flag bit of the status register and in the
1768
Fig. 5. Example illustrating the use of gated slave logic to reduce unneces-
sary switching activity.
16-b transition shift register (TRN). The information contained
in TRN can later be used by a back-tracking routine to find
the optimal path through the trellis. Therefore, it takes only
two cycles to complete the two compare, select, and store
operations. To summarize, the dual ALU mode and the CSSU
allow the Viterbi butterfly to be completed in four cycles as
opposed to the 20 required by a previous architecture. This
represents a substantial savings of both time and energy.
In addition to the CPU, the DSP also contains a substantial
amount of on-chip memory including a 6 K 16 b SRAM
and 48 K 16 b ROM divided into separate program and data
spaces. This large amount of on-chip memory is intended to
minimize off-chip memory accesses and, consequently, mini-
mize the overall power consumption of the system. Several
on-chip peripherals are available as well, including a 16-b
timer, a synchronous full-duplex serial port, a buffered full-
duplex serial port, and an 8-b parallel host interface. This
set of peripherals was designed to facilitate communication
between the DSP and the other components in the system. For
example, in a typical digital cellular phone, one serial port
can communicate with the RF modem; the other serial port
can interface with the audio subsystem; and the parallel host
interface can communicate with the microcontroller. The DSP
also contains emulation and test circuitry which implements
the JTAG (IEEE 1149.1) standard and allows access to all
on-chip resources.
III. CIRCUIT IMPLEMENTATION
In this section, we provide more details of the DSP design,
beginning with the power management strategy in Section III-
A. This leads into a description of the clock generation and
distribution network in Section III-B. Finally, Sections III-C
and III-D cover the MAC unit and the memory subsystem,
respectively.
A. Power Management Strategy
During active operation, power savings are realized by
extensive use of gated clocks (see Fig. 5). In particular, latches
are only clocked when useful data is available at their inputs.
This is achieved by locally gating the master clock with a data
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997
Fig. 6. High-level architecture of digital PLL.
ready signal. This signal is generated automatically by local
control logic using information from the instruction decoder.
The gated slave logic registers when data has been clocked
into the master latch and outputs an enable signal that gates the
slave clock. Thus, functional blocks are only activated when
they have valid data to process. Global clock gating is also
available and is controlled by the user through three power-
down instructions: IDLE1, IDLE2, and IDLE3. The IDLE1
instruction shuts down the CPU but the peripheral devices
and the system clock remain active; the IDLE2 instruction
shuts down the CPU and all the on-chip peripherals, though
the PLL remains active; and the IDLE3 instruction shuts down
the entire processor. In IDLE3 mode, the only source of power
consumption is the standby power of the entire chip which can
be substantially lower than the power during active operation.
However, the latency for the CPU to return to active operation
from the IDLE3 mode is also the largest since the on-chip PLL
has to acquire lock to the external clock source again, which
typically takes about 50 s. In summary, the chip utilizes a
hybrid power management strategy that is partially automated
and partially under user control.
B. Clock Generation and Distribution
The DSP uses an on-chip PLL for clock generation and
multiplication. Traditionally, the PLL’s used for this purpose
have been largely analog [7]. There are several reasons,
however, to consider using a more digital solution. Digital
logic, for example, exhibits much better noise immunity and
is less sensitive to process variations than analog circuitry.
Furthermore, unlike digital logic, the energy efficiency of
analog circuitry is actually worsened by aggressive voltage
scaling [8]. Moreover, the reduction in available headroom
makes analog design much more difficult at low voltage levels.
All of these factors led us to opt for a more digital approach.
1) PLL Architecture: The basic architecture of the PLL is
shown in Fig. 6. The reference input can be driven by either
an external clock source or a crystal resonator. In addition, it
can be used directly or can be divided down in frequency by
a factor of two or four. The output clock can be taken either
from the PLL or from one of these divided down versions of
the reference.
The core loop of the PLL is structurally similar to that of
an analog PLL, with the exception that a digital loop filter
replaces the traditional analog filter, and a digitally controlled
oscillator (DCO) replaces the voltage controlled oscillator
(VCO). The programmable frequency divider in the feedback
path enables the PLL to generate an output frequency that is a
LEE et al.: 1-V PROGRAMMABLE DSP FOR WIRELESS COMMUNICATIONS
factor of 1 to 15 higher than the reference. The combination of
feedforward and feedback frequency dividers allows the PLL
to generate 15 different integer-frequency multiples (1, ,
15), eight different half-frequency multiples (0.5, 1.5, , 7.5)
and eight different quarter-frequency multiples (0.25, 0.75, ,
3.75).
The operation of the PLL is as follows. The phase detector
compares the position of the reference clock edge to that of
the divided-down DCO edge. Depending on whether the DCO
edge lags or leads the reference, the phase detector outputs a
signal telling the DCO to increase or decrease its frequency.
If the two edges are aligned within the tolerance of the phase
detector, then no correction pulses are generated.
Next, the loop filter examines the phase detector output and
determines how to alter the DCO frequency. Since the loop
filter is a synchronous digital circuit, a local clock signal is
required. Therefore, the first stage of the circuit is a clock
generation unit that creates a loop filter clock pulse whenever
it sees a corresponding pulse on the phase detector output.
This clock drives the main loop filter logic, which realizes a
first-order low-pass filter designed to guarantee loop stability.
The output of the loop filter is a 6-b digital control word
that specifies at what frequency the DCO should operate. The
final stage of the loop filter is a synchronizer. The purpose of
this circuitry is to prevent the DCO frequency from changing
midcycle, which could give rise to glitches in the output clock.
The synchronized output of the loop filter then passes to the
DCO. The DCO produces a square wave whose period is lin-
early related to the DCO control word. This signal is then fed
back to the phase detector through a programmable frequency
divider. The frequency locking action of the feedback loop
guarantees that resulting in a DCO frequency
equal to times the reference.
2) Digitally Controlled Oscillator: Since the DCO period
is controlled by a digital input, the PLL cannot generate a
continuous range of frequencies, but rather produces a finite
number of discrete frequencies. Because the quantization of
the DCO period sets some fundamental limits on the PLL’s
achievable jitter, it is desirable for the DCO to have a small
step size. Traditional DCO’s generate their outputs by dividing
down a fixed, high-frequency clock source [9]. This type of
implementation makes it extremely difficult to achieve a small
step size since it is limited by how fast the clock source and
the associated divider can operate. For example, to achieve a
200-ps step between periods would require a 5-GHz oscillator
and counter! The DCO used in this design overcomes this
difficulty by synthesizing a signal with the desired frequency
rather than deriving it from a high frequency source. The
schematic for the DCO is shown in Fig. 7. The circuit uses
a binarily weighted switched capacitor array to control the
frequency of oscillation. More specifically, inverter U2 drives
a variable load, the size of which is controlled by turning
on or off the capacitors labeled through where
is the number of bits in the loop filter output (six in our
design). The capacitors are realized as NMOS transistors with
their source and drain tied together. The gate areas of the
transistors are binarily weighted such that if the on-capacitance
of the smallest transistor is , the capacitance of transistor
1769
Fig. 7. Schematic of digitally controlled oscillator (DCO) with
switched-capacitor frequency control.
is roughly . A capacitor is turned on by pulling the
correspond digital control bit, , to . This grounds the
source/drain and creates an inversion layer in the NMOS
channel contributing to the capacitive load on node .
The capacitor is turned off by pulling to ground, placing the
transistor in the depletion region, and significantly reducing its
gate capacitance to where . Therefore, the
load capacitance on node is roughly given by
where is the value of the
digital control word, is the node’s parasitic capacitance,
and
This causes the delay of inverter U2 to be linearly related
to the digital control word. The step size between adjacent
oscillation periods is controlled by sizing and U2, and the
range is controlled by , U2, and the number of bits in the
control word. Schmitt trigger U3 is used to sense when node
has reached its high or low thresholds at which point a sharp
edge is generated. The signal then travels through a fixed delay
stage (which contributes to the offset of the frequency range)
and is fed back to NAND U1, completing the loop. Finally,
reset devices U4, U5, M , and M are included, to ensure that
Node is at the rails at the start of each charging cycle.
The result is a DCO capable of excellent frequency res-
olution whose period is given by .
Measurements from silicon indicate a typical RMS phase jitter
of about 45.5 ps as shown in Fig. 8.
3) Clock Distribution Network: The clock distribution net-
work is carefully tuned to minimize power dissipation. To
reduce the significant short-circuit currents typical of large
clock drivers, a hierarchical clock buffering scheme is used.
Local clock buffers are placed as close to the clock signal
destination points as possible to minimize skew. After the
required rise and fall times of the clock signal at the inputs
to scannable register latches (SRL’s) are specified, the size
of the clock drivers and interconnect widths are tuned to
satisfy the propagation delay requirements with minimal power
dissipation.
Power is further reduced by careful design of the SRL’s
to minimize clock loading as shown in Fig. 9. In the new
design [Fig. 9(b)] the clock signals drive two NMOS devices
instead of feeding two NMOS and two PMOS devices as in
1770
Fig. 8. Histogram of typical phase jitter for digital PLL.
(a)
(b)
Fig. 9. Comparison of (a) conventional CMOS latch to (b) lower-power latch
which reduces clock loading.
the conventional version [Fig. 9(a)]. When the data is high,
it is driven differentially into the cross-coupled inverter to
ensure good performance even at low supply voltages. A 15%
reduction in power was obtained, while achieving a 15% speed
improvement and a 50% reduction in area. The large area
reduction is due to the use of primarily NMOS devices, which
reduces isolation spacing requirements.
C. Multiply-Accumulate Unit
The multiply-accumulate (MAC) unit on this chip is com-
posed of a 17 17-bit Wallace tree multiplier coupled with
a 40-b carry-lookahead adder. This MAC unit is capable of
performing a nonpipelined multiply-accumulate operation in
a single clock cycle. The multiplier can operate on signed,
unsigned, and signed/unsigned 16-b operands. Both integer
and fractional modes, as well as two’s-complement rounding
and overflow detection, are supported in this MAC unit. The
Wallace tree architecture was chosen not only because of its
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997
Fig. 10. Block diagram of the MAC unit.
inherent speed advantage over the array multiplier, but also be-
cause of its lower dynamic power consumption [10]. The speed
advantage of the Wallace tree comes from the reduction in the
height of the carry-save adder tree—from nine to five stages
in our case. The improvement in dynamic power consumption
comes from a large reduction in spurious switching events
at the internal nodes of the multiplier, resulting from balanced
delay paths in the Wallace tree. The architecture of the Wallace
multiplier used on this chip consists of a 3 : 2 counter stage,
followed by two consecutive 4 : 2 counter stages, as shown
in Fig. 10. The 4 : 2 counter is constructed by cascading two
carry-save adders. A 23% power reduction and 25% speed
improvement are achieved by the Wallace tree architecture
over the array architecture using the same carry-save adder.
The carry-save adder makes extensive use of transmission gate
logic to minimize transistor count and power consumption
[11]. The transistor sizes were carefully tuned so that the
variations in delay for different input signal combinations
are minimized. The tight output delay distribution helps to
minimize the overall dynamic power consumption in the
multiplier [10]. SPICE simulations at 1 V reveal a worst-case
delay of under 5 ns.
D. Memory Subsystem
The on-chip memory subsystem includes a 6 K 16 b
SRAM and 48 K 16 b ROM divided into separate program
and data spaces.
1) Random-Access Memory: The memory subsystem al-
lows two data operand reads or a long (32-b) read from any
one of the three 2 K 16 b on-chip SRAM blocks in a
single machine cycle. If the program bus is used for coefficient
access, three operands can be read in a single cycle. A divided
word line architecture is used in the SRAM to reduce power
[12]. Each 2 K 16 b SRAM block is divided into two banks
as shown in Fig. 11. The banks in turn are subdivided into
four 256 16 b arrays, each with its own local word line
driver. Consequently, each memory access only activates 1/8
of the entire array, thereby reducing the power consumption.
The sense amplifier employs a latch-type design to reduce the
static power dissipation and to ensure proper operation even
at very low supply voltages.
LEE et al.: 1-V PROGRAMMABLE DSP FOR WIRELESS COMMUNICATIONS
Fig. 11. On-chip SRAM architecture illustrating divided word line strategy
for power reduction.
Fig. 12. Architecture of 8 K 2 16 b building block used to construct data
and program ROM’s.
High transistors are used in the six-transistor memory
cell to keep the standby current to a minimum, while low
transistors are used in the sense amplifier and all peripheral cir-
cuitry to allow for high-speed operation at 1 V and below. The
dependence of the access time as a function of the threshold
voltage will be described in greater detail in Section IV.
2) Read-Only Memory: There are two large ROM’s in the
DSP: a 32 K 16 b program store ROM and a 16 K
16 b coefficient data ROM. Both ROM’s use the same
basic architecture and cell design. They are constructed using
multiple occurrences of a basic building block—an 8 K
16 b ROM, illustrated in Fig. 12.
These are diffusion-programmed ROM’s incorporating a
number of design features to reduce power dissipation. They
utilize selective precharge of bit lines, for essentially zero
standby power dissipation and low operating power consump-
tion. A 16 : 1 column mux ratio minimizes bit line capacitance
and, therefore, access time and power consumption. The
diffusion-programming feature results in a 40% memory array
area savings with respect to via- or contact-programmed cores
of the same capacity, further lowering bit line and word line
capacitance and, thus, power. The ROM’s feature dynamic
page selection, which allows either 16-b or 32-b access, to
meet system architecture requirements. The cell bit line contact
1771
TABLE I
KEY PROCESS TECHNOLOGY PARAMETERS
Technology 0.35 m twin-well, dual-Vt ; CMOS with triple-metal
Gate Length 0.25 m
Gate Oxide 5 nm
High Vt 0.4 V
Low Vt 0.2 V
is shared by two adjacent cells, to optimize both bit line
precharge/discharge time and power consumption.
To improve ROM performance at low voltage, additional
steps were taken. For example, all peripheral circuitry employs
low devices; however, as in the SRAM, high devices
are used in the array to minimize standby current. In addition,
horizontal metal-2 straps were added every 32 cells along the
word lines. Vertical metal-1 ground lines were connected to
each other through metal-2 jumper lines to provide a more
solid ground to the array. And finally, the row deselection
circuitry was optimized to reduce word line recovery time,
permitting a shorter cycle time.
IV. PROCESS
The chip was fabricated using a 0.35- m, dual- twin-
well CMOS process with three layers of metal. The minimum
length of patterned gate poly is 0.25 m. The gate oxide
thickness is 5 nm. To fabricate both low and high transistors
on the same chip with minimal process overhead, a surface
counter-doping implantation was performed on the channels
of the low transistors in addition to the regular channel
implant [13]. The nominal threshold voltages (defined as the
gate voltage when the drain current reaches a current level
of 0.1 A where and are the drawn width
and length of the transistor) are 0.4 and 0.2 V, respectively.
The threshold voltages quoted in an earlier publication [1] are
different from the values used here. The discrepancy stems
from a different definition of threshold voltage when
A adopted in the earlier publication. The
leakage current of the high and low devices are below
1 nA/ m and 1 A/ m, respectively. The drive current of the
low (LVT) transistors is typically twice that of the high
(HVT) devices. Key process characteristics are summarized in
Table I.
To gain a better insight into the impact of threshold voltages
on the performance of this DSP, SPICE simulation results of
one of the critical paths, namely the on-chip SRAM access
time, are presented in Table II. SPICE simulations reveal that
the speed of the SRAM is not significantly degraded by using
threshold voltages as high as 0.4 V in the memory cell. The
speed of the SRAM is strongly dependent, however, on the
threshold voltage used in the peripheral circuitry, which is
therefore kept low. For a low and high of 0.2 and 0.4 V,
respectively, SPICE simulations indicate an access time of
about 6 ns.
V. RESULTS
The chip measures 5.65 5.50 mm and contains 1.6
million transistors. A photomicrograph of the die is shown
in Fig. 13. The DSP was functional on first silicon and was
1772 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997

TABLE II
DEPENDENCE OF SRAM ACCESS TIME ON THRESHOLD
VOLTAGE AT 1 V POWER SUPPLY AND NOMINAL CONDITIONS
Vt of LVT (V) Vt of HVT (V) Tacc (ns) Relative Tacc
0.2 0.40 6.16 100%
0.2 0.35 5.87 95%
0.2 0.30 5.62 91%
0.05 0.40 5.00 81%
0.05 0.35 4.71 76%
0.05 0.30 4.46 72%

Fig. 14. Maximum operating frequency as a function of supply voltage.

Fig. 15. Power consumption as a function of frequency for a fixed supply

Fig. 13. Die photo of 1-V DSP implemented in 0.35-m, dual-Vt CMOS
technology.
packaged in a 128-pin TQFP. Since the power consumption
of the DSP depends on the instructions being executed, it is
necessary to specify the benchmark used during testing. The
results presented here were obtained while repeatedly execut-
ing a 16-tap FIR filtering application. This algorithm heavily
exercises the MAC unit, resulting in a fair—if not slightly pes-
simistic—measurement of power consumption. Furthermore,
the program was configured to execute from on-chip memory,
ensuring that the critical (SRAM access) path was exercised.
The performance of the DSP as a function of supply voltage
is shown in Fig. 14. In order to highlight the improvement
made by this chip, curves are given for both the 1-V (0.35- m)
part described in this paper and for an earlier chip having the
same architecture and circuit implementation but fabricated
using a 0.6- m, 3.3-V process with a single standard threshold
voltage. The 0.35- m chip is functional down to 0.6 V,
reaching 63 MHz at 1 V and 100 MHz at 1.35 V. This amounts
to roughly a 10 performance improvement relative to the
0.6- m part for the same 1-V supply.
Fig. 15 gives the power versus operating frequency curves
for the two devices. To a fairly high degree of accuracy, power
is a linear function of frequency. The slope of this curve is
a power-performance metric for active operation in units of
mW/MHz. This metric accounts only for dynamic power. The
0.35- m chip achieves 0.21 mW/MHz at 1.0 V, which is a
19 times improvement over the 4.0 mW/MHz of the 0.6- m
chip at 3.3 V. At 60 MHz, this chip consumes only 17 mW,
which is 15 times less power than the 3.3 V chip. The power at
voltage.
60 MHz is improved by 15 times, rather than 19 times, because
of the 4-mW standby power, which produces a dc offset in the
power versus frequency curve (see the LVT HVT curve in
Fig. 16). The relatively large standby power can be attributed
to the extensive use of low threshold voltage transistors.
One way to reduce the standby power would be to avoid the
use of LVT transistors. In fact, a second chip fabricated with all
HVT devices in the same 0.35- m technology had a measured
standby power of less than 50 W at 1 V. Unfortunately, this
HVT version of the chip can only reach 35 MHz at 1.0 V.
In order to attain the 63 MHz achieved by the LVT HVT
chip, the HVT chip must be operated at 1.3 V. At 1.3 V and
63 MHz, the HVT-only chip consumes 22.6 mW, which is
32% more power than the LVT HVT chip operating at 1.0 V.
Fig. 16 compares the power-performance metric of the HVT-
only chip operated at 1.0 and 1.3 V, respectively, with that
of the LVT HVT chip operated at 1.0 V. The figure shows
that going from 1.0 to 1.3 V degrades the power-performance
metric from 0.21 to 0.36 mW/MHz.
An even better solution is to continue to use both low and
high devices, but to also add HVT switches (controlled
by the power-down modes) in series with the supply. The
sizing of these devices would be dictated by the peak current
requirements of the various modules in the chip. With properly
sized switches, the DSP at 1 V should approach the 63 MHz
performance of the current LVT HVT design, but with a
standby power closer to the 50 W of the HVT-only design.
Table III shows the approximate distribution of the power
consumption at 1.0 V and 63 MHz for the LVT HVT chip.
LEE et al.: 1-V PROGRAMMABLE DSP FOR WIRELESS COMMUNICATIONS 1773

Fig. 16. Power consumption as a function of frequency for the 0.35-m LVT
+ HVT chip and the HVT-only chip. Two curves are shown for the HVT-only
Fig. 17. Energy-delay product as a function of supply voltage.
chip: one is for a 1.0-V supply and another for a 1.3-V supply. The curve for
the LVT + HVT chip is obtained with a 1.0-V supply. TABLE IV
CHIP STATISTICS AND PERFORMANCE DATA
TABLE III Chip size 2
5.65 5.50 mm2 =31.1 mm2
APPROXIMATE POWER BREAKDOWN OF DSP Transistor count 1.6 million
Component Approximate Power Fraction of Total Power Package 128-pin TQFP
Consumption (mW) Speed at room temperature 63 MHz at 1 V, 100 MHz at 1.35 V
Clock 4.4 26% Power 17 mW at 1 V
Datapath 6.5 38% Power–Performance Metric 0.21 mW/MHz at 1 V
Control 3.1 18%
Memory 3.1 18%
Total 17 100% global clocks. A flexible PLL-based clock generator/multiplier
gives the user fine-grain control over the clock frequency as
The power-delay product has been used for many years as well. To facilitate efficient low-voltage operation, the tradi-
a figure of merit in evaluating digital circuits. Recently, it has tional analog PLL has been replaced with an almost entirely
been proposed that the energy-delay product (or power-delay- digital implementation.
delay product) is a better metric to analyze the tradeoff be- The design makes use of a 0.35- m dual- technology
tween energy efficiency and performance [14]. Fig. 17 shows with 0.25- m gate lengths to enable good performance at 1 V.
the energy-delay product of the HVT LVT and HVT-only At this voltage, the chip dissipates 17 mW and operates at
chips as a function of supply voltage. The LVT HVT chip 63 MHz with a power-performance metric of 0.21 mW/MHz.
achieves a minimum of 4.2 nJ-ns at 1.0 V. Thus, 1.0 V is Moreover, the device is functional down to 0.6 V and reaches
indeed the optimal operating voltage for this chip. The HVT- 100 MHz at 1.35 V. These results are indicative of the energy
only chip achieves a minimum of 5.7 nJ-ns at 1.20 V. The efficiency that can be achieved using low-voltage digital
shift of the minimum to a higher voltage is due to the higher design techniques. As cellular phone manufacturers continue
threshold voltage in the HVT-only chip. For comparison, the to drive down the system supply voltage, the trend toward
0.6- m DSP achieves its minimum at 1.8 V with a minimum migrating more functionality to the digital domain is likely
value almost an order of magnitude higher than that of the to continue. This will fuel the demand for high-performance,
1 V chip. low-power DSP’s. The results presented here demonstrate
Some of the more important chip statistics presented in this that high performance and low power consumption can be
section are summarized in Table IV. achieved simultaneously through innovative technology and
digital design techniques.
VI. CONCLUSIONS
This paper has described a low-power, fixed-point pro- ACKNOWLEDGMENT
grammable DSP optimized for wireless communication ap- The authors would like to thank D. Nowlen for mask
plications. From the outset, the DSP was architected for low generation; E. Born, G. Stacey, and B. Garcia for assistance
power consumption, employing a bus and memory structure in testing; B. Strong and B. Fleck for SRAM design; A.
that facilitate a high degree of parallelism and a specialized Amerasekera and C. Duvvury for advice on ESD design; and
instruction set that enables efficient execution of common B. Hewes, A. Shah, P. Yang, S. Shichijo, and G. Frantz for
communication algorithms such as the Viterbi butterfly. Fur- their encouragement and support.
thermore, the DSP includes a rich set of peripherals and a
large amount of on-chip memory (54 K 16 b) that help to REFERENCES
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Sept. 1996.
Wai Lee (S’80–M’89) received the B.S., M.S.,
and Ph.D. degrees in electrical engineering and
computer science from the Massachusetts Institute
of Technology, Cambridge, in 1983, 1986, and
1988, respectively.
From 1988 to 1993, he was a Research Staff
Member at IBM T. J. Watson Research Center in
Yorktown Heights, NY, where he was first involved
with the device design for 0.5-m Si and SiGe
bipolar transistors. He later joined the VLSI design
department and led a circuit design team working
on a high-performance CMOS RISC microprocessor. In 1993, he joined
the low power design branch of the Integrated System Laboratory of Texas
Instruments, Dallas, TX, as a Member of Technical Staff. In 1997, he became
the manager of the DSP Circuits branch in the DSP R&D Center. His
present interests include low-power and high-performance DSP design for
communication applications. He has authored or co-authored more than 30
technical papers.
Paul E. Landman (S’92–M’95) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering
and computer science from the University of Cali-
fornia, Berkeley, in 1989, 1991, and 1994, respec-
tively. His research focused on low-power digital
design techniques and tools with an emphasis on
DSP applications.
After completing his dissertation, he joined the
low-power design branch of the DSP R&D Center of
Texas Instruments, Dallas. His initial research there
focused on low-power algorithms, architectures, and
circuits for portable video applications. Most recently, he participated in
the development of a low-power programmable DSP targeted at wireless
communication applications.
Dr. Landman is a National Science Foundation Fellowship recipient and is
a member of Tau Beta Pi and Eta Kappa Nu.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997
Brock Barton received the B.S and B.A. degrees
in physics and mathematics, respectively, from the
University of Texas, Austin, in 1966. He received
the Ph.D. degree in solid-state physics from the
Massachusetts Institute of Technology, Cambridge,
in 1971.
He is currently a Texas Instruments Fellow, in
the DSPS R&D Center of TI’s Corporate R&D
organization, Dallas. He joined TI in 1972 and has
worked in TI’s Equipment Group, Central Research
Laboratories, Semiconductor Group, and Semicon-
ductor R&D, a part of TI’s Corporate R&D organization. He was responsible
for the design of TI’s first standard cell library. He has worked on a
number of different programs, including CCD imager and memory design and
development, CMOS calculator chip product engineering, and MOS memory
and microprocessor process development, prior to helping create TI’s ASIC
technology. More recently, he was responsible for fuzzy logic IC development
and 1V DSP chip design in the DSPS R&D Center. He is the author or
co-author of more than 25 technical papers and publications and holds five
patents.
Shigeshi Abiko received the B.S. degree in
computer science from the Scientific University
of Tokyo, Japan, in 1982.
He joined the Tokyo Design Center, Texas
Instruments Japan Ltd. in 1982 and then worked on
the development of programmable DSP devices. He
is currently a Senior Member of the Technical Staff.
Hiroshi Takahashi (A’87) was born in Saitama pre-
fecture, Japan, on November 11, 1959. He graduated
from Shohoku College, (Sony gakeun) Kanagawa,
in 1980. His major was electronics.
In 1980, he joined Dai-Nippon Printing Co. In
1984, he joined Texas Instruments (TI) Japan Ltd.
He has been engaged in DSP design since 1985 and
developed several DSP devices including EPROM
versions at TI France and at TI locations at Houston,
Dallas, and Lubbock, TX. He is currently a Senior
Member of the Technical Staff at TI.
Hiroyuki Mizuno was born in Aichi prefecture,
Japan, on February 23, 1969. He received the B.S.
and M.S. degrees in engineering from Tokyo Uni-
versity, Japan, in 1991 and 1994, respectively.
In April 1994, he joined Texas Instruments Japan
Ltd., Tokyo. Since then he has been engaged in DSP
development work.
Shigetoshi Muramatsu was born in Nagano pre-
fecture, Japan. He received the B.E. degree in
applied physics from the University of Nagoya,
Aichi, Japan, in 1987.
He joined Texas Instruments Japan Ltd., Tokyo,
in 1987. Since then, he has been engaged in the
development of several DSP devices.
LEE et al.: 1-V PROGRAMMABLE DSP FOR WIRELESS COMMUNICATIONS
Kenichi Tashiro was born in Osaka prefecture,
Japan, on January 30, 1965. He received the B.E.
degree in electronics from the Osaka Institute of
Technology, Osaka, Japan in 1987.
He joined Texas Instruments Japan Ltd., Tokyo,
in 1987. Since then, he has been engaged in the
development of DSP devices.
Masahiro Fusumada received the B.E. degree in
applied physics from the University of Tokai, Japan,
in 1987.
He joined Texas Instruments Japan Ltd., Tokyo,
in 1987. Since then, he has been engaged in the
development of several DSP devices, including the
design of embedded SRAM’s.
Luat Pham received the B.S. degree in electrical
engineering from the Oregon State University, Cor-
vallis, in 1980.
He join Texas Instruments, Stafford, TX, in 1980.
From 1980 to 1989 he worked as a VLSI De-
sign Engineer developing mega-modules and cell
libraries. From 1989 to 1996 he worked as VLSI
Design Engineer developing submicrometer embed-
ded SRAM and ROM silicon compilers in support
of application-specific product designs. In 1996,
he joined high-performance DSP program as VLSI
Design Engineer developing floating-point datapath circuits. He holds one
patent with three others pending. His interests are in the areas of design for
reuse, high-performance datapath, and memory compiler design.
Frederic Boutaud (M’88) received the diplome
d’ingenieur in electricity and electronics from Ecole
Centrale de Lyon, France, in July 1978.
After two years working on computers for air-
craft automatic pilot, he joined Texas Instruments,
Villeneuve Loubet, France, in 1980, where he be-
came a Senior Member of Technical Staff and
a Design Manager. He has been working mainly
on digital signal processor architecture and design,
digital filters for delta–sigma converters, and low
power design for telecommunication applications.
He authored and co-authored several papers and holds more than 12 patents
in the area of digital design, delta–sigma converters, video processor and DSP
architecture. In 1996, he moved to Boston, MA, and joined the Communication
Division of Analog Devices where he is currently a Design Manager.
1775
Emmanuel Ego received the engineer degree
in microelectronics from Institut Superieur
d’Electronique du Nord, Lille, France, in 1992.
He joined Texas Instruments France, Villeneuve
Loubet, in December 1994. He has been designing
PLL’s for DSP’s circuits since then. He is now
involved in design of digital blocks to be integrated
in next generation of low-power DSP cores.
Girolamo Gallo received the master’s degree in
physics magna cum laude from Naples University,
Italy, in 1989.
He joined TI Italy, Avezzano, as an IC Design
Engineer in 1989. In 1989–1990 he participated in
the 16-Mb DRAM design in Houston, TX. Back in
Italy, he was involved in the design of application
specific nonvolatile memories. In 1992–1994 he was
Project Manager for the Hand Printed Character
Recognition (HPCR) program, aimed at devising
and implementing new handwriting recognition al-
gorithms to be ported to pen-computing systems. He is currently a Member of
the TI Semiconductor Group Technical Staff and the Team Leader for ROM
and Flash EEPROM memories development at the TI European MOS Memory
Design Center in Avezzano, Italy. He holds nine patents and has published or
presented several papers in international technical journals and conferences.
Hiep Tran, photograph and biography not available at the time of publication.
Carl Lemonds received the B.S. and M.S. degrees
in electrical engineering from the University of
Missouri at Columbia.
During graduate school he joined Texas Instru-
ments in Lubbock, TX, working in the consumer
products division. Later, he joined Texas Instru-
ments in Dallas working as a Design Engineer on
catalog CMOS products. In 1984 he joined the
Defense Systems group where he worked on various
designs using CMOS gate arrays and standard cells.
He transferred to Corporate Research as a Member
of Technical Staff in 1989 and worked on TI’s first BiCMOS gate array. Much
of his recent work has been in the area of low power multipliers. Currently, he
is researching high-performance circuit techniques for multipliers and other
CMOS datapath circuits for DSP core applications.
Albert Shih received the B.S. degree in electrical
engineering from National Taiwan University, Tai-
wan, in 1987 and the M.S. and Ph.D. degrees in
electrical engineering from the University of Texas
at Austin in 1991 and 1994, respectively.
He spent the summer of 1991 at Texas Instru-
ments, working on the modeling of crosstalk in
multilevel interconnect VLSI systems. In 1994, he
joined the Submicron Logic Process Development
group of Texas Instruments, Dallas, where he was
involved in the device design and yield enhancement
of logic products. Since 1995, he has worked on low-power CMOS device
and process integration and the prototyping of the first fully functional 1-V
DSP chip presented in this paper. Currently, he is engaged in the design of
high performance dynamic random access memory circuits.
1776
Mahalingam Nandakumar was born in Madras, India, on December 10,
1964. He received the B. Tech degree in electrical engineering from the
College of Engineering, Trivandrum, India, in 1987 and the M. Tech degree
in electrical engineering with specialization in integrated circuits and systems
from the Indian Institute of Technology, Madras, India. He received the Ph.D.
degree in electrical engineering from North Carolina State University, Raleigh,
in 1993.
In his doctoral thesis work, he experimentally demonstrated a new MOS
gated power semiconductor device called the base resistance controlled
thyristor (BRT) for the first time. Since 1993 he has been employed at the
Semiconductor Process and Design Center of Texas Instruments, Dallas, where
he has been responsible for developing a 0.25/0.18-m CMOS technology for
low power applications. His research interests include development of novel
semiconductor device structures and submicrometer CMOS device design.
Robert H. Eklund (M’86) received the B.S. degree
from Davidson College, Davidson, NC, in 1974 and
the Ph.D. degree in chemistry from the University
of Texas at Austin in 1979.
After graduation, he joined Texas Instruments,
Dallas, as a Member of the Technical Staff. Since
joining Texas Instruments, he has worked in the
area of materials characterization and on process
development and integration for various programs at
TI including Schottky diode processes for the VH-
SIC STL program, submicrometer bipolar process
development, BiCMOS on SIMOX process development, and submicrometer
CMOS and BiCMOS process development. Currently, he is a TI Fellow and
Manager of the Logic Process Technology branch responsible for the CMOS
and BiCMOS process integration. He has authored and coauthored numerous
papers and patents issued in the field of microelectronics.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997
Ih-Chin Chen (S’85–M’86–SM’96) received the
B.S. degree in electrical engineering from National
Taiwan University in 1980 and the M.S. and Ph.D.
degrees in electrical engineering and computer sci-
ences from the University of California, Berkeley,
in 1984 and 1986, respectively.
From 1980 to 1982, he served as a Teaching Offi-
cer in the Electronic Training Center of the Chinese
Army Missile Command. From 1983 to 1986, he
was a Postgraduate Researcher at the University
of California, Berkeley. He joined Semiconductor
Process and Design Center, Texas Instruments, Dallas, in 1987. From 1987
to 1991, he had worked on transistor and isolation design, storage dielectrics
development, and cell leakage reduction for 4, 16, and 64 Mb DRAM. Since
1991, he has been the Manager of Advanced Transistor/Isolation branch
focusing on high-performance CMOS for advanced microprocessors, 1 V
CMOS for low power applications, transistor and isolation design for 256 Mb
DRAM, shallow trench isolation, and sub-0.1 mm device research. He was
elected as a TI Fellow in 1996. He holds several patents, and has authored
or co-authored 88 technical papers.
Dr. Chen has served on several international conferences, including IEDM
(1993–1995 as a Program Committee Member and 1996 as the Subcommittee
Chairman of the CMOS Devices and Reliability Subcommittee), Device
Technology Conference of SPIE Microelectronic Manufacturing Symposium
(1995–1996, as the Conference Chairman), IEEE Symposium on Low Power
Electronics (1996–1997, as a Program Committee Member), and the Interna-
tional Symposium on VLSI Technology, Systems, and Applications (1997, as
a Program Committee Member).