 Introduction

 Multifunction Implementation
 The general Architecture Of Reconfigurable Processor
 Architecture
 Programmable I/O
 Technologies Used In Chip
 Design Process
 Advantages and Disadvantage
 Applications
 Future
 Conclusion
 A reconfigurable processor is a microprocessor with erasable hardware
that can rewire itself dynamically.

 This allows the chip to adapt effectively to the programming tasks

demanded by the particular software they are interfacing with at any
given time.

 Reconfigurable processor chip usually contains several parallel

processing computational units knows as functional blocks.
 While reconfiguring the chip, the connections inside the functional
blocks and the connections in between the functional blocks are
changing,

that means when a particular software is loaded the

present hardware design is erased and a new hardware design is
generated by making a particular number of connections active while
making others idle.

 This will define the optimum hardware configuration for that particular
software.
 It takes 20 microseconds to reconfigure the entire processing array.

 Reconfigurable processors are currently available from chameleon

systems, Billions of Operations (BOPS), and PACT (Parallel Array
Computing Technology).

 Among those only Chameleon is providing a design environment, which

allows customers to convert their algorithms to hardware configuration
by themselves.
 In a conventional ASIC or FPGA, multiple algorithms are implemented as
separate hardware modules. Four algorithms would divide the chip into
four functional areas.

 With Reconfigurable Technology, the four algorithms are loaded into the
entire reconfigurable Fabrics one at a time.

 First, the entire Fabrics is dedicated to algorithms.

1; During this processing time, algorithm 2 is loaded into the
background place. In a single clock cycle, the entire Fabric is swapped
to algorithm.

2; during this processing time, algorithm.

3 is loaded into the background plane. The entire reconfigurable fabric

is dedicated to just one algorithm at a time.
 So finally the result is: much higher performance, lower cost and
lower power consumption.
 Machine design supposes that some pins are considered as the configuration
inputs and another as data or control inputs and outputs.

 The most important parts are the logic circuits, which configure function
blocks according to data in the configuration memory.

 The various possible connections between functional blocks are encoded to

bits known as configuration bits. Resulting configuration stream is
downloaded into configuration memory through configuration inputs.
 32-bit ARC (Automation And Remote Control) processor

 64 bit memory controller

 32 bit PCI (Peripheral Component Interconnect) controller

 Reconfigurable processing fabric (RPF)

 High speed system bus

 Programmable I/O (160 pins)

 DMA subsystems

 Configuration Subsystem
 RCP (Representative Concentration Pathway) includes banks of
Programmable I/O (PIO) pins which provide tremendous bandwidth.

 Each PIO (Person of Indian origin) bank of 40 PIO pins delivers 0.5 GB
bytes/sec I/O bandwidth.
 1. E-configurable Tm Technology:

 This technology reconfigure fabric in one clock cycle and increases

voice/data/video channels per chip.

 As mentioned earlier each slice can be configured independently.

 Swapping the Background plane into the Active Plane requires just one
clock cycle. With e configurable technology; the four algorithms are
loaded into the entire reconfigurable processing fabric one at a time.
2. C – Side Development Tools :

 With this software development tools , Chameleon Systems are

providing the ability for the customers to do the programming
themselves thus keeping the secrecy of their algorithms.

 The chameleon systems integrated development environment is a

complete toolkit for designing, and verifying RCP designs.

 C-Side uses a combined C language and Verilog flow to map algorithms

into the chip’s reconfigurable processing fabric(RPF).
3. E- bios:

 It provides a interface between the Embedded Processor

System and the Fabric.

 e-Bios provides resource allocation, configuration management

and DMA services.

 The e-BIOS are automatically generated at compile time, but

can be edited for precise control of any function.
 Can create customized communications global signal processors

 Increased performance and channel count

 Can more quickly adapt to new requirements and standards

 Reducing power
 Reducing manufacturing cost

 Inertia – Engineers slow to change

Inertia is the worst problem facing reconfigurable computing

 RCP designs requires comprehensive set of tools

 ‘Learning curve’ for designers unfamiliar with reconfigurable logic

Wireless Base Stations :

 The reconfigurable technology mainly focuses on base stations and their

unpredictable combination of voice and data traffic.

 Base-station infrastructure will have to be adaptive enough to

accommodate those requirements. With a fixed processor the channels
must be able to support both simple voice calls and high-bandwidth data
connections.
Wireless Local Loop (WLL):
 Reconfigurable technology is widely applied in wireless local loops
also because of their high processing power, bandwidth and
reconfigurable nature.

High-Performance DSL (Digital Subscriber Line Technology):

 DSL technology brings high Bandwidth to homely users.

Software-Defined Radio (SDR):

 SDR concept is applied in cell phone Technology.
 Chameleon chips, also known as morphable computing chips, are
a new type of computer chip that can change their architecture on
the fly to optimize their performance for different tasks.

 One potential application of chameleon chips is in the field of

artificial intelligence and machine learning.

 These chips could be used to optimize the performance of neural

networks and other machine learning algorithms, allowing for
faster and more accurate processing of large amounts of data.
 These new chip called chameleon chips are
able to rewire themselves on the fly to create the exact hardware
needed to run piece of software at the outmost speed. Its
applications are in, data-intensive internet, DSP wireless base
stations, voice compression, software-defined radio.