Question Bank : ETU623 C Electronic Design Techniques with HDL (Dr P R Deshmukh)

1. Describe the various data types(net, register) supported by Verilog?

2. Explain the purpose of various complier directives? Give an example?
3. What is difference between initial and always statement?
4. Elaborate various verilog programming style?
5. Explain the keyword module, initial, assign, parameter statement?
6. Explain various data value set supported by Verilog , with example?
7. Explain various operators supported by verilog and order of precedence?
8. Explain bit wise , reduction operator and conditional operator?
9. Explain the concept of Concatenation and Replication with example?
10. Explain scalar and vector data types example?
11. Describe various built in primitive gates (gate level modelling) with resolution function /table?
12. Explain various mos switches supported by verilog?
13. Explain various Gate delays?
14. Explain module Instantiation and array of instances concept?
15. Explain user defined primitive? Give example of combinational and sequential user defined
primitive?
16. Explain the concept of strength associated with logic levels ?
17. Model/write verilog code and test bench for
a. Half adder
b. Full adder
c. Half substractor
d. Full substractor
e. 4 bit binary adder
f. 4 to 1 Multiplexer
g. 3 to 8 decoder
h. 5 bit parity generator (even/odd)
i. 4 bit priority encoder
j. Level sensitive Latch
k. Edge sensitive D flipflop
l. 8 to 1 mux using 4-1 mux primitive
m. 1 to 4 demultiplexer
n. Based on given circuit
18. What is the value of a,b,c,d ? (similar other examples)
wire [3:0] u = 4’bx001;
wire [3:0] v = 4’b1x10;
wire [3:0] a = u & v;
wire [3:0] b = u | v;
wire [3:0] c = u ^ v;
wire d = & v;
19. Write an UDP description to toggle flip flop. In Toggle flip flop , if data input is 0 output will not
change, if data input is 1, then every clock edge output toggles. Assume triggering clock edge is
negative. Write its test bench?
20. Model rising edge triggered JK Flip flop as UDP. If both inputs J and K are 0, output doesnot
change. If J =0 and K=1 , then output is zero. If J=1 and K=0 , then output is 1 and when J and K
are 1 then output toggles. Write its test bench also.
21. Differentiate between procedural assignment and continuous assignment?
22. Elaborate various loop statement in Verilog with syntax and example?
23. What is difference between sequential block and parallel block? Explain with example? Does
sequential block appear in parallel block?
24. How blocking assignment are different from non blocking assignment?
25. Generate clock waveform with on period of 5 ns and on period of 10 ns?
26. Express the following statement using initial statement and forever loop?
always @( expected or observed)
if (expected !==observed)
begin
$display(“Mismatch : expected = %b, observed = %b”,expected,observed);
$stop;
end
27. Describe the behaviour of JK flip flop using always statement?
28. Describe the behaviour of majority circuit. The input is 12 bit vector. If the numbers of 1’s
exceed numbers of 0’s, then output is set to 1. Input data is to be checked only when
data_ready is 1 ?
29. Model 4 bit binary counter and write its test bench?
30. Declare register called oscillate . Initialize to 0 and make it toggle after every 30 time unit. Don’t
use always statement?
31. Design 4 to 1 mux using if .. then construct?
32. Using case statement , 8 bit ALU that takes 4 bit input A and B , 3 bit input SELECT and give 5 bit
output Y . ALU implement the following functions based on SELECT input
SELECT Y
000 A
001 A+B
010 A-B
011 A/B
100 A%B
101 A << 1
110 A >> 1
111 A > B (Magnitude comparator)
33. Model various types of FlipFlop and write its test bench?
34. What would be the the output /effect of the following statement?
a. Latch = 4’d12;
$display(“ The current value of Latch = %b \n”, latch);
 b. In_reg = 3’d2;
$moniotor($time,”In register value = %b \n”, In_reg[2:0]);
35. Using wait statement , design level sensitive latch that takes clock and d as a input and q as a
output. Q=d whenever clock =1?
36. Differentiate between Function and Task?
37. Define a Function (or Task) to calculate factorial of 4-bit number , output is 32 bit number?
38. Draw a circuit for XOR gate using nmos and pmos switches? Write a verilog description for the
circuit?
39. Instantiate switches with delay specification. Use ur own input output port names
a. A pmos switch with rise=2 and fall =3
b. An nmos switch with rise=4, fall=6, turn-off=5;
c. A cmos switch with delay=6
d. A tranif1 switch with turn on=5, turn off=6
e. A tranif0 switch with delay =3
40. Describe clock gating concept for synthesis purpose?
41. Elaborate the concept of assertion?
42. Elaborate the concept of Verilog functional coverage?
43. Elaborate the concept of Partitioning for synthesis?