ELE-4613 Assignments

ELE-4613
Programmable Devices

Learning Outcome: 3
Project

Created: Summer 2020

Modified: Fall 2020

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ELE-4613 Assignments

This project aims at building a simple hardware description of a sequential circuit in Verilog
HDL which goal is to produce clock signals for serial communication baud rate generators.

Asynchronous serial communication requires clocks to be generated for being able to recover
the information from the received bits. The requirements are:
 Support multiple baud rates (symbols or bits per second)
 A clock signal of frequency 16 times the baud rate frequency should be generated for
every supported baud rate value.

The supported bit rates are given in the table below. They are all based on the nominal baud
rate of 9600 bits per second
Baud Rate (bits Factor to Nominal Remarks
per second) (Baud Rate / 9600)
9600 1 Nominal
19200 2 2x times
38400 4 4x times
115200 12 12x times

Write a Verilog description of a circuit that generates individual clock signals for everyone of
the supported baud rates. The clock signals should have a 50% duty cycle and a frequency
that is 16 times the corresponding baud rate.

The clock generation circuit should create the output clock signals using the FPGA system
clock that has a different frequency for every board.

The following is a list of frequencies that are possible. Every student group should select a
different frequency.
Group# Supported System Clock
Frequencies
1 110 MHz
2 85 MHz
3 125 MHz
4 156 MHz
5 133 MHz
6 144 MHz
7 129 MHz
8 160 MHz
9 115 MHz

The circuit will have the following interface:

 A system clock input called clk
 A synchronous reset called reset
 A set of outputs called

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o clk96: is the 9600 bps clock signal

o clk192: is the 19200 bps clock signal
o clk384: is the 38400 bps clock signal
o clk1152: is the 115200 bps clock signal

The design style should be based on the use of synchronous frequency division counters
along with simple change detection circuits. The following is an example of one step of the
circuit that uses a system clock of 225 MHz frequency.

The first clock output circuit will generate clk1152. Its frequency is
f 1152=115200 ×16=1,843,200=1.8432 MHz

To generate this clock signal output, a counter is used to divides the system clock by the
following factor:
f system
N= =61.03≈ 61
f 1152 × 2
The factor 2 in the denominator is used to guarantee a 50% duty cycle.
The following diagram is an implementation of the frequency divider. It can be noticed that it
uses a regular 6 bits register (because the value is < 26 = 64) along with a 6-bits adder and a
comparator. The output of the comparator drives the multiplexers of both the input register
and the output flip-flop.

1 mux 0
clk
(225 MHz) mux
6-bits register
0

D Q
1
Comparator

Q
1

Adder
60 clk1152
(1.8432 MHz)

The Verilog description of the circuit is given below. This circuit generates only two out of
the four clock signals

module bdgen(
clk,

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reset,
clk1152,
clk384);

input clk;
input reset;
output reg clk1152;
output reg clk384;

parameter DIV1 = 61;

reg [5:0] cnt1;

always @(posedge clk)

if(reset)
begin
cnt1 <= 0;
clk1152 <= 0;
end
else
if(cnt1 == (DIV1-1)) // output of comparator
begin
cnt1 <= 0;
clk1152 <= ~clk1152;
end
else
cnt1 <= cnt1 + 1;

endmodule

In order to generate the subsequent clock signals, several other counters are created and use
the condition of reset of the first cycle to get incremented (or reset) as shown below in the
portion of code
// Division by 3 to obtain 38400 clock signal
// add this line after reg [5:0] cnt1;
reg [1:0] cnt2;

// add this always block after the always block in the previous code
always @(posedge clk)
if(reset)
begin
cnt2 <= 0;
clk384 <= 0;
end
else
if(cnt1 == (DIV1-1))
begin
if(cnt2 == 2)
begin
cnt2 <= 0;

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ELE-4613 Assignments

clk384 <= ~clk384;

end
else
cnt2 <= cnt2 + 1;
end
In order to simulate and test the circuit, a testbench should be developed. The testbench
needs to:
 instantiate the design and connect its inputs and outputs
 create the input clock with the appropriate frequency
The following is the testbench code
`timescale 100ps/100ps
module tb;

reg clk;
reg rst;
wire clk_out_1152;
wire clk_out_384;

// The clock frequency is 1/225 MHz = 4.44 ns which is

// approximately 44 x 100 ps since 1 ns = 1000 ps

initial
begin
clk = 0;
rst = 0;
#15 rst = 1;
#44 rst = 0;
end

// Clock generation. Use 44/2 to flip the clock polarity

always
#22 clk = ~clk;

// Instantiate the design

bdgen bdgen1 (
.clk (clk),
.reset (rst),
.clk1152 (clk_out_1152),
.clk384 (clk_out_384));

// Simulation should be on for at least two periods of the slowest clock

// clk1152 period is 122 times 4.4 ns = 536.8 ns = 5368 x 100 ps
// clk384 period is 3 times clk1152 period which means its period is
// 536.8 ns x 3 = 1610.4 = 16104 x 100 ps
// so a simulation delay of 40000 should be enough

initial
#20000 $finish;

// To save all the signal transition into wave files

initial

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begin
$dumpfile(“wave.vcd”);
$dumpvars(1);
end
endmodule

In order to design and implement this circuit, follow the steps below:
 Create the interface of the circuit
 Determine the division factor of the first frequency divisor
 Determine how many counters are needed and their respective division factor relative
to the first division factor
 Write the Verilog HDL for the design
 Create a testbench that tests the design

Submissions
The project has two mandatory submissions:
 Project report. This report is a group effort that is due before the end of the semester. It
should contain the link to the edaplayground.com site where your design can be
simulated and checked. The grade for this report is 35% of the grade
 Presentation Slides. A set of Powerpoint slides is to be developed. The presentation aims
at showing a summarized view of the whole project: division factors, design and
testbench with thorough but concise explanations. The grade for the presentation is 10%
 Presentation. An on-campus face-to-face presentation featuring the slides where every
student in the group should participate. The presentation should not exceed 10 minutes
and will be followed by questions to all the students individually. The grade for this item
is 40%.

Report Outline
1. Project specifications: circuit specifications. What does the circuit do and what is the
chosen system clock frequency?
2. Number of frequency division counters and their respective division factors.
3. Design HDL code: describe every block of the code.
4. Describe the functionality of the testbench and its features
5. Show the simulation waveform and comment on the results
6. Discussion and Issues: what went well. Did you face any issues?
7. Appendix:
a. edaplayground link
b. Design HDL code listing
c. Testbench HDL code listing
d. Waveform screen capture

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