Series FPGA UART protocol Basics • Transmitter – Tx • Receiver – Rx • Serial communication • Asynchronous (UART Tx and Rx Basic block diagram works @ same Baud Rate) • Full duplex or Half duplex • Can operate at different baud rates (4800, 9600, 14400, 19200, 38400, 57600, 115200 etc.)
Standard serial data format
UART Specification • Simplified model • Data format – 1 start bit – 1 stop bit – No parity bit – 8 data bits • Composed of 3 modules – Baud Rate Generator – Transmitter – Receiver Baud Rate Generator • Baud Rate - Number of signal changes per second (as per modem terminology). • Bit Rate - Number of bits transmitted per second. • As far as the conductor wire (signal wire transmission) is concerned, the baud rate and bps are the same, and we can use the terms interchangeably. • Basic Idea - Baud Rate Generator module divides the System clock by a divisor (N) to provide standard baud rate clock ( bclk ). • Industry Standard System clock frequencies for UART • 1.8432MHz, 2.4576MHz, 3.072MHz • But, 7 series FPGA source clock frequency 100 MHz. • First , it is reqd. to create a clock divider module to convert 100 MHz (10 ns ) to 1.8432 MHz ~ 1.7857 MHz (560 ns) • Basically , divide the FPGA clock by 27 to get standard UART clock of 1.8432 MHz(approx.) Baud Rate Generator • The divisor N can be calculated using the formula Frequency of System clock (1.8432 Mhz) N = Maximum Baud Rate Frequency 38400 X No.of samples per bit (8)x 2 = 3 ( Duty cycle of clkdiv (divided by 3) 33.33% )
Block diagram of Baud Rate Generator
Baud Rate Generator
Baud Rate (bclk ) = 38400
Different Baud rate and sampling frequencies
Timing Diagram Clk div (dvide by 3), bclk, bclk*8 UART Transmitter • Converts a parallel data word into serial form and appends the Start and stop bits. • Composed of – Transmitted bit counter – Data shift register – State machine and support logic
Block Diagram of transmitter
FSM UART transmitter RTL netlist for Baud Rate Generator and Transmitter
Timing diagram of UART TX
UART Receiver • To avoid setup and hold time problems and reading some bits at the wrong time, the received data is sampled eight times during each bit time – sampled on the rising edge of bclkx8.
Data sampling points by the UART receiver.
• UART Receiver – State machine – De-serializer (SIPO logic) and support logic. • The main objective - – To detect the start-bit, then de-serialize the following bit- stream, detect the stop-bit, and make the data available to the host. • No error checking Logic • 2 counters are used • ct1 counts the number of bclkx8 clocks • ct2 counts the number of bits received after the start The state machine is the Mealy machine and composed of three states (idle, start_detected, and recv_data) STA for UART Tx and Rx • FPGA clock 100Mhz
Half Duplex communication mode!! Standard Protocol features • AXI4-Lite interface for register access and data transfers. • Transmit and receive FIFOs. • Configurable number of data bits (5-8) in a character. • Configurable parity bit (odd or even or none). • Interrupt controller logic.