CDC Signoff using SDC

Ravindra Nibandhe
Rangarajan Govindan
July 2018

© 2018 Synopsys, Inc. 1

 Agenda

Clock Domain Crossing (CDC) analysis methodology overview

CDC analysis with Synopsys Design Constraints (SDC) – challenges and solutions

Running SpyGlass CDC analysis with SDC

© 2018 Synopsys, Inc. 3

 CDC Signoff Methodology
RTL SDC

CDC Analysis
Identify clock domains
CDC
Identify CDC paths Setup
Identify synchronizers
Persistent Interactive
Violation
Database Advanced CDC Checks
Divergence / Re-convergence

Reset Check

CDC Reporting Report

TCL Debug GUI Debug

(Design & CDC query) (violation browser, Schematic)

© 2018 Synopsys, Inc. 4

 Defining CDC Setup

• CDC analysis requires all flops to be receiving clock attributes

• Remove unwanted violations due to converging clocks

• Complete CDC analysis for reset synchronization and Reset Domain Crossing flops with
async reset to receive reset attributes

© 2018 Synopsys, Inc. 5

 Defining CDC Setup
Missing Clock Definitions

Black-
Box

Missing clock definitions!

Reported by rule Clock_info03a

© 2018 Synopsys, Inc. 6

 Why Constrain Clock MUXes?
MUX *not* configured for specific operational mode

• Source of crossing drives a merged domain, ‘domain1,domain2’

• Merged domain will never match destination domain ‘domain1’
domain1
• Will always produce “unsynchronized” violation!

Ac_unsync01 flags unsynchronized

Clock_info05 flags clocks converging on
destination
MUX

Unconstrained clock MUXes prevent CDC closure

Debug Data confirms Source flop

drives merged domain

Debug Data shows clocks propagate

© 2018 Synopsys, Inc. 7 individually to Source flop
 Why Constrain Clock MUXes?
MUX configured for specific operational mode

• Operational mode (scenario) #1 • Operational mode (scenario) #2

– MUX selects ‘clk2’  Ac_unsync01 violation – MUX selects ‘clk1’  no violation

set_case_analysis -name ffsel_reg.Q -value 1 set_case_analysis -name ffsel_reg.Q -value 0

Constrained clock MUXes enable CDC closure

Debug Data confirms Source Debug Data confirms Source domain

domain does *not* match matches destination domain  no
destination domain  crossing
unsynchronized crossing

© 2018 Synopsys, Inc. 8

 Defining CDC Setup
Missing Reset Definitions

A
Y
B

sel=0

Missing reset definitions!

Reported by rule Reset_info09a. Ability to report common reset.

© 2018 Synopsys, Inc. 9

 Defining CDC Setup
Defining quasi static signals

© 2018 Synopsys, Inc. 10

 Agenda

CDC analysis methodology overview

CDC analysis with SDC – challenges and solutions

Running SpyGlass CDC analysis with SDC

© 2018 Synopsys, Inc. 11

 CDC Analysis With SDC Is Very Attractive
Motivations

• Ensures consistency and maintains design intent across tools

– Same SDC for many tools – PrimeTime, Design Compiler and SpyGlass CDC

• Robust use model

– Describes clock relationships easily and flexibly
– Uses rich set of design query commands for streamlined programmatic constraining

• Very familiar across design community

– Represents industry standard
– Uses TCL shell

Ensures reuse of constraints across various stages!

© 2018 Synopsys, Inc. 12

 SDC for CDC has challenges!
Overview

• SDC clock paradigm is different than in SGDC

• SDC missing commands for CDC analysis
– Constraints for resets, quasi-static signals, glitchy and convergent sources, control and data synchronization, etc.
– Constraints for boundary condition attributes – synchronizers, combinational logic, etc.
• SDC contains many commands that are not pertinent to CDC
– Maintaining and using SDC for CDC becomes unnecessarily complex
• SDC often available later in design cycle – fine for subsystem, bad for block-level analysis
• SDC typically written and maintained for gate-level netlists, not RTL

Challenges? Here is the guidance!

© 2018 Synopsys, Inc. 13

 Considerations on using SDC for CDC

SDC Reading

Understanding
Constraints
Clock
Interpretation
Propagation

Name Mapping

© 2018 Synopsys, Inc. 14

 CDC analysis with SDC – challenges and solutions

Understanding Clock Relationship

© 2018 Synopsys, Inc. 15

 Synchronous vs. Asynchronous Paradigms
SDC clocks vs. SGDC clocks

SDC assumes synchronous clocks SGDC assumes asynchronous clocks

• Must define *asynchronous* exceptions • Must define *synchronous* exceptions
set_clock_groups, set_false_path clock -domain
• Two asynchronous clocks … • Two synchronous clocks …
block.sdc block.sgdc
create_clock -name c1 [get_pin c1]
clock -name c1; #assumed domain c1
create_clock -name c2 [get_pin c2]
clock -name c2; #assumed domain c2
…

• … will be mistakenly assumed synchronous • … will be mistakenly assumed asynchronous

without the following command without the following additions
block.sdc block.sgdc
…
clock -name c1 -domain d0
set_clock_groups -async \
clock -name c2 -domain d0
-group c1 -group c2
Ensure that ALL asynchronous clock relationships are
explicitly defined in SDC when used for CDC analysis!
© 2018 Synopsys, Inc. 16
 Understanding Clock Relationship

• set_false_path across clocks will enable the CDC analysis

• set_false_path across flops is not supported

Use set_clock_group –async instead of false paths (Consistent results)

Examine the Clock Matrix to see “synchronous” clocks to make sure nothing is missed

© 2018 Synopsys, Inc. 17

 Understanding Clock Relationship
Logically Exclusive Clocks

© 2018 Synopsys, Inc. 18

 Understanding Clock Relationship

• Be careful of clock_sense since it can cause missed violations

– This constraint will stop a clock from propagating
– It is often used on clock muxes to stop a test clock instead of using
set_case_analysis
– But a PT user could use it to stop other async clocks by accident

CKSGDCInfo.rpt from CDC analysis will list all clock_sense constraints

© 2018 Synopsys, Inc. 19

 CDC analysis with SDC – challenges and solutions

Name Mapping

© 2018 Synopsys, Inc. 20

 Pin Name Mismatch for Inferred Registers
• Register pin names in an SDC constraint are typically given to
match
the associated pin names in the target technology library (.lib file)
• Consider, the clock pin for all flip-flops in the .lib file are known to
be CLK
• SpyGlass, however, has its own set of conventions, including the
clock pin of an inferred RTL register to be “CP”, so that the
following constraint will fail:
set_false_path –from i_gen_clk/CLK

In order for SpyGlass to understand you’ll need to add the

SGDC command mapped_pin_map.
– See the documentation for mapped_pin_map to see all of the pin
names that may be modified.

mapped_pin_map –clock CLK

mapped_pin_map –out q

© 2018 Synopsys, Inc. 21

 SDC Mismatch Violations
• How to determine what SpyGlass thinks instances are called
inside the SDC context
– Sometimes this is different than SGDC context 
– Example: SpyGlass can’t find an object that exists in SDC file
set_false_path –from mid/myregs/q_out[3]/CP

• Debug Steps
– Use Instance Browser of SpyGlass GUI.
– The hierarchy or pin name could be different
– Or Add the following to your SDC file and capture the stdout
– Replace the non-alphanumeric characters with wildcards to more likely
achieve a match.
set myinst [get_cell mid/myregs/q_out*]
sdc_puts “\n\n####### instance names are:\n”
sdc_puts “$myinst\n\n\n########\n\n”

• For faster turn around you can create a goal that only
contains the rule SDCPARSE

© 2018 Synopsys, Inc. 22

 Escaped Names in Verilog

• Names that are escaped by necessity in Verilog (and SpyGlass) should not be escaped in the
SDC

• For example, suppose in instance i1 one has the following instantiation:

mymod \mycell[0] (.A(la), .Z(lz));

• The temptation would be to write the constraint as below with a space after the bracket.
set_false_path –from i1/\mycell[0]{space} /Z

• The correct form is (without using renaming – more on this later)

set_false_path –from i1/mycell[0]/Z

© 2018 Synopsys, Inc. 23

 SytemVerilog vs. V2K Unlabeled Generate Blocks
For generated blocks, such as the below:
generate begin • Labels are pre-pended to the instance name, separated by “.”. Each
if (1) begin : g01 begin/end pair inside is considered a “labeled” block, either implicitly
flop u0 (.d(d[0]), .q(q[0]), .ck(ck)); or explicitly
end • In the example shown here, the outer begin/end pair has an implicit
end label
endgenerate • The 2nd begin/end pair has an explicit label, “g01”

• For Verilog 2K only the explicit label is • For SystemVerilog, an implicit label is produced in
part of the instance name the form “genblk#”. Where # is the number of the
– So the example shown above will have an
generated block in the module.
instance that looks like: g01.u0
• In this case, the generated instance name will be:
genblk1.g01.u0

The “.” is NOT a hierarchy separator. It is part of the instance name.

© 2018 Synopsys, Inc. 24

 bus_naming_style
May be incorrect or missing Defines characters in object name
that distinguish base from index
test.v global.tcl
test.sdc
wire [3:0] mydata; current_design test
reg [3:0] myreg; set bus_naming_style %s_%d test.sdc
always @(posedge ck) current_design
set_false_path test
–from myreg_reg_3/CP
myreg <= mydata; set_false_path –from myreg_reg_3/CP

Enables SpyGlass to successfully

match object names in
subsequent SDC commands
Sometimes specified in separate file  may be
accidentally omitted when reading SDC in SpyGlass

test.sgdc
current_design test
sdc_data –file test.sdc

© 2018 Synopsys, Inc. 25

 change_names Create a Tcl file to be read before SDC file
A more generalized renaming method - Define a name rule that specifies allowed
Create a Tcl characters in object
file to be read names
before SDC file
- Define
- Define a replacement
a name character
rule that specifies for
allowed
Create a resulting
Tcl file
characters in to be read
disallowed
object before
names SDC file
characters
In project file, enable change_names with - - Define
Apply aname
name rulesothat
rule
replacement specifies
SpyGlass
character allowed
will
for match
no (GuideWare default) or supermode Create a Tcldisallowed
characters
object
resulting file
in to
names be
object read before
names
within SDC SDC file
constraints
characters

test.prj global.tcl
read_file test.v current_design test
read_file –type sgdc test.sgdc define_name_rule myrule \
current_methodology\ –allowed {a-z A-Z 0-9 _} \
$SPYGLASS_HOME/GuideWare/latest/block/rtl –replacement_char “%”
_handoff change_names –rules myrule -hierarchy
set_parameter pt supermode

test.sgdc test.sdc
current_design test current_design test
sdc_data –file global.tcl –file test.sdc set_false_path –from myreg_reg%3%/CP

In SGDC file, specify Tcl

change_names file and SDC file
© 2018 Synopsys, Inc. 26
 CDC analysis with SDC – challenges and solutions

Constraints Interpretation

© 2018 Synopsys, Inc. 27

 PrimeTime vs. DC Style Constraints
• Parameter pt

• Certain commands, options, and legal points of application are different depending on whether
one is writing constraints for PrimeTime (STA) vs. Design Compiler (synthesis)
– For e.g.- The change_names command in SDC may only be applied in Design Compiler but not in
PrimeTime

• To accommodate users who wish to have the more strict enforcement of PrimeTime but also
allow the change_names command, yet another mode is available for this parameter:
“supermode” - This will enforce PT strictness yet allows change_names

Parameter pt value Behavior

No DC mode, change_names accepted

Yes PT mode, change_names rejected, strict enforcement of SDC

Supermode PT mode, change_names accepted, strict enforcement of SDC

© 2018 Synopsys, Inc. 28

 Handling Unsupported Design Queries in SDC

• Example of missing DC/PT attribute support in SpyGlass

– Both DC and PT support attribute direction
– Only DC supports attribute name
– SpyGlass only supports attribute direction with pt=yes
– SpyGlass only supports attribute name with pt=no
set div_clk_pin [get_pins -of [get_net clkDividerN2*] -filter "direction == out"]
set_case_analysis 1 [get_pins -of_objects u_myflop -filter "name=~o_*"]

Attribute pt = no pt = yes/supermode
direction Not Supported Supported
name Supported Not Supported

© 2018 Synopsys, Inc. 29

 Agenda

CDC analysis methodology overview

CDC analysis with SDC – challenges and solutions

Running SpyGlass CDC analysis with SDC

© 2018 Synopsys, Inc. 30

 Specifying SDC file(s)
• Specify the SDC file using the SGDC file
current_design test
sdc_data –file test.sdc

• Specifying multiple SDC files

– Do NOT use multiple sdc_data commands, do it all on a single line
– Each sdc_data is run as a separate process so there is no communication or transfer of data/knowledge between
commands
current_design test
sdc_data –file setup.sdc –file case_analysis.sdc –file clocks.sdc –file timing_exceptions.sdc
OR
sdc_data –file setup.sdc case_analysis .sdc clocks.sdc timing_exceptions.sdc

• There can be a top level single SDC file sourcing separate SDC files for setup, clocks, case analysis etc
– Specify the top level SDC file as shown below:
current_design test
sdc_data –file top.sdc

© 2018 Synopsys, Inc. 31

 SDC2SGDC flow with SpyGlass
• Design constraints available in form of SDC or TCL can be used for SpyGlass CDC analysis
• SDC2SGDC helps in reusing the set of constraints available for synthesis or timing analysis

• List of SDC commands useful for CDC analysis:

SDC Command Translated SGDC command

create_clock clock
clock or generated_clock depending on parameters sdc_generated_clocks and
create_generated_clock
enable_generated_clocks.
set_case_analysis set_case_analysis
set_clock_groups Used for inferring domain relation of the clocks.
Only clock to clock false path commands are used for inferring asynchronous domain relation.
set_false_path
All flop to flop false path commands are ignored.
set_clock_sense clock_sense
set_input_delay abstract_port
set_output_delay abstract_port

© 2018 Synopsys, Inc. 32

 Mixing SDC and SGDC

• Since SDC doesn’t contain all the constructs necessary for CDC analysis it becomes
necessary to augment the SDC with SGDC

• This works fine except for creating clocks

• Since clock relationships are defined with the set_clock_group command in SDC, if you create
a NEW clock in SGDC, there is no way to say it is synchronous to any of the existing clocks
– The domain names assigned in the SDC could change based on a change in the SDC file

© 2018 Synopsys, Inc. 33

 Managing Noise from Unused SDC Commands
• To reduce noise around the SDC commands which are not relevant for CDC analysis:
• In a text file, say ‘ignored_sdc_commands.txt’, list the SDC commands to be ignored
set_multicycle_path
set_input_transition
set_clock_transition
set_clock_gating_check
set_ideal_network
set_max_delay
………..
• Syntax: Single SDC command on each line for ignoring during the SDC2SGDC usage
• Specify this text file using necessary parameter between current_methodology and
current_goal commands as shown below:
current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
set_parameter tc_ignored_commands ./ignored_sdc_commands.txt
set_parameter tc_stop_parsing_ignored_commands yes; # To stop parsing of the nested/auxiliary
commands present in the SDC commands which are ignored

© 2018 Synopsys, Inc. 34

 SDC2SGDC Recommended Setup
read_file –type sgdc test.sgdc #SGDC file that contains the sdc_data constraint
set_option sdc2sgdc yes; #Enables sdc2sgdc (Fatal if no SDC is provided)
set_option sdc_generate_cfp yes; #To enable generation of cdc_false_path commands
set_option support_sdc_style_escaped_name yes; #To allow non-escaped names used in SDC
set_option sdc2sgdcfile ./<design-name>.sdc2sgdc.out; #(Optional) specify name of the translated SGDC file

current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
set_parameter sdc_domain_mode sta_compliant; #(Optional) default value. Recommended parameter.
set_parameter pt no; #To allow names of design objects to be changed. This is
helpful to reduce noise present for design objects present
under generate blocks
set_parameter show_all_sdc_violations yes; #To enable reporting of all issues for the SDC
set_parameter tc_ignored_commands ./ignored_sdc_commands.txt
set_parameter tc_stop_parsing_ignored_commands yes; # To stop parsing of the nested/auxiliary commands
present in the SDC commands which are ignored
set_parameter sdc_generated_clocks yes; #To have the generated clock definitions translated to
clock constraint
set_parameter enable_generated_clocks yes; #To have the generated clock definitions translated in
uncommented format

© 2018 Synopsys, Inc. 35

 Summary
Advantages Challenges
• Use same SDC for many tools PT, DC and • Assumes all clocks are synchronous
CDC – Good for Worst case Timing analysis
– Ensures consistency and maintains the design • Built for Sync designs, so commands for
intent CDC are not in language
• Easy to describe clock relationships • Many constructs contained in SDC are not
• Verilog Standard on escaped names is applicable to CDC
relaxed – Makes reading file unnecessarily complex
• Industry Standard so it is very familiar • Can come late in design schedule
• Design Query to help automatically create • Written and updated for Gate level and not
commands can add to productivity (clocks, RTL
configuration registers)

Search Solvnet for: SDC2SGDC - Recommended Setup and Debug Steps

© 2018 Synopsys, Inc. 36

Thank You