CDC Synchronization Best Practices

Power Matters.
TM
CDC Synchronization Best Practice

Meridian CDC Training Part 1
© 2016 Microsemi Corporation. Company Proprietary 1

Outline
 CDC Introduction & Concepts

• Clock domains & metastability
 Synchronization Techniques
• Single-bit CDC solutions
• Multi-bit CDC solutions
– CDC handshake protocols
• Reset synchronizer
 Errors in Synchronization
• Common synchronization errors
• CDC errors seen in our silicon
 CDC Design Guidelines

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 2
Outline


Clock Domains
 What constitutes a clock domain?

• The part of the design that is clocked by the same clock.
• The part of the design that is clocked by multiple clocks all with
constant phase relationships to each other (divided clock).
• In functional CDC verification, clock jitter/clock uncertainty is not
considered.
 What is a clock domain crossing (CDC) path?

• Signals that interface between two clock domains.
• Signals that interface from an asynchronous source to a
synchronous destination.

Metastability
 A signal travelling across asynchronous clock domains may

(eventually will) miss the setup/hold time of the local
sampling flop.
 The sampling flop may enter a metastable state.
• The output is neither „1‟ nor „0‟ temporarily.
local sampling flop
in out clk
D Q
(from different
clock domain) in
clk
out
metastable
 Using this output can result in inconsistencies!

 This situation cannot be avoided!
 The solution is to wait for the output to resolve to a stable
value.
Metastability
 What value does the flop resolve to after becoming

metastable?
• Random! Metastable
state
Metastable
state
OR
Logic 0 Logic 1 Logic 0 Logic 1

state state state state
 In theory, a flop can remain in the metastable state

indefinitely.
• The probability that the flop will still be in the metastable state at
time t decreases exponentially with t (and is non-zero at t = ∞).
 In practice, the flop will resolve itself within some amount of

time.

N-Stage Synchronizer
 Adding a retiming flop gives the dat adat

pmc_sync_flop
_sample
pmc_sync_flop
_retime[0]
sampling flop an extra clock cycle to
resolve to a stable value.
aclk bclk
 What if Q1 still isn’t stable before the pmc_sync_flop
next clock edge? Add another
retiming flop!
aclk
 A general N-stage synchronizer adat

consists of one initial sampling flop,
and N-1 retiming flops. MTBF bclk
calculation for each N-stage
synchronizer is performed to ensure pmc_sync_flop
_sample
enough retiming flops are added.
(TSB MTBF > 10,000 years) pmc_sync_flop
_retime[0]

Mean Time Between Failures
Probability of remaining metastable

 Metastability resolution time is statistical.
• The longer you wait the greater the probability of
having a stable output.
• Retiming flops increase the wait time.
 Mean Time Between Failures (MTBF)
•
Time
Statistical measure of the time between successive failures
of a retiming circuit.
• Dependent on:
 Number of retiming flops
 Clock frequencies
 Data switching factor: ratio of data transitions to clock periods
 Process technology
 For more information on MTBF refer to the
Metastability Calculator Application Note (cad_tl_00264)

Single-bit CDC Problem
 Can N-stage synchronizer dat adat

pmc_sync_flop
_sample
pmc_sync_flop
_retime[0]
solve all your CDC problems?
In the following case, the input async
pulse is too narrow thus it is highly
possible to be missed no matter how aclk bclk
many retiming flops inserted. To fix pmc_sync_flop

this CDC issue, input pulse needs to
be widened. aclk
adat
 More considerations are
needed to safely pass data
from one clock domain to bclk
another async domain. pmc_sync_flop
_sample
pmc_sync_flop
_retime[0]

Outline


Single-bit CDC Solutions (Option 1)
 Solution #1: pmc_sync_flop pmc_sync_flop pmc_sync_flop pmc_sync_flop
(N-stage synchronizer) dat adat _sample _retime[0] _retime[1]
• Most suitable for non-frequently changing

signals where capture by the receiving
clock domain is guaranteed. aclk bclk
pmc_sync_flop
• If destination clock (bclk) frequency ≥
500MHz, RETIMING_FLOP_NUM should
be set to 2 or larger to ensure MTBF aclk
performance.
adat
• “Three edge” requirement: to synchronize a
CDC pulse, the minimum pulse width is
bclk
1.5X the period of the receiving clock
frequency. Meridian Pulse width check can pmc_sync_flop
verify the 1.5X RX clock requirement. _sample
pmc_sync_flop
• can model metastability in simulation to _retime[0]
stress design robustness. pmc_sync_flop

_retime[1]
• Latest is pmc_sync_flop v003
(cad_dd_00973/LW16_48_03_A)

Single-bit CDC Solutions (Option 2)
 Solution #2: Pulse pmxxxx_pmc_sync_flop_pulsew
Transfer Wrapper (Rising Edge Detect) pmxxxx_pmc_ (Toggle-to-Pulse Conversion)

sync_flop
(pmc_sync_flop) pulse_w D
T
level_w
sigin sigout D
pulse_r
• Transfer all single- or multiple- ena launch_clk clk ena
cycle pulses in the source busy_w

1'b0 pmxxxx_pmc_
sync_flop
D
stall_r
domain to single-cycle pulses sigout sigin

level_r
in the destination domain. clk launch_clk

clk_w clk_r
• Robust against different clk_w domain 1'b0 clk_r domain
combinations of fast and slow

clocks in source and clk_w
retiming
destination clock domains. pulse_w
busy_w
• Guarantees no pulse level_w
squelching. CDC CDC
clk_r
• Destination domain can delay retiming
the pulse output using stall_r pulse_r
level_r
stall_r
1 sampling and 2 retiming flops in both pmc_sync_flops

Multi-bit CDC Problems
 Problem #1: skewed bdata
d q
bbus
sampling of the multi-bit value a_load
bq1_load bq2_load
d q d q load
• Never pass multiple CDC bits required in
the same transaction in parallel! pmc_sync_flop
a_en
 Could result in incorrect data d q
bq1_en
d q
bq2_en
en
 e.g: asynchronous bus transition: “00” to

“11” pmc_sync_flop
 could result in following synchronized bclk

transition: “00” to “10” to “01”
aclk
• Small data changing skews can a_load

Small skew between control signals
occasionally be sampled on different

rising clock edges in the destination
a_en
domain. bclk
bq1_load
• Note: Gray coded buses are an bq2_load

“load” but not “enable”
exception to this rule. “missed”

bq1_en
“enable” but no “load”
bq2_en

Multi-bit CDC Scenarios
 There are two scenarios that are possible when passing

multiple signals across CDC boundaries, and it is important
to determine which scenario applies to your design:
1) It is permitted to miss samples that are passed between clock

domains. Example: gray-code counter used in async FIFO.
2) Every signals passed between clock domains must be sampled.

Example: data buses.
In both of these scenarios, the CDC signals will require some form of
synchronization into the receiving clock domain.

Multi-bit CDC Solutions (Option 1)
 Solution #1: Gray-code pmxxxx_pmc_sync_flop_pulsew
Wrapper (pmc_sync_flop)
000 000 000
PMC Sync flop

• Wrapper that support transferring a 001 001 001
Gray encoder
Gray decoder
pipeline flop
gray-encoded bus across clock 010 011 010
011 010 011
domains !
100 110 100
 Gray-encodes the input bus or optionally 101 111 101
accepts an already gray-encoded input 110 101 110
bus. aclk 111 100 111 bclk
 Instantiates multiple pmc_sync_flops for domain domain
transferring the gray-code bus.
 models metastability based on Gray- aclk
encoded bus behavior. gc_in[2]
• Scenario #1: gray-code synchronizer gc_in[1]
does not capture every legal value if gc_in[0]
destination clock frequency is less than
source clock frequency. bclk
• Note: Gray encoding for CDC can only gc_out[2]

be used on buses that are guaranteed gc_out[1]
to only increment or decrement by 1, gc_out[0]
such as counters!
 Solution #2: Load control with Mux recirculation register
mux recirculation register data_A[2]

0
1
data_B[2]
clkB
• A common technique to safely pass

clkA
CDC data bus data_A[1]

0
1
data_B[1]
clkB
 Source data must be held constant clkA
while the control signal (enable) is data_A[0]

0 data_B[0]
asserted.
1
clkB
clkA
 Control signal must be held high (and pmc_sync_flop

rising edge
detect
low) long enough to be synchronized. enable enable_d

enable_sync
clkA clkB
 Clock relationships need to be well
understood as varying the clock rates
could break the design. aclk
• Scenario #2: Every data word enable

passed between clock domains must enable_d
be sampled. To achieve that goal, data_A[2:0] 000 111
extra control logic is needed. bclk
enable_sync
data_B[2:0] 000 111

 An important responsive variation of the load control technique is to
pass the enable signal back to the source clock domain as an
acknowledge signal.
Mux recirculation register
0
data_B[2]
data_A[2] 1
clkB
clkA
0 data_B[1]
data_A[1] 1
clkB
clkA
0
data_B[0]
data_A[0] 1
clkB
clkA
rising edge
pmc_sync_flop detect
enable enable_d
enable_sync
clkA clkB
ack

 Solution #3: Handshaking bus synchronizer
• A handshake protocol can be used to ensure safe datapath synchronization.
 Implements a 2-phase (transition-based) handshake protocol
 Ensures non-overlapping sample and capture signals
 Transmit FSM asserts busy when current transaction is in progress
 Receiver can insert wait states by deasserting ready
sample capture
Transmit FSM pmc_sync_flop Receive FSM

start
(Master) req req_sync (Slave)
busy valid
done clkB
ready
error
pmc_sync_flop
clkA ack_sync ack
clkB
clkA
Timeout
Timer
rstb_A rstb_B
Handshake controller

 Handshake timing
clk_A
start
busy
done
sample
req
ack_sync
clk_B
req_sync
ack
capture
valid
Wait state
ready
A handshake cycle

 Handshaking Bus Handshaking bus synchronizer
Synchronizer
mux recirculation reg mux recirculation reg
 Uses handshaking controller data_in data out
(earlier slides) to generate non- data_in data_out data_in data_out
overlapping pulses. enable enable
 Uses mux recirculation registers

to setup and capture data.
rstb
 Sending and receiving processes rstb_A rstb_B
have control over transfer.

 This design is robust, but has high
latency! Suitable for low- handshake controller
bandwidth channels. sample
start
start capture
busy valid
busy valid
done ready
done ready
error
error
rstb_A rstb_B
rstb_A rstb_B
clk_A clk_B
clk_A clk_B

 Solution #4: Ping-Pong sampling_a retiming_a_0 retiming_a_1 loop_a_b pipeline_a_1 pipeline_a_2
ping
bus synchronizer 0 D Q 0
D
Q 0
D
Q D Q D Q 0
D
Q
1 1 1 1
 Generates Ping and Pong clk_a

which are non-
overlapping, mutually pong
pipeline_b_2 pipeline_b_1 loop_b_a retiming_b_0 sampling_b
exclusive pulses. Q
D 0 Q D Q D Q
D
0
1
Q
D
0
1
1
 The major advantage of clk_b

using the Ping-Pong
circuit is that only one pair
of ping-pong signals per clk_a
clock domain. sample_a

retime_a_0
 The Ping-Pong circuit is retime_a_1
part of the FIFO Controller loop_a_b
CAD component ping
(cad_dd_00980). clk_b
sample_b
retime_b_0
loop_b_a
pong

 Ping-Pong Bus ping-pong synchronizer
Synchronizer
mux recirculation reg mux recirculation reg
 Uses existing ping-pong controller
to generate non-overlapping data_in data_out data_in data_out
data out
pulses in each clock domain.

enable enable
 Uses mux recirculation registers
to setup and capture data. rstb
 Relatively inexpensive compared
to handshaking bus synchronizer rstb_A rstb_B
and async FIFO. valid
 Sending process has no control

over when each transfer starts.
 Receiving process can’t ready
ping-pong controller
backpressure. rstb_A
pong_w pong_r
rstb_B
rstb_w rstb_r
 Suitable for low-bandwidth clk_A
clk_w clk_r
clk_B
channels.

 Solution #5: Asynchronous FIFO
• If you cannot tolerate per-word handshaking latency in the crossing, use an
asynchronous FIFO to buffer the data.
• This solution is the most robust and offers the highest throughput, but also the most
expensive in terms of gates.
– First word out will have some synchronization latency, but subsequent words
emerge from the FIFO on every clock cycle!
• The design reuse FIFO controller provides an audited solution to the problem:
cad_dd_00980.
data_A data_B
enqueue_A dequeue_B
full_A empty_B
Asynchronous FIFO
rstb_A rstb_B
clkA clkB

overflow
min_ slots_free_w
full
read_req
fifo_clrb fifo_clr_ busy
fifo_clrb_w fifo_clr_ busy_r

full_w
WRITE READ
overflow_w
INTERFACE FIFO min_ slots_free_w INTERFACE
CONTROLLER empty_r empty
underflow_r min_ slots_ occupied
min_ slots_ occupied_r underflow
dequeue_r write_ addr_w waddr
write_req enqueue_w raddr
read_addr_r
wceb_w wceb
clk_w dout read_data
rceb_r rceb
clk_r rstb_w rstb_r
RAM BIST
WRAPPER
write_data din
clk wclk clk
rclk
rstb wrstb rrstb rstb
W Clock
R Clock
W Reset
R Reset

Multi-bit CDC Solutions (Summary)
 A quick summary of all listed multi-bit CDC solutions
Multi-bit CDC solution Latency Complexity Robustness
Solution #1 *: Low Low Missed samples may
Multi-bit gray code wrapper occur if fast-to-slow
of pmc_sync_flop (scenario #1)
Solution #2: Medium/High Low Requires extra control

Load control with mux logic on both Tx and Rx
recirculation register side
Solution #3: High Medium High

Handshaking bus
synchronizer
Solution #4 *: Medium/High Low Extra logic may be
Ping-Pong bus synchronizer required to prevent data
underflow/overflow
Solution #5 *: Low High High
Async FIFO
* currently CAD supported solution

Reset Synchronizer
 Reset can also cause scanb
metastability! async_resetb
reset_sync_pmcsync_rstb_plm_inst
0
0
• Asynchronous deassertion of sw_reset 1
1
0
reset can violate setup (“reset scanb_and_sw_reset_plm_inst '1' 1
sync_resetb
recovery time”)
sync_resetb_plm_inst
• “Assert asynchronously, deassert CLK
retiming_ retiming_ retiming_
synchronously.”
pmcsync
flop 1 flop 2 flop 3
 Use a reset block to clk
synchronize your scanb(=1)
asynchronous resets. async_resetb

sw_reset(=0)
• Include pmcsync (Q)
LW16_48_06_A/RESET_SYNC_
retiming_flop1 (Q)
retiming_flop2 (Q)
V3 in your depend.txt. retiming_flop3 (Q)
 See Reset Block v003 sync_resetb
application note (PMC-

2124067) synchronous with clk

Outline


Common Synchronization Errors
 Common user synchronization errors include:
• Sending entire multi-bit data buses to the receiving clock domain via
arrays of N-flop synchronizers
• Implementing combinational logic immediately before a synchronizer
• Failing to ensure stable data in the transmitting clock domain
• Divergent and reconvergent paths in synchronization logic
• Not implementing proper CDC handshaking protocols
• Omitting or forgetting synchronization logic completely

CDC Pitfalls: Convergence
 Convergence in the CDC path can cause intermediate glitches and thus
potentially create functional errors downstream.
convergent path
clkA
dA S dB
dA1
dA1
dA2
dA2
INCORRECT
dA
clkA clkB
clkB
dA S dB
S
dA1
dB
dA2
CORRECT S might sample an ... leading to an

Move logic invalid intermediate unintentional pulse
before flop
value... on dB
clkA clkB

CDC Pitfalls: Divergence
 Risk of functional errors due to propagation delays (CDC path is false
path).
• Example: dB1 and dB2 can assert at different times. What if these control FSMs?
divergent path
dA dA1 S1 dB1 clkA

clkA
Tprop
dA
dA2 S2 dB2
dA1
INCORRECT
dA2 Tprop
clkB
clkB
dA dA1 S1 dB1
dB1
clkA dB2
dB2
Move point of
divergence after
synchronizer
CORRECT
dA 2 missed first clkB edge
clkB

CDC Pitfalls: Divergence
 Another thing that can happen is sampling flop S1 may settle (at
random) to a value different from sampling flop S2.
• Results in inconsistencies! Designer expects signal dB1 to be the same as dB2!
divergent path
clkA
dA dA1 S1 dB1
dA
clkA
Tprop dA1
dA2 S2 dB2
dA2
INCORRECT
clkB
clkB
S1
S2
dA dA1 S1 dB1
dB1
clkA
dB2
dB2
Move point of
divergence after
synchronizer
CORRECT
S 1 settled to new value … causing delayed dB2
clkB
S 2 settled to old value...

CDC Pitfalls: Reconvergence
 Synchronized signals must also not converge. This can create functional
errors from propagation delays or random settling values.
Propagation delay causes unexpected pulse Random settling causes unexpected pulse
clkA clkA
reconvergent path dA1

dA1 Tprop1
dA2
dA2 Tprop2
dA1 S1
Tprop1
dB1
clkB clkB
dB
dB1 S1
dB2 S2
dB2
dA2 S2
Tprop2 dB dB1
dB2
dB
clkA clkB
dA 2 missed first clkB edge
S 1 settled to new value … causing delayed dB2

S 2 settled to old value...
• Exception: Gray-coded buses.

– For example, asynchronous FIFO flag generation logic is reconvergent.
• Reconvergent logic must be carefully crafted and audited. Best to avoid if possible.

Luxor Case Studies
 Problem: input SDC had incorrect clock domain specified in some of the
set_input_delay commands.
 Consequence: Missed CDC paths without proper synchronization (W_DATA).
Therefore it caused some top level debug registers not working properly in Luxor
RevB.
All supported SDC commands in Meridian ENV commands
create_clock create_waveform, create_clock
create_generated_clock create_derived_waveform, create_clock
set_case_analysis set_constant
set_input_delay create_input
set_output_delay create_output
set_false_path Used with create_clock
set_clock_groups Used with create_clock
 Conclusion: Input SDC should be carefully reviewed. Meridian CDC cannot do

anything but assume every command in the input SDC is correct.

Luxor Case Studies
 Problem: Not enough retiming flops in synchronizers on fast-to-fast/slow-to-fast CDC paths.
 Consequence: This issue cannot be found in Meridian structural CDC check. But it can be
found in the MTBF report.
CDC Freq of Source Freq of Destination Num of Flops in Technology Flop MTBF
Name Clock Domain Clock Domain Synchronizer
(MHz) (MHz)
a1 300 300 2 28 ARM 9-track MTBF=1 3.73E+14
a2 300 500 2 28 ARM 9-track MTBF=1 7.05E+01
a3 300 500 3 28 ARM 9-track MTBF=1 1.30E+18
a4 500 500 2 28 ARM 9-track MTBF=1 4.23E+01

a5 500 500 3 28 ARM 9-track MTBF=1 7.80E+17
 Conclusion: Past experience shows if destination clock domain ≥ 500MHz,

RETIMING_FLOP_NUM in pmc_sync_flop should be set to 2 or larger to ensure MTBF
performance.

Luxor Case Studies
 Problem: In RevA, core_clk and ack were mistakenly connected. In RevB, designer tried to use
XCBI build-in synchronizer but specified the input “async clock” as “sync” thus an ECC interrupt bit
was not properly synchronized.
 Consequence: This error was caught by Meridian and reported as W_DATA/W_GLITCH.
However it was waived for no good reason. It caused failures later in firmware tests.
Luxor RevA Luxor RevB
XCBI In RevB, the

ECC_I3 is
pmc_sync_flop mistakenly
ECC_I3 ECC_I3_EVT int_sync bit specified as
core_clk ECC_I3 “sync” in the
input XML
<reg_bit status="show">
<bit_position>3</bit_position>
aclk <bit_type action="int_sync">R/W</bit_type>
<bit_name>ECC_I3</bit_name>
XCBI <bit_attribute type="int_edge">changing</bit_attribute>
<bit_attribute type="clk">aclk</bit_attribute>
<bit_default>0x00</bit_default>
</reg_bit>
aclk and core_clk

were mistakenly
connected in
Luxor RevA
core_clk domain aclk domain
 Conclusion: All CDC warnings/errors should be carefully examined! CDC results may need
cross auditing.

Luxor Case Studies
 Problem: Combinational logic (pulse generator) was directly passed into a synchronizer in the
receiving clock domain. Pulse was originally designed wide enough to be sampled but due to added
buffer delay in the backend flow, the pulse got shrank unexpectedly thus miss-sampled.
 Consequence: This error was flagged as W_GLITCH but it was actually a pulse width issue.
Meridian could not predict this failure as backend info was not available. This caused RAM initialization
failure in Luxor RevB.
Add buffer delay
core_clk
pmc_sync_flop pmc_sync_flop pmc_sync_flop input_tip

xcbi_attri_tip _sample _retime[0] _retime[1]
input_tip input_tip_d
adat
INCORRECT
core_clk aclk adat
pmc_sync_flop
missed edge
aclk
pmc_sync_flop
xcbi_attri_tip pmc_sync_flop pmc_sync_flop pmc_sync_flop _sample
_sample _retime[0] _retime[1]
input_tip input_tip_d
pmc_sync_flop
_retime[0]
CORRECT
pmc_sync_flop
core_clk aclk
_retime[1]
pmc_sync_flop
 Conclusion: A good practice is to always register signals from the TX domain before passing
into the RX domain.
Outline


CDC Design Guidelines
 CDC checks should be run as early as possible.
o Run prior to dry-run and tape-in milestones.
 Input SDC should be tailored for CDC
o Only 7 SDC commands are valid in the Meridian CDC tool (see page 33).
o SDC commands using netlist hierarchical pin names should be properly adjusted to match RTL.
 All CDC errors and warnings reported in the Meridian CDC tool must be
carefully examined. Waivers must be properly documented.
o In case of design reuse, CDC waivers should not be directly reused if the design has any
functional changes (e.g. clock frequency or clock domain changes).
 All asynchronous signals must be synchronized

o Exceptions can be made when:
• signal must be set up once at startup and then never changes (a “quasi-static signal”)
• i.e. configuration registers
• control signal is synchronized and used to indicate when it is safe to sample unsynchronized
data
o Exceptions must be documented in the datasheet
CDC Design Guidelines
 All asynchronous signals should be registered before passing into the
receiving clock domain.
 MTBF analysis must be performed as early as possible in the design
stage to ensure enough retiming flops are used to meet the MTBF
requirement.
• A conservative target of MTBF>10,000 years per TSB has been established to eliminate the
need to consider MTBF in the chip level Soft Error Rate calculation; see CAD_PREP 14107
 For designs that contain synchronizers that are not pmc_sync_flop

synchronizers, run the mtbf_optimize_flops synthesis procedure.
• CAD Synopsys Tcl Procedure Set (cad_dd_00430)
 Use gate-level muxes (pmc_logic_mux) to reduce CDC glitch issues.
• Use where muxes are present in the CDC crossing path (ie. mux recirculation paths).
• Include LW16_48_07_A/PMC_MACROS_V2 in your depend.txt.
• See pmc_mux v002 application note (PMC-2124124).

References
 Sync Flop Home Page (cad_dd_00569)

• PMC Sync Flop v003 (LW16_48_03_A / PMC_SYNC_FLOP_V3)
– See Application Note PMC-2122592 and IP Release Notes
 Reset Block Home Page (cad_dd_00744)
• Reset Block v003 (LW16_48_06_A/RESET_SYNC_V3)
 PMC Mux v002 (cad_dd_00986)
• Part of PMC Macros v002 (LW16_48_07_A/PMC_MACROS_V2)
 FIFO Controller Home Page (cad_dd_00389)

References
 Meridian CDC Home Page (cad_dd_00952 cad_dd_01036)

 Philips Semiconductors: A Metastability Primer Application
Note
 Metastability Calculator App Note (cad_tl_00264)
 TSB Training: CDC Synchronization (cad_dd_00851)
 Guidelines for SER Control of Memories (cad_mem_00022)
 Clifford E. Cummings, “Clock domain crossing design and
Verification techniques using System Verilog”, SNUG 2008
 Clifford E. Cummings, “Synthesis and Scripting techniques
for Designing Multi- Asynchronous clock designs”, SNUG
2001.

Rev DATE Initials Description
===================================================================================================================
1 2016-03-21 HC Initial creation based on TSB CDC training.
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CDC Synchronization Best Practices

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CDC Synchronization Best Practices

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Power Matters.

CDC Synchronization Best Practice

© 2016 Microsemi Corporation. Company Proprietary 1

 CDC Introduction & Concepts

 CDC Design Guidelines

 CDC Introduction & Concepts

 CDC Design Guidelines

 What constitutes a clock domain?

 What is a clock domain crossing (CDC) path?

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 4

 A signal travelling across asynchronous clock domains may

 Using this output can result in inconsistencies!

 What value does the flop resolve to after becoming

Logic 0 Logic 1 Logic 0 Logic 1

 In theory, a flop can remain in the metastable state

 In practice, the flop will resolve itself within some amount of

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 6

 Adding a retiming flop gives the dat adat

 A general N-stage synchronizer adat

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Probability of remaining metastable

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 8

 Can N-stage synchronizer dat adat

many retiming flops inserted. To fix pmc_sync_flop

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 9

 CDC Introduction & Concepts

 CDC Design Guidelines

• Most suitable for non-frequently changing

verify the 1.5X RX clock requirement. _sample

stress design robustness. pmc_sync_flop

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 11

Transfer Wrapper (Rising Edge Detect) pmxxxx_pmc_ (Toggle-to-Pulse Conversion)

• Transfer all single- or multiple- ena launch_clk clk ena

cycle pulses in the source busy_w

domain to single-cycle pulses sigout sigin

in the destination domain. clk launch_clk

combinations of fast and slow

destination clock domains. pulse_w

1 sampling and 2 retiming flops in both pmc_sync_flops

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 12

 e.g: asynchronous bus transition: “00” to

 could result in following synchronized bclk

• Small data changing skews can a_load

occasionally be sampled on different

• Note: Gray coded buses are an bq2_load

exception to this rule. “missed”

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 There are two scenarios that are possible when passing

1) It is permitted to miss samples that are passed between clock

2) Every signals passed between clock domains must be sampled.

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 14

PMC Sync flop

• Note: Gray encoding for CDC can only gc_out[2]

mux recirculation register data_A[2]

• A common technique to safely pass

CDC data bus data_A[1]

while the control signal (enable) is data_A[0]

 Control signal must be held high (and pmc_sync_flop

low) long enough to be synchronized. enable enable_d

• Scenario #2: Every data word enable

data_B[2:0] 000 111

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 16

© 2016 Microsemi Corporation. Company Proprietary Power Matters.TM 17