Power Electronics Tutorial

Substep
Tutorial
Substep Tutorial
Table of Contents
1 INTRODUCTION ......................................................................................................................................... 3
2 SUBSTEP SIMULATION BASICS .................................................................................................................. 4
3 DIFFERENCE BETWEEN SUBSTEP AND SMALL TIME-STEP......................................................................... 7
4 SIMPLE VOLTAGE RECTIFIER .................................................................................................................... 10
4.1 SUBSTEP HIERARCHY BLOCK ........................................................................................................... 10
4.2 VOLTAGE RECTIFIER CIRCUIT........................................................................................................... 11
5 SIMPLE STATCOM .................................................................................................................................... 16
5.1 STATCOM CIRCUIT ........................................................................................................................... 16
5.2 LOAD ................................................................................................................................................ 19
5.3 TRANSFORMER ................................................................................................................................ 20
5.4 FILTER .............................................................................................................................................. 21
5.5 TWO-LEVEL STATCOM CONVERTER, AC REACTORS, AND DC BUS.................................................. 23
5.6 STATCOM CONTROLS ...................................................................................................................... 25
5.7 BASE VALUES ................................................................................................................................... 29
5.8 DC LINK VOLTAGE CONTROL ........................................................................................................... 30
5.9 PLL, ABC-DQ TRANSFORM, AND FILTERS ........................................................................................ 31
5.10 PLL CONTROLS ................................................................................................................................. 32
5.11 ABC-DQ TRANSFORM CONTROLS.................................................................................................... 33
5.12 PCC AC VOLTAGE CONTROL ............................................................................................................ 33
5.13 Q CONTROL ..................................................................................................................................... 34
5.14 DQ DECOUPLED CURRENT CONTROL .............................................................................................. 36
5.15 MODULATION WAVEFORMS, CARRIER AND FIRING PULSE GENERATOR ....................................... 40
5.16 REFERENCE WAVEFORMS ............................................................................................................... 41
5.17 CARRIER WAVEFORMS .................................................................................................................... 41
5.18 FIRING PULSE GENERATION ............................................................................................................ 42
5.19 HIGH RESOLUTION SCOPE ............................................................................................................... 44
5.20 SUBSTEP HIERARCHY BOX PARAMETERS ........................................................................................ 44
5.21 RUNTIME ......................................................................................................................................... 45
6 SIMPLE PWM TUTORIAL - SUBSTEP ........................................................................................................ 49
6.1 OVERVIEW ....................................................................................................................................... 49
6.2 STEP #1 ............................................................................................................................................ 49
6.3 STEP #2 ............................................................................................................................................ 52
6.4 STEP #3 ............................................................................................................................................ 57
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Substep Tutorial
6.5 STEP #4 (OPTIONAL) ........................................................................................................................ 58

7 INTERFACING MAINSTEP AND SUBSTEP ENVIRONMENTS...................................................................... 60
7.1 INTERFACE TRANSFORMER ............................................................................................................. 63
8 CONNECTING SUBSTEP BOXES USING SUBSTEP TRANSMISSION LINES ................................................. 65
9 SUBSTEP I/O ............................................................................................................................................ 67
9.1 OVERVIEW OF STEPS TO FOLLOW WHEN USING I/O: ..................................................................... 68
10 REFERENCES ........................................................................................................................................ 71
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Substep Tutorial
1 INTRODUCTION
The substep simulation environment is used for the modelling of power electronic (PE)
circuits with time-steps in the microsecond range that can accurately capture the circuit’s
high frequency dynamics. Various VSC converter topologies for FACTS or HVDC applications
are available in the substep environment such as the 2-level, 3-level, and modular multi-level
converter (MMC) converter topologies. Converter topologies such as Buck and Boost are
also available that can be used for motor drive applications. The significant increase in
computing power provided by the introduction of NovaCor allowed for modeling of these
power electronic converters using two-state resistors. Individual switches modelled using
the LC switch model is supported for unique converter topologies in substep. The user can
select the time-step as an integer fraction of the mainstep. The time-step can be as low as
~500 nanoseconds for basic circuits.
The purpose of this tutorial manual is to provide information to the user of the capabilities
of substep. This tutorial is broken up into several parts. In section 2, the basic theory behind
substep simulation and features of the substep environment are provided. In section 3, the
substep environment is compared with the original small time-step environment. Next,
some of the details involved in building a substep case are shown; this is done primarily by
means of example. Section 4 shows the procedure for building a simple voltage rectifier. A
simple STATCOM is assembled in Section 5. The aim of those sections is to assist the reader
in assembling a working simulation case. Section 7 details how to interface a substep
simulation circuit with a mainstep circuit. Section 7 will explain how to interface multiple
substep environments to simulate a larger PE network. The final section, Section 9, deals
with sending and receiving digital and analog signals into and out of the simulation for testing
of external equipment with the real time simulator.
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Substep Tutorial
2 SUBSTEP SIMULATION BASICS

In Electromagnetic Transient (EMT) type simulations, a network solution algorithm is
performed each time-step to compute all the node voltages and branch currents of the
power system. The computation time for solving the network solution places a limit on the
number of nodes that can be computed in each time-step in real time. In particular, the time
it takes to decompose the Nodal Admittance Matrix (NAM) becomes exponentially longer as
the number of nodes increases. The maximum node limit is 60 nodes per substep
environment. The substep time-step is user defined as an integer fraction of the mainstep.
This time-step is typically a couple of microseconds but can go as low as 500ns if the circuit
is very simple.
The solution process performed in the substep is outlined below. This is a similar solution
process to what is used in the mainstep.
1. Convert the power system to an equivalent network of only current sources and
resistors. This is accomplished using the Dommel algorithm and trapezoidal rule of
integration which converts the differential equations of each power system
component to a linear equation in the form: 𝑖(𝑡) = 𝑔 ∙ 𝑣(𝑡) + 𝐼𝐻 (𝑡), where 𝑖(𝑡) is
current through the power system component, 𝑔 is the conductance, 𝑣(𝑡) is the
voltage across the component, and 𝐼𝐻 (𝑡) is the ‘History’ current which represents
all the terms in the equation which are a function of the previous time-step. It can
be seen that each power system element can be represented as a current source
in shunt with a resistor, as shown in Figure 2.1.
Figure 2.1: Current Source Parallel to a Resistor
2. Formulate the conductance matrix [𝐺] for the equivalent network, as shown in
Figure 2.2.
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Figure 2.2: Equivalent Power System Network
3. Using data from previous time-steps (or initial conditions for first time-step),
compute new current injection matrix values [𝐼].
4. Solve for the node voltages using the equation: [𝑉] = [𝐺]−1 [𝐼].
5. With the node voltages and current injections determined, solve for the branch
currents.
The network solution algorithm solves the network equations to get a new set of node
voltages and currents at each time-step. Please refer to Chapter 1 of the power system
manual for further details on the general solution process. Note: the substep and mainstep
computations are slightly different and substep has been optimized to run at a smaller time-
step.
Due to the full decomposition of the network solution each time-step, the switching
elements of the circuit can be modelled as resistors. Resistive switching allows efficient
modeling of power electronics circuits and helps to study higher frequency electromagnetic
transient phenomena accurately. A large resistance, Roff, is used to represent an open switch;
whereas, a small resistance, Ron, is used to model a closed switch. The two resistances must
be significantly different from each other such that Roff >> Ron.
(a)Switch OFF (b)Switch ON

Figure 2.3: Resistive Switch Model
The substep simulation environment is intended to execute at a fraction of the mainstep and
to be used to model power electronics circuits. In each substep the computational
architecture starts with the network solution followed by control and power system
components. The process is repeated multiple times within each mainstep, as shown in
Figure 2.4. Results are passed to the mainstep network once every mainstep.
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Figure 2.4: Substep Architecture
The substep has a dedicated library where its components have been optimized to run at
smaller time-steps. The substep library will continue to grow as time passes. The
components available from the substep library can support many different applications such
as HVDC, FACTS, renewables, microgrids, and motor drives to name a few. Additionally,
power system and control components from the mainstep library (excluding GTNET) can also
be used in substep which increases the availability of supported components. However,
mainstep components were not written for a smaller time-step; as many components
contain complex computations that are likely not optimal to use within the substep
environment. The user should expect that using mainstep components will increase the
minimum time-steps that can be achieved. It would be up to the user to determine if the
results from using the mainstep components are suitable.
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3 DIFFERENCE BETWEEN SUBSTEP AND SMALL TIME-STEP

This section will cover the main differences between substep and the previous generation
small time-step environment. This section will particularly focus on the difference between
how the switches are modelled between the two environments.
The small time-step environment [1] has been available since 2005 for modelling high
frequency PE systems with a time-step in the range of 1.4-3.75 usec. The network equation
for EMT simulations, shown in Equation 3.1, in is solved every single time-step.
[𝑉] = [𝐺]−1 [𝐼] Equation 3.1
where [𝑉] is the node voltages, [𝐺]−1is the conductance matrix, and [𝐼] is the current
injection matrix.
The time required for re-factorization of a power electronic circuit’s conductance matrix is
not practical in the small time-step environment. The technique used to achieve such a small
time-step for real time applications is to maintain a constant admittance matrix, thereby
eliminating any time required to decompose the admittance matrix each time-step. This is
possible by using an LC switching method which models the ON state of the switch as a small
inductor and the OFF state of the switch as small capacitor. The benefit of this method is the
Dommel conductance of the inductor, gsc, and capacitor, goc, can be forced to the same
value (gsc=goc) which means changing the state of the switch does not change the
admittance matrix, and only changes the current injection matrix.
(a) Closed Switch (b) Open Switch

Figure 3.1: LC Switch Model
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Despite the advantage of enabling small time-steps in real time, there are some drawbacks
that must be considered. It is well known that the LC switching method can cause higher
than expected converter losses due to artificial switching losses associated with abruptly
switching from a small inductor (switch ON) to a small capacitor (switch OFF) model. In
addition, the switching method introduces additional inductance and capacitance that
would not exist in the real circuit and may introduce current and voltage oscillation that
would appear as noise. It can also be unclear to the user on how to configure the parameters
of the switch. While the user does not have to specify the value for L and C, they are required
to provide the base current, voltage, and a dynamic factor, which can still lead to confusion.
The impedance of the switch will also be frequency dependent, which will limit its
operational bandwidth. Detailed information on LC switch modelling in the small time-step
environment can be found in section 2 of the small time-step tutorial manual.
To address some of these issues in the small time-step, an alternative way to model the
switches was required. Interface travelling wave t-line techniques are employed to decouple
the switching components from the rest of the small time-step solver in order to support
resistive switching. For example, a 2-level converter which consists of five nodes (three at
AC terminals and two at DC terminals) can be decoupled from the rest of the small time-step
network. By using a t-line for decoupling a small network of switches, the switching devices
can be modelled as two-state resistors where 𝑅𝑂𝑁 ≪ 𝑅𝑂𝐹𝐹 . Due to the smaller network size,
the conductance matrix re-factorization for all possible switching states are pre-calculated
and stored before the simulation case is run meaning that re-factorization of the
conductance matrix does not need to be computed each time-step. Resistive switches
provide more accurate losses and cleaner results. However, this method can only be used
for a reduced number of switches as there is limited memory to store all the pre-calculated
matrices. A 3-phase 3-level topology cannot use this technique as there will be too many
matrices to pre-calculate and store. The drawback of this technique is the inclusion of an
interface t-line that would not exist in the real system. A t-line will add additional series
inductance and shunt capacitance in the system which can add noise and oscillation. This
can be minimized by proper selection of parameter and by absorbing any existing line
inductance or shunt capacitance into the transmission line parameters. The transmission line
parameters are specified within the t-line decoupled component. The small time-step
environment has been successfully used by RTDS users since it was introduced and is one of
the most used features of the RTDS simulator.
The introduction of RTDS ® NovaCor platform in 2017 provides a significant increase in

computing power compared to the previous generation of hardware. This has led to the
development of several new features and applications for the RTDS platform. One such
feature is the substep simulation network. The key feature of substep is that the substep
network solver will perform matrix re-factorization of the conductance matrix for each
substep time-step when solving the network equation. This means that the admittance
matrix can be modified during the simulation and therefore changing conductance values
are permitted. As a result, switching circuits can be modelled with pure resistive switches.
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By using pure resistive switching, higher switching frequencies are supported, lower losses
and cleaner waveforms will be seen compared to the small time-step environment. It is also
easier to configure the converters, as the user is required to provide the ON and OFF
resistance of each switch. The substep time-step is selected by the user from within the
substep hierarchy box parameters.
In addition to the improved switch model in substep compared with small time-step, there
are several other benefits to using the substep environment compared with the small time-
step environment. A summary of the features and limitations between small time-step and
substep are outlined in Table 1.
Table 1: Comparison Between Small Time-Step And Substep

Small Time-step Substep
Hardware Available GPC, PB5, NovaCor Available for NovaCor only
Processor
• One or two small time-step boxes on • One full core
Assignment
one core
• Only supported on NovaCor
• One small time-step box on one to two
PB5/GPC processors
Node Limit Node limit = 30 (PB5/GPC) Node Limit = 60

Node limit = 45 (NovaCor)
Timestep Small time-step range: Substep range:
1.4 – 3.75µs no minimum – 10us
Range if LC switching included:
no minimum – 3.75us
Time-step is user selectable. Time-step is user selectable
Time-step is adjusted by RSCAD based on Substep time-step = 1/N * main time-step,
requested time-step by user where 5≤N≤64
Switch Model RLC Switching Resistive switching (without artificial

Resistive switching with artificial interface tlines interface tlines)
for two level converter and MMC models RLC switch models supported (only used
for individual switches/custom topologies)
Solution process Constant conductance matrix with up to 10 Full decomposition of Network Solution.
resistive branches supported, where the matrices No resistive switch limit
are pre-calculated
I/O See Small time-step tutorial for instructions. Mainstep I/O components used.
GTNET not supported GTNET not supported
Components Only small time-step components Substep, Controls, Power system
components
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4 SIMPLE VOLTAGE RECTIFIER

In this section a simple voltage rectifier will be assembled and simulated using the substep
feature of the RTDS Simulator. The topology of the circuit will be similar to that shown in
Figure 4.1. Since switching will only occur at power system frequency this is not an example
of the type of circuit that would typically need to be studied using substep simulations, but
the construction of this circuit is instructive nevertheless and serves as a good starting point.
Figure 4.1: Simple Voltage Rectifier Circuit To Be Assembled
4.1 SUBSTEP HIERARCHY BLOCK
In order to build a circuit simulated in substep, a substep hierarchy box, shown in Figure 4.2,
must be placed into the DRAFT case. Any circuit which is to be simulated using a substep
time-step must be assembled inside this substep hierarchy box. The Master library contains
a tab labelled Substep which contains a collection of substep models. The substep hierarchy
component is available from the substep library; however, any hierarchy box (from power
system library, substep library or superstep library) is configured to operate as a substep
hierarchy box when the Type parameter is set to SUBSTEP from the parameter window, as
shown in Figure 4.3 (a). The components in the substep library have been optimized for the
substep environment, however, the substep environment is not restricted to only substep
components. Substep, power system, and control components can all be placed inside the
substep environment keeping in mind that more complex power system/control
components will require a larger substep time-step. All components placed in the substep
environment are computed at the substep time-step which is an integer fraction of the
mainstep. This time-step fraction is specified by the user within the substep hierarchy box
parameters as shown in Figure 4.3 (b). The user also has the option to specify whether the
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contents of the substep environment are power system or only controls as shown in Figure
4.3 (b). To edit the hierarchy box parameters, right click on the box and select Edit
→Parameters, or alternatively simply hit E on your keyboard while keeping the curser over
the hierarchy box. The help documentation for the substep feature is available through right
clicking on the substep box and selecting Help.
Figure 4.2: Substep Hierarchy Box
(a) Substep Box Parameters
(b) Substep Options Parameters

Figure 4.3: Hierarchy Box Parameters For Substep
4.2 VOLTAGE RECTIFIER CIRCUIT
Inside the substep environment the circuit of Figure 4.4 should be constructed. The two level
voltage rectifier consists of an IGBT bridge with anti-parallel diodes. If firing pulses for the
IGBTs are not provided, then the IGBT bridge effectively becomes a diode bridge. The load
on the DC bus will be a 100Ω resistance and the source impedance will be a 1Ω resistance.
The two level bridge component, named rtds_ss_LEV2_V3, can be found in the substep
library in the ‘Resistive-Switching Converters’ box.
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Figure 4.4: Simple Voltage Rectifier Circuit To Be Assembled
As previously mentioned, components from both the substep and mainstep library are
supported within a substep hierarchy block. To optimize the time-step, it is recommended
to use substep components. Table 2 shows where each of the components in this circuit can
be found.
Table 2: Component Selection For Simple Voltage Rectifier Circuit

Component Library Component Name
Three phase Source Substep rtds_ss_BRC3.def
2 level converter Substep → Resistive rtds_ss_LEV2_V3
Switching Converters
Resistive load Substep rtds_ss_BRC3.def
Three Phase Node voltage label Power system rtds_sharc_sld_BUSLABEL
DC side voltage label Substep rtds_sharc_node
Table 2 shows that the same component, rtds_ss_BRC3.def, is used for both the three phase
source and the resistive load. This branch component is highly customizable through its
parameters as shown in Figure 4.5 (a). It can be used to model R, L, C, RL, RC, RRL and high
pass filter branches. The number of branches per component can be varied between one
and three and they can be positioned either inline or in parallel. It is also possible to include
a controlled voltage source in the branch by setting the vsrc parameter to Yes. The shape
and magnitude of the voltages follow that of the control signals referenced under the
NAMES FOR REAL VOLTAGE SOURCE INPUTS tab as shown in Figure 4.5 (b).
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(a) Substep 3 Branch Model Parameters (b) Names for real voltage source inputs
Figure 4.5: Branch Component Parameters
The AC voltage references (VSRCA, VSRCB, VSRCC), for the controlled voltage source shown
in Figure 4.5 (b), are generated using the control logic shown in Figure 4.6. The source
magnitude is 11.5 kV LL rms.
Figure 4.6: Control Circuit for the 3 Phase Sine Wave
In order to model a diode rectifier, no firing pulses are provided to the IGBTs of the two level
converter bridge. The firing control word is specified in the VALVE FIRING PULSES INPUT
NAMES parameters as shown in Figure 4.7. The Figure shows that phase A, B, and C are being
controlled by the same firing control word where bits 1 and 2 control valve 1 and 2 in phase
A, bits 3 and 4 control valve 3 and 4 in phase B, and bits 5 and 6 control valve 5 and 6 in
phase C. The FPWORD signal is set to zero by using a wire label and an integer constant as
shown in Figure 4.8.
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Figure 4.7: Valve Firing Pulses Input Names In 2 Level Bridge Parameters
Figure 4.8: Firing Pulse Input Control Signal
The two level converter, rtds_ss_LEV2_V3.def, includes AC side reactors and DC side
capacitance. In this tutorial, set the inductance and capacitance to their minimum value to
minimize their effect on the circuit.
The DC link voltage can be computed using the control logic shown in Figure 4.9.
Figure 4.9: Controls To Compute DC Voltage
Once the case has been successfully compiled, RUNTIME can be launched and the DC and
AC side voltage signals can be plotted. Figure 4.10 shows plots of the results that should be
obtained. The signal VP, as expected, is the maximum value of the signals VA, VB and VC;
conversely the signal VN is the minimum amongst them. The DC link voltage is VP – VN as
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Figure 4.10: Runtime Results. From Top To Bottom: (ii) Voltages At Terminals Of Converter,
(ii) DC Positive Rail And Negative Rail Voltages, And (iii) DC Link Voltage
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5 SIMPLE STATCOM
The substep capabilities of the RTDS Simulator are often used to model high frequency
switching circuits such as those used in PWM schemes. In this next section the foundations
established in the previous section are built upon and a simple STATCOM will be assembled.
A STATCOM controls the flow of reactive power into a bus and can thus be used to regulate
the voltage at that bus. Figure 5.1 shows the topology of the circuit that will be constructed;
it consists of an AC source feeding a load that can be switched in or out of service by
controlling a breaker. The system side is 93kV while the voltage on the converter side of the
transformer is 11.5kV. The base power for the system is 100 MVA. A significant drop in the
voltage at the load bus will occur when the load is connected; the purpose of the STATCOM
is to correct this voltage drop.
Figure 5.1: Topology of the STATCOM Circuit
5.1 STATCOM CIRCUIT
The entire STATCOM circuit, shown in Figure 5.1, is built inside the substep environment, as
shown in Figure 5.2. The system in 93kV on the high voltage side and 11.5kV on the low
voltage side; the base MVA is 100. It is important that the power electronic STATCOM
converter is placed within the substep environment to capture all the high frequency
dynamics.
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Figure 5.2: STATCOM Circuit Built In Substep
As previously mentioned, components from both the substep, mainstep, and controls library
are supported within a substep environment. As a result, there are many different ways
components can be selected to create the same case. To optimize the time-step, it is
recommended to use substep components. Table 3 shows where each of the components
in this circuit can be found.
Table 3: Component Selection For Simple STATCOM

Three phase Source Substep rtds_ss_BRC3
Three phase breaker Power System → Faults & Breaker lf_rtds_sharc_sld_BREAKER
Models
Load Substep lf_rtds_sharc_sld_SHUNTRLC
transformer Substep → Substep Transformers rtds_ss_TRFS1PH
HP filter Substep lf_rtds_sharc_sld_SHUNTHP
2 level converter Substep → Resistive Switching rtds_ss_LEV2_V3
Converters
Node voltage label Substep rtds_sharc_node
Further details of the circuit are provided below.
Source:
The three phase AC source has a rated voltage of 93kV LL RMS, and a source impedance of
0.019 + j0.064 pu (Rs = 1.64Ω and Ls = 0.0147H at a nominal frequency of 60Hz). There are
several ways the three phase AC source can be modelled in the substep environment. The
power system library component for the three phase source can be used in the substep
environment, as shown in Figure 5.3 (a). However, an optimized substep controlled voltage
source component is available as shown in Figure 5.3 (b). This component is computationally
less heavy compared to the power system library source model.
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(a) Power system library source model (b) Substep library controlled voltage
source
Figure 5.3: Source Models
The controlled voltage source, shown in Figure 5.3(b), will be used in this tutorial. This
component requires control signals to set the voltage. These controls can be created using
components from the controls library, as shown in Figure 4.6 of the simple rectifier circuit in
section 4. In this section, a new component is introduced, shown in Figure 5.4, which can
also be used to set the voltages of the controlled voltage source in the substep branch
component.
Figure 5.4: Substep Signal Wave Repeater
This component requires controls from the mainstep environment, as shown in Figure 5.5.
These control components can be found in the controls library.
Figure 5.5: Control Inputs For Substep Signal Wave Repeater Located In Mainstep Environment
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Table 4: Control Components For Signal Wave Repeater Inputs

Constants Controls Library rtds_sharc_ctl_CONSTANT
Ramp Controls Library →Signal Generators rtds_sharc_ctl_ARAMP
Rad to sin, Controls Library →Math Functions rtds_sharc_ctl_SINCOS
cos
Gain Controls Library →Math Functions rtds_sharc_ctl_GAIN
Multiplier Controls Library →Math Functions rtds_sharc_clt_MUL
Within the source parameters, under the Substep 3 Branch Model tab, set the branch type
to RL, enable the voltage source, and set the number of parallel branches to 3, as shown in
Figure 5.6. Within the RLC PARAMETERS, set: R=1.64Ω and L=0.0147H. Choose to monitor
the branch currents from within the ENABLE MONITORING tab, and set the SIGNAL NAMES
to Isa, Isb, and Isc for the phase A, B, and C currents respectively.
Figure 5.6: Source Parameters
5.2 LOAD
The Y-connected load is 120 MVA with a power factor of 0.9322 (R = 67.25 Ω and L=0.06925H
at a nominal frequency of 60Hz).
The load can be switched in and out of the circuit using the three phase circuit breaker
component. Within the breaker parameters, set the parameter ‘Asig’, which is the signal
name to control the breaker, to “BrkLOAD” for all three phases. Set the parameter ‘Abit’,
which is the active bit number in Asig to control the breaker, equal to 1 for all three phases,
as shown in Figure 5.7. The breaker closed resistance is set to 0.001.
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Figure 5.7: Breaker Parameters
A switch to control the breaker in Runtime should be created, as shown in Figure 5.8.
Figure 5.8: Breaker Switch
When the load is switched in, the voltage at Bus 2 is expected to dip and it is this dip that
the STATCOM should regulate.
5.3 TRANSFORMER
A transformer is typically used to connect the STATCOM and the filters to the bus where
voltage regulation is needed. The impedance is selected as purely reactive and is Xleak = 0.18
pu. The transformer is an ideal transformer. The following parameters should be set from
within the transformer parameters.
In the CONFIGURATION tab, set the number of single phase units to 3 to create three single-
phase transformers.
Set the transformer electrical parameters based on Figure 5.9.
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Figure 5.9: Transformer Electrical Parameters
5.4 FILTER
In this tutorial, a PWM scheme is used where switching occurs at a frequency of 5000 Hz.
Current and voltage harmonics will be generated in the vicinity of this switching frequency
and the shunt filter branch will behave as an effective short circuit at these harmonic
frequencies and effectively ground Bus 2 to minimize their impact on the network. The value
for the parameters of the filter are Rshunt = 0.15915Ω, Cshunt = 200uF and Lshunt = 5.066e-6H.
These parameter choices lead to the bode plot of Figure 5.10 for the impedance of the shunt
branch. The input impedance of the shunt branch is 0.1125Ω at 5kHz which is small relative
to the impedance offered by the transformer and reactor at that frequency. At the nominal
frequency of 60Hz the input impedance provided by the shunt filter branch is fairly large and
has a value of 13.261 Ω, approximately 10x the base impedance. This implies that the filter
will have a minimal impact on the circuit at the nominal frequency.
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Figure 5.10: Bode Plot Of The Magnitude Of The Shunt Branch Impedance
The design rules listed below were used to select the parameters of the shunt high-pass filter
branches.
a. Select the capacitor so that at the nominal frequency of 60Hz, the shunt filter branch
behaves like an open circuit. The impedance of the capacitor can be arbitrarily
chosen as 10 pu at 60Hz.
11.52 Equation 5.1
𝑍𝑏𝑎𝑠𝑒 𝐿𝑉 = = 1.322 Ω
100
At the nominal frequency of 60Hz, 𝑙𝑒𝑡 𝑍𝐶𝐴𝑃 = 10 𝑝𝑢 = 13.22𝛺
1 Equation 5.2
𝐶= ≈ 200𝜇𝐹
𝜔𝑍𝐶𝐴𝑃
b. Neglect the parallel resistor and assume a series LC circuit. Using the capacitance
calculated in step (A) select the inductance such that a resonance occurs at the
modulation frequency and the impedance of the capacitor and inductor cancel each
other to provide a path to ground. The resonant frequency of a series LC circuit is
1
𝜔= and the resonance should occur at 5000 Hz.
√𝐿𝐶
1 1 Equation 5.3
𝐿= 2 = 2 −6
= 5.066𝑒 −6
𝜔 𝐶 (2𝜋 ∗ 5000) ∗ 200.65𝑒
c. Select R such that its impedance is equal to that of the parallel connected inductance
at the modulating frequency.
𝑅 = 𝜔𝐿 = (2𝜋 ∗ 5000) ∗ 5.066𝑒 −4 = 0.15915Ω Equation 5.4
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5.5 TWO-LEVEL STATCOM CONVERTER, AC REACTORS, AND DC BUS
The two level STATCOM component models the two-level STATCOM, AC reactors, and the
DC capacitors. Within the VSC 2-LEVEL EMBEDDED BRIDGE CONFIGURATION parameters of
the converter, the number of phases is set to three and the Enable DC neutral Rail
Connection is set to ‘Yes’.
The firing pulse signals for the converter is specified in the VALVE FIRING PULSES INPUT
NAMES tab of the converter parameters. Each phase of the converter has two valves
controlled by a two bit firing signal. For each phase of the converter, the user must specify:
(1) the name of the firing pulse word, and (2) the location of the two bits in the firing pulse
word used to control the two valves of that phase. In this tutorial, the same control word,
FPOUT1, is used for each phase; however, specific bits of FPOUT1 will control the switching
of specific valves in the converter. The bit numbers of FPOUT1 used to control the firing of
the valves is selected such that bit 1 and bit 2 control valve 1 and 2 of phase A, bit 3 and 4
control valve 3 and 4 of phase B, and bit 5 and 6 control valve 5 and 6 of phase C, as shown
in Figure 5.11.
Figure 5.11: Firing Signals For Each Valve Of The Two-Level Converter
For each phase, the two LSB of the control word are used to set the switching state of the
two valves. The user must right shift the control word by a specified number of bits such that
the two LSB are the bits used to control the switching of the valves, as shown in Figure 5.12.
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Figure 5.12: Firing Pulse Input
The switches of all converter models in substep are modelled as resistive switches. The ON
Resistance, OFF resistance, and snubber capacitance and resistance are specified in the
VALVE PARAMETERS tab. In this tutorial, the parameters chosen are shown in Figure 5.13.
Figure 5.13: Valve Parameters
The AC side reactor can be set from within the AC REACTOR PARAMETERS tab of the
converter parameters. The inductance is set to 0.001H and the resistance is set to 0Ω.
The DC bus consists of two series capacitors with a grounded midpoint. These capacitors can
be set from within the DC CAPACITOR PARAMETERS tab. The capacitance of each DC
capacitor is set to 2500uF and a series resistance of 0.0001Ω.
Enable monitoring of the AC terminal voltages and currents, i.e. mon4, mon5, mon6 and
mon10, mon11, mon12 from the ENABLE MONITORING IN RUNTIME AND CC. Set the
converter AC terminal voltage signal names to Vta, Vtb, and Vtc, and the AC terminal current
names to Ita, Itb, and Itc from within the SIGNAL NAMES tab.
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5.6 STATCOM CONTROLS
The STATCOM regulates the voltage at the point of common coupling (PCC) of the AC system.
The high level control structure of the STATCOM used in the tutorial is shown in Figure 5.14.
The PCC AC voltage is regulated through a PI controller whose output sets the PCC reactive
power reference for a reactive power controller. The STATCOM converter DC side consists
of capacitors whose voltage must also be regulated. Conventional DQ decoupled current
controls are utilized for this STATCOM tutorial. The d and q axis current references for the
current control are obtained from the DC voltage control and the reactive power controller
respectively. The output of the DQ decoupled current control are the modulation
waveforms, which are fed into a firing pulse generator to generate the firing pulses for the
2-level VSC STATCOM.
Figure 5.14: STATCOM Controls
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Each portion of the control scheme will be discussed in further detail in this section. In Figure
5.14, all the high frequency elements are modelled in a substep hierarchy box such as the
power electronic circuit, triangle wave generator and the firing pulse generator to ensure
that the high frequency dynamics are captured, as shown in Figure 5.15 (b). The remaining
controls are placed in the mainstep environment, as shown in Figure 5.15 (a), (c), and (d).
Figure 5.15 shows the completed RSCAD draft case, and where each of the components are
located. These figures can be used as a reference when building the case. In addition, a
completed case is available in RSCAD’s tutorial folder.
Main Draft Window : Consisting Of A Substep Environment, And Two Hierachy Boxes Containing The
Controls.
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(a) Inside Substep Hierachy Box: STATCOM circuit, triangle wave generation, firing pulse
generation, HD plot signals, and voltage source controls.
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(b)
(c) Inside Controls Hierachy Box: AC source voltage controls, PLL, ABC-DQ, PQ meters, AC voltage
control, DC voltage control, Q control, DQ decoupled current control
(d) Inside Master Controls Hierachy Box: Base Values, per unit calculations,
sliders for PI gains, sliders for reference signals
Figure 5.15: RSCAD Draft Case
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5.7 BASE VALUES
The controller is based on per unit quantities. The 100MVA system has a voltage base of
11.5kV on the converter side of the transformer, and a base voltage of 93kV on the system
side of the transformer. The DC voltage base is set to 30kV.
These controls are placed in the mainstep environment within the ‘Master Controls’
hierarchy box, as shown in Figure 5.15 (d), using components from the controls library.
Figure 5.16: Base Values
The peak line to neutral base values for the high voltage and low voltage sides of the
transformer are computed, as shown in Equation 5.5, Equation 5.6, and Equation 5.7.
𝑉𝐿𝐿 Equation 5.5

𝑉𝑏𝑎𝑠𝑒𝑃𝐾 = √2 ∗
√3
𝑆𝑏𝑎𝑠𝑒 Equation 5.6
𝐼𝑏𝑎𝑠𝑒𝑃𝐾 = √2 ∗
√3 𝑉𝑏𝑎𝑠𝑒
(𝑉𝑏𝑎𝑠𝑒 )2 Equation 5.7
𝑍𝑏𝑎𝑠𝑒 =
𝑆𝑏𝑎𝑠𝑒
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Figure 5.17: Base Value Calculations
5.8 DC LINK VOLTAGE CONTROL
The DC link voltage of the STATCOM is regulated to a reference value set by a slider. In
Runtime, the slider is set to 1pu. The measured DC link voltage is the difference between the
positive rail voltage, VP, and the negative rail voltage, VN. Both VP and VN are monitored
using substep node labels in the STATCOM circuit, as shown in Figure 5.15 (b). The per unit
Vdc value is computed as shown in Figure 5.18.
Figure 5.18: Per-Unit Calculation Of The DC Voltage, VDC
The measured DC link voltage is regulated to the reference DC link voltage via a PI controller,
as shown in Figure 5.19. When the measured DC voltage is larger than the reference voltage,
the current out of the STATCOM should increase to lower the DC capacitor voltage, and vice
versa. Due to this relationship, the error between the DC voltages is multiplied by a factor of
-1. The output of the PI controller sets the d axis current reference for the DQ decoupled
current controller.
Figure 5.19: DC Voltage Control
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The PI box shown in Figure 5.19 is a hierarchy box containing the PI controls shown in Figure
5.20. The signal names added at the terminals of the hierarchy box, such as Vdcerror and
Idref, should also be referenced inside the hierarchy box, as shown in Figure 5.20. An internal
limiter on the integral control ensures that integral windup is avoided.
Figure 5.20: Inside PI Controller Hierachy Box For Vdc Control
The reference voltage, and the PI controller gains (Kp_Vdc and Ti_Vdc) are set by sliders, as
shown in Figure 5.21. These controls were placed in the ‘Master Controls’ hierarchy box, as
shown in Figure 5.15 (d).
Figure 5.21: Sliders For Pi Controller Gains, And Vdc Reference
5.9 PLL, ABC-DQ TRANSFORM, AND FILTERS
Conventional power system control is performed in the DQ-frame due to its several control
benefits compared to other reference frames such as ABC and 𝛼𝛽-frame representations.
The ABC-frame and 𝛼𝛽-frame are stationary frames of reference, whereas, the DQ-frame is
a rotating reference frame. When the DQ-frame of reference and the space vector rotate at
the same frequency, the space vector appears constant with reference to the DQ-frame. As
a result, utilizing simpler controllers, such as PI controllers, are possible. In addition, control
of three phase quantities in DQ-frame reduces the control variables to two, compared with
ABC-frame which has three control variables. It is this DQ-frame control that will
implemented in this tutorial.
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5.10 PLL CONTROLS
PLL is used to extract the system frequency, as shown in Figure 5.22. This frequency is fed to
the ABC to DQ transformation component in RSCAD, as shown in Figure 5.24, to set the
frequency of rotation of the DQ-frame.
Figure 5.22: PLL Controls
For the PLL controls of Figure 5.22, the location of the components in the RSCAD library are
shown in Table 5.
Table 5: Components For PLL Controls

PLL Controls→ Signal Processing rtds_sharc_ctl_PLL
ANGLE range limit Controls → Signal Processing rtds_sharc_ctl_ANGLEFIX
Set the PLL parameters as shown in Figure 5.23.
Figure 5.23: PLL Parameters
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5.11 ABC-DQ TRANSFORM CONTROLS
The PCC AC voltages, and the STATCOM terminal currents are transformed from ABC to DQ-
frame as shown in Figure 5.24. The Configuration parameters for the ABC to DQ-frame
controller are set such that Vq leads Vd and the DQ0 quantities are computed as peak
values.
A low pass filter is placed at the output of the ABC to DQ block to remove high frequency
noise at the PCC voltage, as shown in Figure 5.24. The time-constant of the filter is selected
as 𝜏 = 0.01𝑠.
Figure 5.24: ABC-DQ Transform And Filters
The components selected for the ABC-DQ transform and the filters are shown in Table 6.
Table 6: Components For ABC-DQ Transform And Filters

ABC-DQ Transform Controls→ Signal Processing rtds_sharc_ctl_ABC2DQ0
Filter Controls → Transfer Functions rtds_sharc_ctl_REALPL
5.12 PCC AC VOLTAGE CONTROL
The function of the STATCOM is to exchange reactive power with the grid to regulate the
voltage at the PCC. The reference PCC AC voltage is set by a slider. In Runtime, the slider is
set to 1pu. PCC AC voltage control, to regulate the measured voltage to the reference
voltage, is achieved through a PI controller. The output of the PCC AC voltage control sets
the reference reactive power for the reactive power controller.
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Figure 5.25: PCC AC Voltage Control
The contents of the PI controller hierarchy box is shown in Figure 5.26.
Figure 5.26: Inside PI Controller Hierarchy Box For Vac Control
The slider for the reference PCC AC voltage, and sliders for the PI controller’s proportional
and integral constant must be created, as shown in Figure 5.27. These controls are placed in
the ‘Master Controls’ hierarchy box, as shown in Figure 5.15 (d).
Figure 5.27: Sliders For Vsd PI Controller Gains, And Vsd Reference
5.13 Q CONTROL
The reference reactive power is set by the output of the PCC AC voltage controller. The
measured reactive power is computed using PQ meters as shown in Figure 5.28. The output
of the PQ meter is multiplied by -1 to account for the reference direction of power which is
out of the STATCOM.
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Figure 5.28: PQ Meter For P And Q At PCC
The parameters of the PQ meter component is shown in Figure 5.29. The output is scaled to
per unit with a rated MVA of 100MVA. The voltage and current signal are already aligned so
no delay is required, as shown in Figure 5.29. Default values are kept for the Proc and Pri
parameters.
Figure 5.29: PQ Meter Parameters
The STATCOM’s reactive power at the PCC is regulated through a PI controller, as shown in
Figure 5.30.
Figure 5.30: Q Control
The contents of the PI controller hierarchy box is shown in Figure 5.31.
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Figure 5.31: Inside PI Controller Hierarchy Box For Q Control
The PI controller’s proportional and integral constant sliders must be created, as shown in
Figure 5.32.
Figure 5.32: Slider For PI Controller Gains In Q Control
The output of the Q controller sets the q axis current reference for the DQ decoupled current
controller.
5.14 DQ DECOUPLED CURRENT CONTROL
Conventional DQ decoupled current control for the STATCOM AC terminal currents are
utilized. A quick overview of the control strategy is covered along with its implementation in
RSCAD. Let’s consider the STATCOM tutorial circuit, shown in Figure 5.33.
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Figure 5.33: STATCOM Tutorial Circuit
The voltage across the line inductance (transformer and reactor inductance) is shown in
Equation 5.8, where 𝑖𝑡 is the STATCOM AC terminal current, 𝑉𝑡 is the STATCOM AC terminal
voltage, 𝑉𝑠 is the PCC AC voltage, and 𝐿 is the line inductance. In this tutorial the line
resistances are omitted.
𝐿𝑑𝑖𝑡 Equation 5.8
= 𝑉𝑡 − 𝑉𝑠
𝑑𝑡
Writing Equation 5.8 in dq-frame results in Equation 5.9 and Equation 5.10, where d and q
values are coupled by an 𝐿𝜔0 term:
𝐿𝑑𝑖𝑡𝑑 Equation 5.9
= 𝐿𝜔0 𝑖𝑡𝑞 + 𝑉𝑡𝑑 − 𝑉𝑠𝑑
𝑑𝑡
𝐿𝑑𝑖𝑡𝑞 Equation
= −𝐿𝜔0 𝑖𝑡𝑑 + 𝑉𝑡𝑞 − 𝑉𝑠𝑞
𝑑𝑡 5.10
Two new terms, 𝑢𝑑 and 𝑢𝑞 , are introduced to decouple the dynamics, as shown in Equation
5.11 and Equation 5.12.
𝑢𝑑 = 𝑉𝑡𝑑 + 𝐿𝜔𝑜 𝑖𝑞 − 𝑉𝑠𝑑 Equation 5.11
𝑢𝑞 = 𝑉𝑡𝑞 − 𝐿𝜔0 𝑖𝑑 − 𝑉𝑠𝑞 Equation

5.12
Due to the nature of the two-level converter, DC voltage and the AC terminal voltage of the
STATCOM must satisfy Equation 5.13 and Equation 5.14, where 𝑉𝑡 is the peak LN AC voltage,
𝑉𝑑𝑐 is the DC link voltage, 𝑚 is the modulation index, and the subscripts indicate d-axis or q-
axis in the dq-frame.
2 Equation 5.13
𝑚𝑑 = 𝑉𝑡𝑑 ( )
𝑉𝑑𝑐
2 Equation 5.14
𝑚𝑞 = 𝑉𝑡𝑞 ( )
𝑉𝑑𝑐
The equation for the modulation index in dq-frame can be re-written, as shown in Equation
5.15 and Equation 5.16, by substituting Equation 5.11 and Equation 5.12 into Equation 5.13
and Equation 5.14.
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2 Equation 5.15
𝑚𝑑 = (𝑢 − 𝐿𝜔0 𝑖𝑞 + 𝑉𝑠𝑑 )
𝑉𝐷𝐶 𝑑
2 Equation 5.16
𝑚𝑞 = (𝑢 + 𝐿𝜔0 𝑖𝑑 + 𝑉𝑠𝑞 )
𝑉𝐷𝐶 𝑞
The implementation of the DQ decoupled current control in RSCAD is shown in Figure 5.34.
The output of the DQ decoupled current control is converted to the three phase modulation
reference waveforms, 𝑚𝑎 , 𝑚𝑏 and 𝑚𝑐 .
Figure 5.34: Dq Decouple Current Control
The contents of the PI controller hierarchy box for the d-axis and q-axis current control is
shown in (a) and (b) respectively.
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(a) Contents of PI controller hierarchy box for d-axis current control
(b) Contents of PI controller hierarchy box for q-axis current control

Figure 5.35: Inside PI Controller Hierarchy Box DQ Decoupled Current Control
The per-unit 𝜔𝐿 term is calculated as shown in Figure 5.36. The per-unit line inductance
includes the transformer inductance and the series inductance at the AC terminals of the 2-
level VSC STATCOM.
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Figure 5.36: Calculation Of 𝜔𝐿 In pu
The per-unit 𝑉𝑑𝑐/2 term is calculated as shown in Figure 5.37.
Figure 5.37: Vdc/2 Per-Unit Calculation
Sliders for the PI controller gains are created, as shown in Figure 5.38.
Figure 5.38: Sliders For DQ Decoupled PI Controller Gains
5.15 MODULATION WAVEFORMS, CARRIER AND FIRING PULSE GENERATOR
The firing pulse generator generates the firing pulses to set the switch state of the valves in
the converter. To illustrate the concept, let’s consider a single phase circuit with two
switches (S1, S2) shown in Figure 5.39 (a). At the midpoint of the switches is the AC terminal
output, and across both switches is a DC voltage. The firing pulse generator uses a SPWM
scheme where a sinusoidal modulation waveform is the reference waveform, and a high
frequency triangular waveform is the carrier, as shown in Figure 5.39 (b). When the
reference waveform is greater than the carrier, S1 is closed while S2 is opened resulting in
an output waveform of Vdc/2 at the AC terminal, as shown in Figure 5.39 (c). When the
reference waveform is less than the carrier, S1 is open while S2 is closed resulting in an
output waveform of –Vdc/2 at the AC terminal. This square waveform contains high
frequency content which must be filtered out using High Pass filters at the terminal of the
converter. The resulting filtered waveform should have the same wave-shape as the
modulation waveform.
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Figure 5.39: SPWM Scheme
In this tutorial, SPWM is used to control a two-level three phase converter. Each phase of
the three phase converter assumes complimentary switching, i.e when the upper switch is
closed the lower switch of that phase is open and vice versa.
5.16 REFERENCE WAVEFORMS
The output of the DQ decoupled current control are the modulation waveforms: ma, mb,
and mc.
5.17 CARRIER WAVEFORMS
The triangle carrier waveform is created using components from the control library, as
shown in Figure 5.40. These controls are place in the substep box so that they can be
computed at a high resolution. The triangle waveform has peak values of ±1 with a switching
frequency set to 5kHz.
Figure 5.40: Triangle Carrier Wave Generation For SPWM Scheme
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5.18 FIRING PULSE GENERATION
The firing pulse generator component (rtds_ss_FPGEN.def) can be found in the Substep
Signal Generators category of the substep library. For each of the three phases, a comparator
within the firing pulse generator will compare the reference waveform with the carrier
waveform. Within the VSC FIRING PUSE GENERATOR tab, the number of comparators should
be set to 3. The name of the triangle wave carrier signal, deblock signal, and the output firing
word signal are also specified within this tab, as shown in Figure 5.41.
Figure 5.41: Firing Pulse Generator Parameters: Configuration
Parameter tabs for comparator # 1, 2 and 3 correspond to phase A, phase B, and phase C
respectively. Within the comparator parameters tab, enter the modulation input name, and
leave the remaining fields as default, as shown in Figure 5.42. The modulation input name
for phase A, B, and C is ma, mb, and mc respectively.
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Figure 5.42: Firing Pulse Generator Parameters: Comparator Parameters
The description of the “Two-Level STATCOM Converter, AC reactors, and DC bus” under
section 5.1 on the STATCOM CIRCUIT covers the implementation of the firing pulse controls
in further details.
The valves of the STATCOM can be blocked by the user through the DBLKL signal as shown
in Figure 5.41. As shown in Figure 5.11, the firing pulse word uses the six least significant bits
to set the firing signals for the six valves of the STATCOM. To block all six valves, a deblock
signal of 0 must be applied to all the least six significant bits, as shown in Table 7. Similarly,
to deblock all six valves, a deblock signal of 1 must be applied to all the least six significant
bits.
Table 7: Block/Deblock STATCOM Controls
STATE Binary Integer Value

BLOCK STATCOM DBLKL = 000…..000000 DBLKL = 0
DEBLOCK STATCOM DBLKL = 000…..111111 DBLKL = 63
The controls to create the deblock logic are show in Figure 5.43. The user can block and
deblock the STATCOM using a switch in Runtime.
Figure 5.43: Deblock Controls For The STATCOM
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5.19 HIGH RESOLUTION SCOPE
For Runtime plots, the default setting is to plot a data point each mainstep. For high
frequency signals, it is desirable to plot at the substep resolution. To plot a data point each
substep in Runtime, the high resolution scope component, rtds_ss_scope, is used. Simply
attach the signal name to the scope and the signal in Runtime will be updated with substep
resolution. There is a limit of 16 scopes for each substep block. As such, it is recommended
to use the scope component for monitoring signals that contain higher frequency harmonics.
Set up the HD plot signals as shown in Figure 5.44 to monitor the voltages at the terminal of
the STATCOM (Vta, Vtb and Vtc) and the high frequency carrier waveform (TWAVE) in high
resolution in the Runtime environment.
Figure 5.44: High Resolution Signal Monitoring
5.20 SUBSTEP HIERARCHY BOX PARAMETERS
When the case is built and compiles successfully, it is time to define the time-step. The time-
step for each substep block is configured by specifying number of times the substep network
will execute for every mainstep. This value is configured in the parameter SubstepDivisor as
shown in Figure 5.45. In the figure, the divisor is set to 20. If the mainstep is set to 50 usec,
the substep will execute at 50/20= 2.5 usec.
Figure 5.45: Substep Hierarchy Block Substep Options
It is likely that the user would like to run their system at the lowest possible substep so it is
up to them to find the optimal value. There is no ideal method to determine the best value
for the divisor other then a ‘guess and check’ approach. Using a mainstep of 45 µs, it was
determined that the divisor can be set to 61 which results in a substep time-step of ~0.74
µs. Smaller time-steps result in SMALL TIMESTEP OVERFLOW in runtime environment.
Compile and Save your draft case.
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5.21 RUNTIME
Once the draft case has successfully compiled, open the Runtime window and create the
plots shown in Figure 5.46,
The triangular carrier waveform, and the two-level STATCOM terminal voltages have substep
resolution due to the substep scope that connects to the signals in the draft case. For signals
that do not connect to a substep scope in draft, the resolution is that of the mainstep.
For the STATCOM VSC controller to be effective, the converter must be deblocked using the
“BLKL” switch.
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Figure 5.46: Runtime Window
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The DC voltage is regulated to the reference slider value of 1pu, as shown by the signal Vdc
in Figure 5.47.The AC voltage is regulated to the reference slider value of 1pu, as shown by
the signal Vsd in Figure 5.47, by controlling the reactive power supplied at the PCC. The
reactive power controller regulates the reactive power, Qs, to its reference value, Qsref,
requested by the AC voltage controller. The DC voltage controller and the reactive power
controller set the reference signals for the d-axis and q-axis current controllers, respectively.
Both DQ decoupled current controllers regulate the measured current to the reference
values as shown in Figure 5.47. The inner loop controllers are chosen to operate faster
(smaller Ti constant) compared to the outer loop controller for effective control of the
signals.
Figure 5.47: Plots From Top To Bottom: DC Voltage Regulation At 1pu, d-axis AC voltage
regulation to 1pu, Reactive power at PCC,
STATCOM AC terminal d-axis current and q-axis current and reference
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Switching the load into the circuit:

The STATCOM effectively regulates the PCC AC voltage and DC voltage at 1pu when
the load is switched into the circuit, as shown by the transient response in Figure
5.48. The reactive power and the inner loop DQ-decoupled current controllers
effectively regulate the measured values to their reference values when the load is
switched into the circuit.
Figure 5.48: Plots From Top To Bottom: DC Voltage Regulation At 1pu,

D-Axis AC Voltage Regulation To 1pu, Reactive Power At PCC,
STATCOM AC Terminal D-Axis Current
And Q-Axis Current
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6 SIMPLE PWM
6.1 OVERVIEW
This simple tutorial is meant as a quick introduction on how a simple Sinusoidal Pulse Width
Modulation (SPWM) scheme can be implemented on the RTDS Simulator using the substep
simulation environment. The example is fairly trivial but is nevertheless instructive. The
circuit shown in Figure 6.1 will be assembled and simulated.
Figure 6.1: Test Circuit

Ideal sources will be used for the DC Bus and a sinusoidal PWM scheme will be used to create
a switched voltage waveform at Bus #3. That switched waveform will be filtered to produce
a signal with reduced harmonic content at Bus #2. The voltage is then stepped-up to 93 kV
and will supply a purely resistive load.
6.2 STEP #1
The first step is to add a substep box to your case. All portions of the circuit running at the
reduced timestep should be placed inside this box. A substep box is simply a hierarchy box
which has been setup to run at substep resolution.
Copy a hierachy box component from the Power System/General library into the draft case.
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Figure 6.2 : Location of hierarchy box in library
Edit the hierarchy box parameters for substep by right-clicking on the hierarchy box and
selecting Edit->Parameters. Please change the highlighted parameters as shown in Figure
6.3.
Figure 6.3: Parameters for the hierarchy box

With the substep divisor set to 25 and with the default main timestep of 50µs, the substep
timestep is 2µs. If desired, the substep divisor and/or the main timestep can be further
adjusted so that the substep network can execute at the smallest possible.
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Next, the circuit of Figure 6.4 should be assembled inside a substep box. Double click on the
substep box to open the canvas where the substep network can be built. Please note that in
this first step the controls are simplified (ie: no firing pulses). These controls will be enhanced
in subsequent steps.
Figure 6.4: RSCAD Circuit
Explore the library to find the necessary components. Although all mainstep control and
power system components from the RSCAD library can be used inside the substep box,
substep library components are optimized for the substep environment and should be used
for best performance. Table 8 shows the library location for the components used in this
case.

DC Source Power System/Sources rtds_ss_BRC3
Power System/Power Electronics/VSC rtds_ss_LEV2_V3
2-level Converter Converters
HP filter Power System/Filters lf_rtds_sharc_sld_SHUNTHP
Transformer Power System/Transformers/Conventional rtds_ss_TRFS1PH
lf_rtds_sharc_sld_SHUNTRE
Resistive Load Power System/Passive Elements S
Table 8: Component Selection
A listing of main component parameters is given below. In this first step, no firing pulses are
provided to the two-level bridge.
51
DC Bus:
Voltage: ±20kV
Two Level Converter:

Numberof Phases = 3
Enable DC Neutral Rail = Yes Firing Pulse input: FPWORD
AC reactor, L=5.05e-4H, R=0 DC Capacitor = 1e4uF
Valve Parameters: default
Load:
R = 86.49 Ω
Transformer:
Primary Voltage: 93 kV L-L, rms
Secondary Voltage: 13.8 kV L-L, rms
Rating: 100 MVA
Winding Resistance = 0.0 pu
Winding Reactance = 0.1 pu
Filter:
R = 0.90675 Ω
L = 1.1453e-4 H
C = 139.3 μF
Compile the case and create a RUNTIME interface and monitor the 3-phase RMS voltages at
Buses 1, 2 and 3. Are they as expected?
6.3 STEP #2
With the basic circuit assembled, the next step is to create the controls for our SPWM
scheme. In a standard SPWM scheme a sinusoidal modulation signal is compared with a high
frequency triangle wave as demonstrated in Figure 6.5 (B). When the value of the triangle
wave exceeds that of the modulation signal then switch S1 of Figure 6.5 (A) will be turned
off. Conversely, when the amplitude of the triangle wave is less than that of the modulation
waveform then switch S1 will be turned on. The switch S2 will be controlled in a
complimentary fashion.
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Substep Tutorial
Figure 6.5: Sinusoidal PWM Scheme

The signal 𝑉𝑜𝑢𝑡 from the circuit will be a switched waveform similar to that shown Figure 6.5
(C). With the SPWM scheme that will be deployed, it can be shown that the magnitude of
the filtered signal that would ideally appear at each phase of Bus 2 will be 𝑚 ∙ 𝑉𝐷𝐶 , where m
is the amplitude modulation ratio. Similar principles of operation apply to all three legs of
the bridge.
The control circuit shown in Figure 6.6 can be used to create the firing pulses for the switches
of all three phases. These controls are built inside the substep box to capture the high
frequency carrier and firing pulse waveforms. The HD signal scopes allow signals to be
viewed with substep resolution in RunTime. The modulation waveforms will have the same
wave-shapes as the voltages we are trying to create. The triangle wave generator provides
the high resolution triangle wave needed for the SPWM; in this case, with a frequency of 21
times the fundamental (or 1260 Hz). A slider can be used to increase the frequency to see
the effect on the generated AC waveforms.
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Substep Tutorial
Figure 6.6: SPWM Controls Located Inside Substep Box

The generated high resolution triangle wave is then used by the substep firing pulse
generator and is compared to the modulation signals generated. This comparison must be
done in the substep in order to accurately determine the instants at which the switching
events should occur. The firing pulse word that is generated is created such that bit 1
controls valve 1, bit 2 controls valve 2, bit 3 controls valve 3…etc for the two level converter.
Within the two level converter parameters, the appropriate bit shift must be applied to the
firing pulse words, as shown in Figure 6.7.
Figure 6.7: Converter Parameters

Note that the firing pulse generator needs a deblock signal. When the six least significant
bits of the deblock word are high (DBLK = 00…111111), each of the six valves of the converter
will be deblocked. The switch component is requires as input a decimal integer value for the
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Substep Tutorial
switch state; therefore, DBLK = 0 when the switch is off, and DBLK = 63 when the switch is
on and deblocking the converter.
Compile your case and create a RUNTIME interface that looks similar to that of Figure 6.8.
How do your simulation results compare to those shown? Change the amplitude modulation
index, m. Does it affect the simulation as you expect it should? How does the switching
frequency affect the results?
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Substep Tutorial
Figure 6.8: Runtime Metering And Control
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Substep Tutorial
6.4 STEP #3
Up until this point, the circuit in this tutorial has been modelled entirely in the substep
environment. When possible this is the best option but it isn’t always practical. The main
timestep can model much larger circuits and the need for these larger circuits sometimes
drives the need to interface substep and main timestep simulations. A conventional AC
system that is operating at the nominal frequency (50 or 60 Hz) does not require the reduced
time step of the substep environment to be accurately simulated.
In order to interface main and substep simulations, an interface transmission line or

interface transformer must be used. One side of the interface transformer/tline will have
only main timestep components connected to it and the other side will only be connected
to substep. In this example we will use the interface transformer. Whenever possible thed
circuit should be divided at a point where an actual transformer exists. This is due to the
fact that the interface transformer has leakage reactance. To minimize the impact of
inserting the interface transformer into the circuit it is best to insert it a point where a
leakage reactance exists. It is important to know that the interface transformer is modelled
as a travelling wave transmission line and therefore the component introduces shunt
capacitances. Please see the substep manual for more information.
Some slight modifications to the case from Step #2 will be made. The resistive load is moved
from the substep into the main timestep, as described in the instructions below:
1. Save the existing case under another name so that we can retain the case where everything
is simulated using substep.
2. Replace the substep transformers with three single phase interface transformers
(rtds_ss_ITFC_TRF_SS). Figure 6.9 illustrates how this can be done.
Figure 6.9: Substep circuit with Interface Transformer
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Substep Tutorial
3. Duplicate main timestep interface transformers outside the substep hierarchy box and
move Bus 1 and the resistive load to the main timestep as show in Figure 6.10.
4. Compile the case and run it. Does it work as expected?
Figure 6.10: Main Timestep Side of Substep-Mainstep Interface

6.5 STEP #4 (OPTIONAL)
The control system from Step #2 can be modified so that a simple integral regulator keeps
the voltage at Bus #2 at some desired set-point. Modify the controller as indicated in Figure
6.11 then compile and run the case again. Does the regulator work?
Figure 6.11: Optional Voltage Control
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Substep Tutorial
The PI controller does not need to execute in the substep as the reduced time step is not
required. Therefore, in a practical case, the regulating controller would be modelled in the
mainstep.
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Substep Tutorial
7 INTERFACING MAINSTEP AND SUBSTEP ENVIRONMENTS

Up until this point, the power electronic circuits in this tutorial have been built inside the
substep hierarchy box which means that the circuit and any controls in the substep box are
simulated at the substep resolution. When possible this is a good option, but it is not always
practical. The substep simulation is relatively computationally intense when compared to
the mainstep simulation so it does not always make sense to model everything with the level
of detail provided by the substep simulation. In order to interface the mainstep and substep
simulations, a component called an interface transformer or interface transmission line must
be used. In this section, the interface transformer will be discussed. There are two
components involved for the interface; one component, rtds_ss_ITFC_TRF_SS.def, is placed
in the substep box and connects to the substep network, while another component,
rtds_ss_ITFC_TRF_MS.def, is placed in the mainstep and connects to the mainstep network.
Currently this interface transformer is only available in single phase form; a three phase
transformer can be created using three of these single phase transformers. Whenever
possible, the circuit should be divided at a point where an actual transformer exists. Details
on the implementation of the interface transformer components are given at the end of this
section. As an exercise, the SIMPLE STATCOM from Section 5 can be modified. The
transformer will be replaced by an interface transformer and the source and load will be
modeled using mainstep components since there is no need to model these devices at
substep resolution. Figure 7.1 illustrates how the original circuit is to be divided.
Figure 7.1: Division of substep case for mainstep interface
The first step would be to remove the source, load and breaker from the substep simulation
and move them to the mainstep network replacing substep components with mainstep
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power system components. For the example with the simple STATCOM circuit in Section 5,
set the voltage time constant of the source to zero (Tc = 0). An inductor component should
also be added in series with the source. If these components in substep that were to be
moved to mainstep were built using power system components, they can be simply grouped
and moved to the mainstep environment. The transformers in the substep environment will
need to be replaced with substep interface transformers (rtds_ss_ITFC_TRF_SS.def) with
equivalent ratings, leakage reactance and resistance. The next step is to place substep
interface transformer for mainstep network side (rtds_ss_ITFC_TRF_MS.def) into the
mainstep network. Make sure that the mainstep and substep interface transformers have
the same transformer name. Figure 7.2 illustrates what the circuit should look like with the
source and load modeled in the mainstep.
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Substep Tutorial
(a) Mainstep with interface transformer
(b) Inside substep box with interface transformer

Figure 7.2: Simple STATCOM Case Divided Between Mainstep And Substep Simulation
Using An Interface Transformer
Table 8 shows where the interface transformer components can be obtained.
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Table 9: Interface Transformer Components For Substep And Mainstep

Interface transformer. Substep→Substep/Mainstep Interface rtds_ss_ITFC_TRF_SS
Substep side
Interface transformer. Substep→Substep/Mainstep Interface rtds_ss_ITFC_TRC_MS
mainstep side
7.1 INTERFACE TRANSFORMER
The interface transformer model is implemented as a travelling wave transmission line. This
approach to modeling the transformer was chosen because of the stability that it provides.
The transmission line is kept quite short; its travel time is fixed at 1.5 mainsteps. The
inductance, L, of the transmission line is chosen so that it is equal to the leakage of the
interface transformer. The capacitance, C, of the transmission line is then calculated by
RSCAD using the travel time and the inductance of the line specified by the user. For the
purpose of this calculation, the line is assumed to be lossless. The actual model can
accommodate the presence of losses. Assuming a lossless line, the travel time of wave
propagating on a transmission line is given by Equation 7.1, where L is the line inductance in
H, and C is the line capacitance in F.
𝜏 = √𝐿 ∙ 𝐶 Equation 7.1
With the travel time set to 1.5 times the mainstep, Equation 7.1 can be used to determine
the line capacitance. The result is given in Equation 7.2.
2
(1.5 ∙ ∆𝑡𝑀𝑎𝑖𝑛𝑠𝑡𝑒𝑝 ) Equation 7.2
𝐶=
𝐿
This capacitance is a direct consequence of modeling the transformer as a transmission line
and would not normally exist in the circuit. Care should be taken to make certain that this
capacitance is not too large. If it is, then it will start to impact the simulation; something
which should be avoided. In general, impedance of the capacitance should be significantly
larger than the surrounding impedances.
By inspection of Equation 7.2, it is evident that if the leakage of the interface transformer is
chosen very small then the capacitance, C, will be large. In order the avoid this situation, the
interface transformer leakage must be greater than 0.05 pu.
The capacitance and inductance described above represent distributed parameters. In order
to be able to assess whether the capacitance of the line has become too large, it is helpful
to find the effective capacitance seen at terminals of the interface transformer. In order to
do this, the π-circuit equivalent for the transmission line/interface transformer must be
found. Figure 7.3 shows this equivalent; an ideal transformer has been added to the
transmission line π-circuit equivalent to model the voltage transformation capabilities of the
interface transformer.
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Substep Tutorial
Mainstep Substep
Simulation Simulation
Figure 7.3 Π -Circuit Equivalent For The Interface Transformer With An Ideal Transformer
The effective capacitive reactance of the interface transformer seen from the large time-
step side of the interface transformer is labelled as XC and can be calculated using Equation
7.3 [2]. In this equation ZC is the characteristic impedance of the line, γ is the propagation
constant of the line and l is the length of the line.
𝑌𝑒 −1 1 𝛾𝑙 −1 Equation 7.3
𝑋𝐶 = ( ) = ( tanh ( ))
2 𝑍𝐶 2
With the assumption of a lossless line Equation 7.3 can be simplified to Equation 7.4.
−1
𝑌𝑒 −1 1 𝑗𝜔 ∙ 1.5 ∙ ∆𝑡𝑚𝑎𝑖𝑛𝑠𝑡𝑒𝑝 Equation 7.4
𝑋𝐶 = ( ) = ( tanh ( ))
2 𝑍𝐶 2
𝐿
Where 𝑍𝐶 = √𝐶
When a case containing an interface transformer is compiled the effective capacitive
reactance is calculated for the rated frequency of the interface transformer and is listed in
the MAP file, as shown in Figure 7.4.
Figure 7.4: MAP File
The MAP file can be viewed by pressing the view button in DRAFT’s toolbar, as shown in
Figure 7.5, and selecting MAP File in the dialog that appears.
Figure 7.5: The ‘View’ Button To Open The MAP File.
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8 CONNECTING SUBSTEP BOXES USING SUBSTEP

TRANSMISSION LINES
If the network size becomes significant and reaches the node limit of 60 nodes, it might
become necessary to distribute the system across multiple substep cores. The other scenario
is that the system running on a single core requires a time-step that is too large for the user’s
requirement. By distributing the system across two substep cores, the time-step will be
reduced.
The process of linking substep boxes is analogous to connecting different racks for the large
time-step simulation. The network solutions for substep box are effectively decoupled if the
travelling time of the transmission line connected between them is greater than a substep.
This decoupling allows the network solutions to be solved independently and results in
significant computational savings. As an example, let’s consider the scenario when the
substep time-step is 1us. Assuming a wave propagation velocity of 3x108 m/s, the minimum
length of the substep transmission line is 300m, which is significantly shorter than the large
time-step transmission lines which are typically on the order of 15km.
Similar to large time-step transmission lines, three components are required to make a
substep transmission line: (1) a sending end terminal, (2) a receiving end terminal and (3) a
calculation block, as shown in Figure 8.1.
(a) Sending End (b) Calculation Block (c)Receiving End

Figure 8.1: Substep Transmission Line
In order to link two substep boxes, one end of the substep transmission line would be placed
in one of the substep boxes and the other end would be placed in the second substep box;
the calculation block can be placed in either. Figure 8.2 shows a 2-level back to back system
distributed across two substep cores at the DC link. The time-steps for each substep network
must be the same and a compiler error will be generated if they are not. The substep
networks can be in the same subsystem or on separate subsystems (i.e. cross-chassis).
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Substep Tutorial
Figure 8.2: 2-Level Back To Back VSC On Two Substep Cores
Signals generated inside a substep box can be used in the mainstep environment or in other
substep boxes. Although calculated at each substep, this transfer of signal out from a substep
box happens every mainstep. In applications requiring this transfer to happen at every
susbtep time‐step, users can use the “High Resolution Transfer” component, shown in Figure
8.3.
Figure 8.3: HD Transfer Component
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Substep Tutorial
9 SUBSTEP I/O
Sending and receiving signals into and out of the substep simulation is straight forward and
identical to how I/O is used in the mainstep. The signals will be input/output once per
substep time-step. The I/O components from the Controls Library, shown in Figure 9.1, are
used for substep I/O. These are the same I/O components that are used in the mainstep.
Figure 9.1: I/O Components From Controls Library Are Used For Substep I/O
A common example of using I/O in the substep environment is for control-hardware-in-the-

loop (CHIL) testing of a physical controller for a power electronic converter which is
simulated in the RTDS, as shown in Figure 9.2.
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Substep Tutorial
Figure 9.2: CHIL Test Of An External Controller With The RTDS Simulator
Section 9.1 outlines the procedure for using I/O in the substep environment.
9.1 OVERVIEW OF STEPS TO FOLLOW WHEN USING I/O:
All mainstep IO components can be used directly in Substep environment with Substep
sampling rate
The general steps for using I/O in the substep environment are outlined below.
1. Update configuration file. Select “SAVE” once the configuration file is updated.
2. If the required I/O cards are not in the desired locations, the user will need to
manually move I/O cards to the desired location. It is important to make sure the I/O
power is turned off before cards are physically moved. Please refer to the I/O manual
for more details on the proper procedure. Repeat step 1.
From the configuration file, note down the rack number, and port number. Check the seven
segment display on the I/O card to determine the I/O card number for each I/O card that is
being used in the simulation case. Determine which channels should be used to connect to
the external device:
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GTAO GTDI ….
Chassis/Rack #
Port #
I/O Card #
Channels
3. Inside the draft case, ensure that the correct configuration for the I/O cards are set
(as noted in step 3). If an incorrect configuration is specified, the user will receive an
error message when the draft case is compiled.
The GTAO and GTAI require scaling factors. The GTAO output and GTAI inputs must be a
voltage between ±10Vpk. The scaling factor in the GTAO is used to scale the signal to this
specified range (±10Vpk). The scaling factor in the GTAI is used to scale the input (±10Vpk)
to the desired value to be used in RSCAD.
Figure 9.3 shows how the scaling factors (SC) are used to scale the voltages. Please refer to
the GTAO and GTAI chapter of the hardware manual for more information.
(a) GTAO scaling factor
(b) GTAI scaling factor

Figure 9.3: GTAO And GTAI Scaling Factors
NOTE: It is good practice to make sure that the I/O cards you plan to use are not already
connected to other devices before running the case.
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1. Before connecting a GTAO output to physical devices, such as a controller, measure

the output voltage from the GTAO and verify that it is what you expect. Scaling
factors might need to be updated.
2. Once the I/O cards are set up as desired, the external equipment can be tested in
real time with the RTDS Simulator.
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10 [1]
REFERENCES
T. Maguire and J. Giesbrecht, "Small Time-step (≤2us) VSC Model for the Real Time
Digital Simulator," 2005 International Conference on Power Systems Transients,
Montreal, 2005, pp. 1-6.
[2] Prabha Kundur. Power System Stability and Control. Toronto. McGraw-Hill, Inc. 1994
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Time-Step
Tutorial
20210715
Table of Contents
1 SMALL TIME-STEP TUTORIAL..................................................................................................................... 3
1.1 INTRODUCTION ................................................................................................................................. 3
2 SMALL TIME-STEP SIMULATION BASICS .................................................................................................... 4
2.1 THE CHALLENGE ................................................................................................................................ 6
2.2 THE SOLUTION................................................................................................................................... 6
3 SIMPLE VOLTAGE RECTIFIER ...................................................................................................................... 9
3.1 VSC BRIDGE BOX................................................................................................................................ 9
3.2 VOLTAGE RECTIFIER CIRCUIT........................................................................................................... 10
3.3 ALTERNATIVE APPROACHES ............................................................................................................ 14
3.3.1 DISCRETE SWITCHING ELEMENTS ........................................................................................... 14
3.3.2 TWO LEVEL VSC BRIDGE .......................................................................................................... 14
3.3.3 INTERFACED SIX PULSE BRIDGE............................................................................................... 15
4 SIMPLE STATCOM EXAMPLE ................................................................................................................... 17
4.1 STATCOM CIRCUIT ........................................................................................................................... 17
4.1.1 SOURCE.................................................................................................................................... 18
4.1.2 LOAD ........................................................................................................................................ 18
4.1.3 FILTER ...................................................................................................................................... 18
4.1.4 TRANSFORMER ........................................................................................................................ 20
4.1.5 SIX-PULSE BRIDGE ................................................................................................................... 20
4.1.6 DC BUS ..................................................................................................................................... 20
4.2 STATCOM CONTROLS ...................................................................................................................... 20
4.2.1 ACTIVE POWER REGULATOR ................................................................................................... 21
4.2.2 BUS VOLTAGE REGULATOR ..................................................................................................... 22
4.2.3 SIGNAL FILTERING ................................................................................................................... 24
4.2.4 SINUSOIDAL PULSE WIDTH MODULATION (SPWM) ............................................................... 25
4.2.5 MODULATION WAVEFORMS ................................................................................................... 25
4.2.6 TRIANGLE WAVEFORM ............................................................................................................ 26
4.2.7 PWM COMPARATOR ............................................................................................................... 28
4.3 RUNTIME INTERFACE ...................................................................................................................... 30
4.4 ADDITIONAL EXERCISE: MONITORING SMALL TIME-STEP SIGNALS IN HIGH DEFINITION .............. 32
4.4.1 SCOPE ...................................................................................................................................... 32
4.6 ADDITIONAL EXERCISE: CHANGE IN THE DC BUS ............................................................................ 35
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Tutorial: Small Time-Step
4.6.1 DC BUS REGULATOR (FORMERLY ACTIVE POWER REGULATOR) ............................................ 36

4.6.2 VOLTAGE REGULATOR ............................................................................................................. 37
5 SIMPLE PWM TUTORIAL .......................................................................................................................... 39
5.1 OVERVIEW ....................................................................................................................................... 39
5.2 STEP #1 ............................................................................................................................................ 39
5.3 STEP #2 ............................................................................................................................................ 42
5.4 STEP #3 ............................................................................................................................................ 44
5.5 STEP #4 (OPTIONAL) ........................................................................................................................ 46
6 INTERFACING LARGE AND SMALL TIME-STEP SIMULATIONS ................................................................. 47
6.1 INTERFACE TRANSFORMER ............................................................................................................. 49
7 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP TRANSMISSION LINES ................. 53
7.1 HARDWARE CONNECTIONS............................................................................................................. 53
7.2 SMALL TIME-STEP TRANSMISSION LINES ........................................................................................ 55
8 SMALL TIME-STEP IO ............................................................................................................................... 59
8.1 ANALOG OUTPUTS .......................................................................................................................... 59
8.1.1 FRONT PANEL AO .................................................................................................................... 59
8.1.2 GTAO ....................................................................................................................................... 60
8.2 DIGITAL INPUT ................................................................................................................................. 63
8.2.1 GTDI ......................................................................................................................................... 63
8.3 ANALOG INPUT ................................................................................................................................ 64
8.3.1 GTAI ......................................................................................................................................... 64
8.4 DIGITAL OUTPUT ............................................................................................................................. 66
8.4.1 GTDO ....................................................................................................................................... 66
9 SELECTING VALVE PARAMETERS ............................................................................................................. 67
9.1 STRATEGY FOR SELECTING VBLOCK AND ICONDUCT ................................................................................ 71
10 DISTRIBUTING PROCESSING LOAD OVER TWO PROCESSORS ............................................................. 72
11 REFERENCES ........................................................................................................................................ 74
2
1
1.1 INTRODUCTION
SMALL TIME-STEP TUTORIAL
Typical time-steps for EMTP type simulations are on the order of 50 microseconds. Such
time- steps, however, are not sufficiently small to allow for the accurate simulation of high
frequency switching circuits such as those used in PWM schemes. In order to model such
schemes a feature known as small time-step simulation was introduced into RSCAD. Small
time-step simulation uses several ‘shortcuts’ in order to reduce the time-step down to
somewhere in the neighborhood of 1.5 to 2.5 microseconds. The actual time-step is not
directly controlled by the user but is a function of the complexity of the circuit being
simulated. The aim of this tutorial is to familiarize the user with the small time-step
simulation feature of the RTDS Simulator.
This tutorial is broken up into several parts. In Section 2 some of the basic theory behind
small time-step simulation is provided. Next, some of the details involved in building a small
time-step case are shown; this is done primarily by means of example. First a simple voltage
rectifier is built in Section 3 and then a simplified STATCOM is assembled in Section 4. The
aim of Section 3 and Section 4 is to assist the reader in assembling a working simulation case.
Section 5 through Section 9 will introduce some more advanced topics. Section 5 details how
a small time-step simulation circuit can be interfaced with a large time-step circuit. Section
6 will explain how to increase the size of a circuit simulated using the small time-step
simulation facility. Section 7 deals with importing and exporting digital and analog signals
into and out of the simulation. Section 8 discusses strategies for how to go about selecting
the valve parameters. Finally, in Section 9, details are given on how to spread the processing
load of the small time-step simulation over multiple processors.
3
2 SMALL TIME-STEP SIMULATION BASICS

In order to understand small time-step simulation it is important to understand some
fundamentals about the core solution algorithm used by the RTDS Simulator. Consider the
simple circuit of Figure 2.1 (a) for a moment. It consists of a source and three series
connected conductances (g1, g2 and g3). If the source and g1 are converted to their Norton
equivalent the circuit can be redrawn as shown in the adjacent figure of 2.1B. The labels V1
and V2 are added to the circuit; our objective is to solve for these voltages.
(a) (b)
Figure 2.1: Simple Circuit used to Demonstrate RTDS Solution Algorithm (a) Simple Circuit (b)
Norton Equivalent
Kirchhoff’s Current Law (KCL) can be used to write the nodal equations at V1 and V2. The
results are shown in Equation 2-1 and Equation 2-2.
𝑉1 𝑔1 + (𝑉1 − 𝑉2 )𝑔2 = 𝑔1 𝑉(𝑡) Equation 2-1

𝑉2 𝑔3 + (𝑉2 − 𝑉1 )𝑔2 = 0 Equation 2-2
Equation 2-1 and Equation 2-2 can be re-written in matrix form as shown in Equation
2-3.
𝑔 +𝑔 −𝑔2 𝑉1 𝑔1 𝑉(𝑡) Equation 2-3

[ 1−𝑔 2 𝑔2 + 𝑔3 ] [𝑉2 ] = [ 0 ]
2
Solving for the node voltages V1 and V2 leads to Equation 2-4 or equivalently Equation
2-5.
−1
𝑉 𝑔 +𝑔 −𝑔 𝑔 𝑉(𝑡)
[ 1 ] = [ 1−𝑔 2 𝑔 + 2𝑔 ] [ 1 ] Equation 2-4
𝑉2 2 2 3 0
[𝑉] = [𝐺]−1 [𝐼] Equation 2-5
4
The voltages at both nodes can be calculated if the voltage source signal, V(t), along with the
conductances g1, g2 and g3 are known. Equation 2-5 is a very simplified summary of
calculations carried out by the RTDS Simulator. In the equations above, G is known as the
conductance matrix. In general, a circuit with N single phase nodes will lead to a conductance
matrix of N x N dimension.
Without proof it is stated that passive elements such as inductors and capacitors can be
modeled as current sources connect in parallel with conductances. Figure 2.2 shows the
equivalent circuits for inductors and capacitors.
(a) (b)
Figure 2.2: Equivalent Circuits for (a) Inductor and (b) Capacitor
Furthermore, complicated elements such as Transformers, Transmission lines and

Generators can also generally be modeled as current sources connected in parallel with a
conductance. Once all the elements in a circuit are converted to a parallel conductance and
current source, KCL can again be written for each of the nodes in the circuit and an equation
similar in form to that of Equation 2-5 can be written. This is the general approach that the
RTDS Simulator uses. The true complication comes in trying to accurately model the behavior
of physical devices by modeling them as a parallel connected current source and
conductance.
One of the primary uses of the RTDS Simulator is its ability to study the transient behavior
of power systems. It is important to understand how a power system responds when a
breaker opens/closes, when a fault occurs or is cleared or when a power electronic device
misfires. Fortunately, the framework developed above can easily accommodate simulation
of these conditions/scenarios.
Consider the circuit of Figure 2.3 (a) which contains two series connected resistances and a
switch which can open or close. A switch can be modeled fundamentally as a conductance
which is small when the switch is open and large when the switch is closed. Given this
realization the circuit of Figure 2.3 (a) can be rewritten as shown in Figure 2.3 (b). This circuit
is identical to the circuit developed in Figure 2.1 (a) thus the node voltages can be solved for
using Equation 2-5. The primary difference will be that the conductance matrix, G, will evolve
with time. When the switch is in an open state the conductance g3 will be small, conversely
when the switch is in a closed state g3 will be large. A time-varying conductance can just as
easily be used to model a fault, or a power electronic switch.
5
(a) (b)
Figure 2.3: Circuit Demonstrating the Modeling of Switches in Large Time-Step Simulations
2.1 THE CHALLENGE
Anytime the switching state of the circuit changes, the G-matrix changes. Whenever the G-
matrix changes, its inverse will also need to be recalculated. Unfortunately, the number of
operations needed to invert an N x N matrix increases exponentially with N. Currently the
effective inversion of a 66 node G matrix takes on the order of 50μsec. Given the real-time
constraint applied to the RTDS Simulator, it is not difficult to imagine that a 25-fold increase
in processing power would be needed in order to use the above described method to model
switches with the 2μsec time-step range necessary to accurately model some power
electronic circuits. This is the challenge that must be overcome in order to complete a real-
time electromagnetic simulation using a time-step on the order of 2μsec.
2.2 THE SOLUTION

Given the challenges listed above, an alternate method for modeling a switch is needed.
Instead of modeling an open circuit as a small conductance, it will be modeled as a series
connected resistor and capacitor. Also, instead of modeling a short circuit as a large
conductance, it will be modeled as an inductor.
(a) (b)
Figure 2.4: Equivalent Circuits used to Represent (a) Short Circuit and (b) Open Circuit in the
Small-Time-step Simulation.
6
It is possible, again without proof, to simplify the circuits chosen to represent a short circuit
and an open circuit into equivalent parallel connected current sources and conductances.
Figure 2.4 (a) and Figure 2.4 (b) show the small time-step representations for a short circuit
and an open circuit respectively. These representations can easily be incorporated into the
above discussed formulation used to solve for node voltages. Changing the state of a switch
now involves two possible changes. First gsc is changed to goc or vice versa; secondly, IHsc is
changed to IHoc or vice versa. Up to this point one approximation of an open circuit and
another for a short circuit has been proposed but neither the validity nor the advantages of
such approximations have been discussed.
The validity of the approximation is the most pressing concern; the values of R and C must
be selected so that together they represent a fairly large impedance across the system
bandwidth. Similarly, L must be selected so that it represents a fairly small impedance across
the system. If these criteria are not met then the chosen approximations for a short circuit
and an open circuit are invalid and there is no point in continuing with this approach.
Fortunately, it is possible to choose R, C and L to meet these constraints.
In addition to being selected so that the constraints above are met, the parameters R, L and
C can also be chosen in such a way that gsc and goc are equal. If gsc equals goc then the
conductance matrix of the system being simulated will not change when the state of a switch
changes. This in turn implies that the conductance matrix remains constant throughout the
entire simulation and that it does not need to be re-inverted when a switching event occurs.
Only the values of IHsc and IHoc need to be recalculated. This approach results in huge
computational savings and is the primary reason the time-step can be reduced to within the
1.5 – 2.5μsec range.
There are, however, disadvantages to this approach. The problem lies in the fact that open
and short circuits are being represented using capacitors and inductors, both energy storage
devices. In either of the two states a small amount of energy from the system will be stored,
something which does not occur when using a pure conductance to represent the open and
short-circuited conditions. Upon the occurrence of a switching event one circuit
representation is abruptly changed to the other and in doing this, the small amount of
energy that was stored in the previous switching state is effectively discarded. This is an
artificial energy loss that is introduced by the modeling method and the total energy loss
increases as the number of switching events increases. Switches modeled in the above
described manner can be operated up to about 3 kHz without problem but beyond this
frequency the artificial losses become unrealistic. Some of the small time-step models can
be switched at increased rates of up to 12 kHz but these switches have been modeled using
the traditional method and are mathematically decoupled from the small time-step G-
matrix. This will be discussed later in this tutorial.
What has been presented so far was intended to give the user a basic understanding of the
fundamentals of small time-step simulation; further details about the above described
7
approaches can be found in [1]. In the next section, a simple voltage rectifier circuit will be
assembled using the RTDS Simulator’s small time-step simulation facilities.
8
3 SIMPLE VOLTAGE RECTIFIER

In this section a simple voltage rectifier will be assembled and simulated using the small
time- step functionality of the RTDS Simulator. The topology of the circuit will be similar to
that shown in Figure 3.1. Since switching will only occur at power system frequency this is
not an example of the type of circuit that would typically need to be studied using small
time-step simulations, but construction of this circuit is instructive nevertheless and serves
as a good starting point.
Figure 3.1: Simple Voltage Rectifier Circuit to be Assembled
3.1 VSC BRIDGE BOX

In order to build a small time-step simulation case the first thing that must be done is to add
a special hierarchy box into the DRAFT case. This special hierarchy box is known as a VSC
Bridge Box and appears as shown in Figure 3.2. Any circuit which is to be simulated using a
small time- step must be assembled inside a VSC Bridge Box. In general, only small time-step
components can be placed inside the VSC bridge box; large time-step component will not
work using a small time-step. The Master library contains a tab labelled Small_dt which
contains a collection of small time-step models. Although control compiler components can
be placed within a VSC bridge box without generating a compile error, they are nonetheless
simulated using the large time-step.
9
Figure 3.2: Small Time-Step Bridge Box Icon
Double-clicking on a VSC bridge box allows its contents to be edited in the same manner that
the contents of a hierarchy box can be modified. Right-clicking on the VSC bridge box and
selecting Edit->Parameters opens the parameter menu; Figure 3.3 shows the parameter
menu for the small time-step bridge box. Some of these parameters will be described later
in this tutorial but additional details can be found in the ‘VSC Small Time-Step Modelling’
Chapter of the manual.
Figure 3.3: rtds_vsc_BRIDGE_BOX Parameter Menu
3.2 VOLTAGE RECTIFIER CIRCUIT

Inside the VSC bridge box the circuit of Figure 3.4 should be constructed. It is a simple voltage
rectifier where the diode bridge has been replaced by a GTO bridge with anti-parallel diodes.
If firing pulses for the GTOs are not provided, then the GTO bridge effectively becomes a
diode bridge. The load on the DC bus will be a 100Ω resistance and the source impedance
will be a 1Ω resistance. The six GTOs with anti-parallel diodes are a single component named
rtds_vsc_PH3LEV2 which can be found in the small time-step library in the ‘2 & 3 LEVEL VSC’
box.
10
Figure 3.4: DRAFT Model of Rectifier Circuit
This component is highly customizable and can be used to model R, L, C, RL, RC, RRL, and
high pass filter branches. The number of branches per component can be varied between
one and three and they can be positioned either inline or in parallel. It is also possible to
include a controlled voltage source in the branch by setting the vsrc parameter to Yes as
shown in Figure 3.5 The shape and magnitude of the voltages follow that of the controls
compiler signals referenced under the NAMES FOR REAL/INT VOLTAGE SOURCE INPUTS
tab.
Figure 3.5: Adding Voltage Sources to a Branch Component
11
The AC side of the bridge has a three-phase controlled voltage source so some external
signals from the controls compiler must be referenced. The control logic shown in Figure 3.6
will generate a set of three phase signals which are assigned to SRCa, SRCb, SRCc. The source
magnitude is 11.5 kV LL rms.
Figure 3.6: Control Signals which Generate the AC Voltage Signal
Five nodes are included in the circuit; three on the AC side and one at each rail of the DC
side. It should be noted that small time-step nodes differ from large time-step nodes in that
their values are only monitored if explicitly requested. Only the node voltages of interest
should be monitored; for this example, the voltages at all the nodes should be monitored.
In order to achieve rectifier operation, no firing pulses are provided to the GTOs/IGBTs
connected in anti-parallel with the diodes. This can be done by changing the source of the
firing pulses of the bridge to CC_WORD, naming the control signal which serves as the control
word for the bridge (FPWORD1 in this case as seen in Figure 3.7) and assigning zero to that
control word by using a wire label and an integer constant. The least significant bit of the
control word (bit 0) controls switch 1, the second least significant bit (bit 1) controls switch
2 and so on. Figure 3.7 shows the menu items of the bridge which must be modified.
12
Figure 3.7: Change the Source of the Firing Pulse so that it Originates from the Control Compiler
When the case is compiled the warning listed below might appear. This warning is to inform
the user that there might be a problem with their control circuitry because they are trying
to control the switching of the bridge elements use a gating signal that originates from the
large time-step. This fundamentally undermines the advantages of small time-step
simulation. For the moment this warning can be safely ignored because the GTOs/IGBTs are
not being switched during the simulation and there is no need for precise timing of the gating
signals. This issue will be revisited later in the tutorial when a PWM scheme will be
implemented.
WARNING: This message is from a small time-step

VSC component of type: ph3lev2
and of component name: BRDG1
located on the first processor
of a VSC bridge named: VB1
in subsystem number: 1.
The firing pulse word input "FPWORD1" for the VSC
component is not locally produced on the processor but
comes from the large time-step backplane.
Consequently, firing pulse word input
changes only once in a large time-step.
The firing could have better resolution if
it was created on the local processor.
Noted in fcn: rnet_ph3lev2_code
Warning issued from <rnet_ph3lev2_code>
Once the case has been successfully compiled, RUNTIME can be launched and the DC and
AC side voltage signals can be plotted. Figure 3.8 shows plots of the results that should be
obtained. The signal VP, as expected, is the maximum value of the signals VA, VB and VC;
conversely the signal VN is the minimum amongst them.
13
Figure 3.8: RUNTIME Plot of the AC and DC Side Signals from the Voltage Rectifier Circuit
3.3 ALTERNATIVE APPROACHES

There are a number of alternative approaches to building the diode rectifier in this section;
some of these are briefly described below. Each method has its own distinct advantages and
disadvantages.
3.3.1 DISCRETE SWITCHING ELEMENTS
The small time-step component rtds_vsc_VALVE1 can be used to build the diode bridge. The
vtype parameter can be modified so that several types of switching elements can be
represented. Among them are a GTO, a GTO with an anti-parallel diode, a diode, a thyristor
and a thyristor with an anti-parallel diode. To build the diode rectifier of this section, each
switching element would be a separate component. Using this approach, any arbitrary circuit
topology can be implemented and is particularly useful when circuits having non-standard
topology must be simulated. Figure 3.9 shows the implementation of a diode rectifier using
this approach.
3.3.2 TWO LEVEL VSC BRIDGE
Certain common circuit topologies have been implemented as single components. The
rtds_vsc_PH3LEV2 component, for instance, consists of six GTOs/IGBTs with anti-parallel
diodes and is useful for modeling two-level converters. In this section this component was
used to build a diode rectifier by simply not providing any gating signals to the GTOs/IGBTs.
Figure 3.10 shows the implementation of diode rectifier using this approach. There is
essentially no difference in how this circuit functions when compared to the first
implementation using discrete switching elements. There are two advantages of using this
model, however, (1) the circuit is more easily assembled and (2) foreknowledge of the
topology allowed the component to be coded in a more efficient manner. The benefit of
14
these added efficiencies is that the simulation time-step might be reduced or the number of
components that can be simulated might be increased. Another useful topology in the library
is a single leg of a three-level converter, rtds_vsc_PH1LEV3.
3.3.3 INTERFACED SIX PULSE BRIDGE

A third option in assembling the simple diode rectifier is to use the rtds_vsc_LEV2
component. Figure 3.11 shows the implementation of diode rectifier using this component.
This third implementation of the diode rectifier is fundamentally different from the two
previous implementations. The bridge in the rtds_vsc_LEV2 component is actually interfaced
with the small time-step network solution using a transmission line having a wave
propagation delay of one small time-step. The presence of this short t-line implies that what
occurs at one end of the transmission line does not affect what occurs at the other end for
at least one small time-step. The valve group is thus effectively decoupled from the small
time-step network solution during any single small time-step. This is the same principle used
to divide a large simulation across multiple racks. Instead of modeling the VSC switches in a
network solution using the methods introduced in Section 2, an open switch is a small
conductance and closed switch is a large conductance. All possible conductance matrices for
the circuit are pre-calculated and stored in memory; they are then referenced as needed.
The anomalous power loses previously described do not occur and higher switching
frequencies can be supported. The disadvantage, of course, is that transmission lines which
do not exist in the real system have to been introduced into the circuit. These transmission
lines can lead to reflections and other effects, and thus this component must be applied with
care.
Figure 3.9: Alternative Construction for the Diode Rectifier Circuit using Discrete Valves
15
Figure 3.10: Alternative Construction for the Diode Rectifier Circuit using Valve Bridge
Figure 3.11: Alternative Construction for the Diode Rectifier using Interfaced Valve Bridge
16
4 SIMPLE STATCOM EXAMPLE

The small time-step capabilities of the RTDS Simulator are often used to model high
frequency switching circuits such as those used in PWM schemes. In this next section the
foundations established in the previous section are built upon and a simple STATCOM will
be assembled. A STATCOM controls the flow of reactive power into a bus and can thus be
used to regulate the voltage at that bus. Figure 4.1 gives details about the topology of the
circuit that will be constructed; it consists of an infinite bus feeding a load that can be
switched in or out of service by controlling a breaker. The system side is 93kV while the
voltage on the converter side of the transformer is 11.5kV. The base power for the system is
100 MVA. A significant drop in the voltage at the load bus will occur when the load is
connected; the purpose of the STATCOM is to correct this voltage drop.
Figure 4.1: Overview of the Simplified STATCOM Case being Assembled
The circuit of Figure 4.1 differs from a practical STATCOM in that ideal voltage sources are
used for the DC bus. Normally large capacitors are used on the DC side of the STATCOM, but
the use of ideal sources will significantly ease the construction of a control system since the
capacitor voltage will not need to be actively regulated. In a practical STATCOM the concepts
of instantaneous reactive power are deployed in order to achieve fast, sub-cycle control of
the bus voltage. Here, a simplified approach will be adopted where conventionally defined
reactive power will be regulated.
4.1 STATCOM CIRCUIT

The small time-step circuit to be constructed is given in Figure 4.2. The system in 93kV on
the high voltage side and 11.5kV on the low voltage side; the base MVA is 100. All
17
components must be placed inside a small time-step bridge box. Brief descriptions of each
of the important parts of this circuit are provided in Figure 4.2.
Figure 4.2: DRAFT Model of Simplified STATCOM
4.1.1 SOURCE
A controllable source is used to model an infinite bus having a rated voltage of 93 kV LL RMS.
The source impedance is 0.019 + j0.064 pu (Rs = 1.64Ω and Xs = 5.54 Ω at a nominal
frequency of 60Hz). The control signals for the source originate from the large time-step and
the circuit shown in Figure 4.3 can be used to provide these signals.
Figure 4.3: Signal Source for Infinite Bus
4.1.2 LOAD
The load is 120 MVA with a power factor of 0.9322 (Rl = 67.25 Ω and Xl = 26.11 Ω at a nominal
frequency of 60Hz). The load can be switched in and out of the circuit using the three-phase
circuit breaker component rtds_vsc_BKRN3 which is modeled using the same method as
other switches in the small time-step. When the load is switched in, the voltage at Bus 2 is
expected to dip and it is this dip that the simplified STATCOM should regulate.
4.1.3 FILTER
The elements found between Buses 3 and 4 together make up a filter; it consists of reactors
and shunt high-pass filter branches. The high-pass filter can be created by using the
rtds_vsc_BRC3 component and selecting HIPASS as the Branch Type. In this tutorial a PWM
scheme is used where switching occurs at a frequency of 21 times the fundamental or 1260
Hz. Current and voltage harmonics will be generated in the vicinity of this switching
18
frequency and the shunt filter branch will behave as an effective short circuit at these
harmonic frequencies and effectively ground Bus 3 to minimize their impact on the network.
The value for the parameters of the filter are Lreactor=0.006686H, Rshunt=0.6295Ω,
Cshunt=200μF and Lshunt=0.000079517H. These parameter choices lead to the bode plot of
Figure 4.4 for the impedance of the shunt branch. The input impedance of the shunt branch
is ~0.4466Ω at 1260 Hz which is small relative to the impedance offered by the transformer
and reactor at that frequency. At the nominal frequency of 60Hz the input impedance
provided by the shunt filter branch is fairly large and has a value of 13.23 Ω, approximately
10x the base impedance. This implies that the filter will have a minimal impact on the circuit
at the nominal frequency.
Figure 4.4: Bode Plot of the Magnitude of the Shunt Branch Impedance
The size of the reactor was selected almost arbitrarily and the design rules listed below were
used to select the parameters of the shunt high-pass filter branches. Justification for the
design approach is beyond the scope of this tutorial.
1. Select the capacitor so that at the nominal frequency of 60Hz, the shunt filter branch
behaves like an open circuit. The impedance of the capacitor can be arbitrarily
chosen as 10 pu at 60Hz.
11.52
𝑍𝑏𝑎𝑠𝑒 𝐿𝑉 = = 1.322Ω Equation 4-1
100
At the nominal frequency of 60 Hz, let 𝑍𝐶𝐴𝑃 = 10 𝑝𝑢 = 1.322Ω𝑥10 = 13.22Ω
1 1
𝐶= = ~200𝜇𝐹 Equation 4-2
𝜔𝑍𝐶𝐴𝑃 376.991𝑥13.22
19
2. Neglect the parallel resistor and assume a series LC circuit. Using the capacitance
calculated in step (A) select the inductance such that a resonance occurs at the
modulation frequency and the impedance of the capacitor and inductor cancel each
other to provide a path to ground. The resonant frequency of a series LC circuit is
1
𝜔= and the resonance should occur at 1260 Hz.
√𝐿𝐶
1 1 Equation 4-3
𝐿= = = 7.9517𝑒 −5 𝐻
𝜔 2 𝐶 (2𝜋𝑥1260)2 𝑥200.65𝑒 −5
3. Select R such that its impedance is equal to that of the parallel connected inductance
at the modulating frequency.
𝑅 = 𝜔𝐿 = (2𝜋𝑥1260)𝑥7.9517𝑒 −5 = 0.62952Ω Equation 4-4
4.1.4 TRANSFORMER
A transformer is typically used to connect the STATCOM and the filters to the bus where
voltage regulation is needed. The impedance is selected as purely reactive and is Xleak = 0.18
pu (15.568 Ω at 60Hz on the primary side). The small time-step transformer
rtds_vsc_TRFS1PH should be used; it is an ideal transformer. The three-phase transformer
should be implemented using three single phase units, each rated at 33.3 MVA. This
component will initially be one single phase unit, but within the configuration menu this can
be changed to three single phase units.
4.1.5 SIX-PULSE BRIDGE

The six-pulse bridge shown uses the rtds_vsc_PH3LEV2 component. The bridge could
alternately be constructed using the rtds_vsc_LEV2 component or several rtds_vsc_VALVE1
components as was described earlier in this tutorial. The firing pulses for these components
will be provided by the rtds_vsc_3LGFIR component which will need to be supported by a
rtds_vsc_TRIWAV3 component and a large time-step control system which will be described
shortly.
4.1.6 DC BUS
The DC bus for the STATCOM will simply be implemented as an ideal source. As discussed
above, this will lead to simplification of the control system. The source impedance will be
selected as purely resistive and as small as possible. The DC bus should be set to 60kV across
the positive and negative poles. (+30kV for the positive pole and -30kV for the negative pole).
4.2 STATCOM CONTROLS

Two regulators are used in this tutorial; the first will control the voltage magnitude at bus 2,
the second will regulate the real power flow. The theoretical basis for our control is derived
20
from Equation 4-5 and Equation 4-6. These two equations describe the physical system that
is to be controlled; specifically, they describe the real and reactive power injected into bus
2. The impedance found between bus 2 and bus 3 is assumed to be purely reactive and δ is
the angle of the voltage at Bus 3 relative to that at Bus 2.
𝑉3 𝑉2 Equation 4-5
𝑃𝑖𝑛𝑗 = sin 𝛿
𝑋
𝑉3 𝑉2 cos 𝛿 − 𝑉22 Equation 4-6
𝑄𝑖𝑛𝑗 =
𝑋
Given that there are no capacitor voltages which need to be actively maintained, the power
flowing out of the STATCOM will simply be regulated to zero. This closely approximates a
real STATCOM where the real power consumption is generally quite small. The voltage at
bus 2 will be regulated to the nominal value of 1.0 per unit.
It is well documented that the power flowing between buses 2 and 3 is strongly correlated
to δ. Similarly, the reactive power flow is a strong function of the voltage magnitudes of the
buses. Given such strong correlations, δ will be used to control P32, and V3 will be used to
control Q32. The mutual effects of δ on Q32 and of V3 on P32 are effectively ignored but good
control should be achievable.
4.2.1 ACTIVE POWER REGULATOR

If δ is limited to +/- 90 degrees then a simple relationship exists between the electric power
transfer, Pinj, and δ. If δ increases, then so will P. Such a relationship is ideally suited for
control using the PI controller of Figure 4.5.
Figure 4.5: Block Diagram of Active Power Regulator
Failure to limit the output of the PI controller is a failure to consider the non-linear nature
of the underlying process and could cause the controller to fail. Consider the case where P ref
𝑉𝑉
is set to a value above the theoretical limit of the process, 3𝑋 2. The simple Pi controller, in
an attempt to regulate the power flow, would cause δ to increase continually which in turn
would cause Pmeas to oscillate.
Figure 4.6 shows the implementation of the Active Power Regulator for this example. As
mentioned above, Pref will be fixed to zero. The proportional gain is selected as G = 0.01 and
the integrator time constant is set to T = 0.1s. These values are selected experimentally and
21
have not been optimized in any way. In order to prevent windup problems, the integrator is
reset when the controller is operating in the open loop. For this tutorial, the controller will
only be open looped if firing of the bridge’s valves is blocked. The integrators are also reset
for the first second after the simulation is started. This is necessary to make certain that the
controllers respond quickly after the simulation’s start-up electrical transients end. Figure
4.7 shows the integrator reset logic. The reset logic is not a robust or comprehensive solution
but it will work for this example. The same reset logic is used to reset all the integrators in
the STATCOM’s controller.
Figure 4.6: Implementation of Active Power Regulator
Figure 4.7: Implementation of Integrator Reset Logic
4.2.2 BUS VOLTAGE REGULATOR

The objective of the voltage regulator is to regulate the voltage at bus 2 to some pre-defined
value. Fortunately, the voltage at bus 2 can be fairly easily regulated by controlling the
amount of reactive power injected. If the reactive power injected into bus 2 increases, then
so will the voltage at the bus. The PI controller below can be used to control such a system.
22
Figure 4.8: Block Diagram of Bus 2 Voltage Regulator
The next step involves determining how to go about controlling the reactive power injecting
into bus 2; this will have to be done indirectly. By inspection of Equation 4-6, a simple
relationship between Qinj and V3 can be found. Assuming that δ has been limited to +/- 90
degrees then as V3 increases, so will Qinj. Like before, this simple relationship is ideally suited
to be controlled by a PI controller.
Figure 4.9: Block Diagram of Reactive Power Regulator
The PI regulator shown in Figure 4.9 has been designed as though the voltage at bus 3 can
be directly controlled. This is in fact approximately true; the voltage at bus 3 can be
controlled by modulation of the fixed DC bus voltage. With the sinusoidal PWM scheme that
will be deployed, it can be shown that the magnitude of the filtered signal that would ideally
appear at bus 3 will be 𝑚𝑎𝑉𝑆𝑅𝐶 [2] . Here VSRC is the one half of the fixed DC bus voltage and
ma is the PWM’s amplitude modulation ratio. Thus, the amplitude of the filtered voltage
found at bus 3 can be controlled directly through manipulation of the amplitude modulation
ratio.
Cascading the two PI controllers above allows the control of the voltage at bus 2 indirectly
by changing the amplitude modulation ratio. The complete controller is given in Figure 4.10.
Figure 4.10: Complete Block Diagram of Voltage Regulator
Figure 4.11 shows the implementation of the voltage regulator for this example. Like with
the Real Power Regulator, provisions for resetting the integrators during simulation start-up
and when operating in the open loop are included. The first PI controller has a proportional
23
gain of G=1000 and an integrator time constant of T = 0.0005s. The second PI controller has
a proportional gain of G = 0.005 and an integrator time constant of T = 40. These parameters
were also chosen through trial and error. Furthermore, a limiter is added so that the
amplitude modulation ratio is kept in the range of zero and one in order to avoid over-
modulation.
Figure 4.11: Implementation of the Bus Voltage Regulator
4.2.3 SIGNAL FILTERING

In order to provide stable results, the measured signals used by the voltage regulator and
the active power regulator are first passed through filters; simple real-pole filters are used.
The gains for all the filters are set to one. The time constants for P and Q filters are set to T
= 0.2s. The time constant for voltage filter is also set to T = 0.2s. Again, these parameters are
selected heuristically. The filters can be seen in Figure 4.12. The current values, CRT1, CRT2,
and CRT3, are the input currents into winding 1 of the transformer.
Figure 4.12: Regulator Input Signal Measurement and Filtering
24
4.2.4 SINUSOIDAL PULSE WIDTH MODULATION (SPWM)

Two separate regulators have been designed whose outputs define the amplitude and phase
of the voltage that should appear at bus 3 in order to achieve the dual design objectives of
regulating the bus 2 voltage and regulating the active power drawn by the STATCOM. The
next step is to generate this desired voltage. Sinusoidal PWM (SPWM) is used to achieve this
objective.
Consider the circuit of Figure 4.13 (A) which shows one leg of the bridge that has been
created in this tutorial example. In a standard SPWM scheme a sinusoidal modulation signal
is compared with a high frequency triangle wave as demonstrated in Figure 4.13 (B). When
the value of the triangle wave exceeds that of the modulation signal then switch S1 will be
turned off. Conversely, when the amplitude of the triangle wave is less than that of the
modulation waveform then switch S1 will be turned on. The switch S2 will be controlled in a
Figure 4.13: Sinusoidal Pulse Width Modulation Basics
The signal Vout from the circuit will be a switched waveform similar to that shown in Figure
4.13 (C). It can be shown that if the amplitudes of the triangle wave and sinusoidal
modulation signal are the same, then the amplitude of the fundamental component of V out
will be equal to the DC rail voltage, VDC. Similar principles of operation apply to all three legs
of the bridge.
4.2.5 MODULATION WAVEFORMS

The outputs of the active power and bus voltage regulators designed above are δ and m
respectively. Both of the signals are used in the generation of the modulation waveforms of
25
the PWM scheme that will be deployed. The control circuit used to generate the modulation
signals is shown in Figure 4.14; the frequency is fixed at 60Hz.
Figure 4.14: Control Circuit to Generate Modulation Waveforms for Sinusoidal PWM
4.2.6 TRIANGLE WAVEFORM

In order to implement SPWM, a high frequency triangle wave needs to be compared to the
modulation signals. The small time-step Triangle Wave Generator Component
(rtds_vsc_TRIWAV3) will be used to generate this triangle wave. The triangle wave is
generated within the small time-step simulation because a high-resolution signal is needed
in order for the switching instants to be calculated with precision.
In practice, the frequency of the triangle wave is commonly an integer multiple of the
fundamental frequency. Since the fundamental frequency can drift in a real system, the
small time-step triangle wave generator was designed to accept inputs from a large time-
step controls circuit which can track such drift. The circuit of Figure 4.15 is one such circuit
that can be quite useful for SPWM applications. A three-phase signal can be input into a PLL
whose output is the phase and frequency of that three-phase signal. Multiplying the output
frequency by the SPWM’s frequency modulation factor, mf, yields a frequency signal for a
triangle wave. Multiplying the phase signal by mf and fixing it so that is lies between 0 and
2π yields the associated phase signal for the triangle wave.
26
Figure 4.15: Generation of Support Signals for Small Time-Step Triangle Wave Generator
Figure 4.16 further illustrates the generation of the triangle wave’s phase signal assuming
mf = 4. The output of the PLL is multiplied by mf = 4 and the result is then fixed so that it lies
between the range of 0 and 2π. Notice that result is a phase signal appropriate for a triangle
wave having frequency mf times that of the original signal.
Figure 4.16: Generation of the Triangle Wave’s Phase Signal
It was stated earlier that a high-resolution triangle wave is needed in order to precisely
determine switching instants. The small time-step component rtds_vsc_TRIWAV3 uses the
phase and frequency information generated by the large time-step control circuit of Figure
4.15 to generate that high-resolution triangle wave in the small time-step. This is done
primarily through extrapolation as well as some boundary wrapping. Every small time-step
the incremental phase, θ’, can generally be calculated according to the equation θ’ = θ0 + ωt
and based on the calculated value, the proper point on a triangle wave can be fairly easily
found using a lookup table and/or by simple range checking. Figure 4.17 illustrates this
concept.
27
Figure 4.17: Extrapolated θ’ used to get a Value for the Triangle Wave
Some of the default parameters in the rtds_vsc_TRIWAV3 component will need to be

changed. The signal label names assigned to the triangle wave phase and frequency outputs
must be specified inside the rtds_vsc_TRIWAV3 component. Only a single triangle wave is
needed in this example and its peak-to-peak magnitude will be set to 2.0 with an offset of
0.0; this will produce a triangle wave that oscillates between ±1.0. A name must be assigned
to the triangle wave signal that will be output from the component so that it can be
referenced by the small time-step comparator that will be described next. Finally, the
triangle wave should explicitly be targeted for monitoring during RUNTIME so that the
performance of the PWM scheme can be evaluated. The user is encouraged to consult
documentation regarding the additional capabilities of the triangle wave generator.
4.2.7 PWM COMPARATOR

At this stage both a triangle wave and the desired modulation signals have been generated.
What remains to be done is a comparison of these signals in order to generate the required
firing pulses. This comparison must be done in the small time-step simulation in order to
accurately determine the switching instances. The rtds_vsc_3LGFIR component is used in
order to do the comparison. A single component is capable of doing the three comparisons
needed for the three-phase system.
Several inputs must be provided to this component. These include the names of the triangle
wave and modulation signals as well as a de-block signal. The rtds_vsc_3LGFIR component
gives the user complete freedom to specify how the firing pulse word used to control valve
firing is generated. Each of the component’s three comparators makes one of two possible
contributions to the final firing pulse word; one for when its modulation signal is greater
than or equal to the triangle wave and another for when its modulation signal is less than
the triangle wave. The outputs from each of the comparators are then bitwise ORed
together. The result is then ANDed with a de-block signal. The equation for the output of the
firing pulse generator is given in Equation 4-7 where cmp1t, cmp2b, cmp1t, cmp2b, cmp3t,
cmp3b and dblknm are all parameters of the rtds_vsc_3LGFIR component.
28
𝑓𝑝𝑜𝑢𝑡 = [(𝑐𝑚𝑝1𝑡||𝑐𝑚𝑝1𝑏)||(𝑐𝑚𝑝2𝑡||𝑐𝑚𝑝2𝑏)||(𝑐𝑚𝑝3𝑡||𝑐𝑚𝑝3𝑏)]&&𝑑𝑏𝑙𝑘𝑛𝑚 Equation 4-7
For this tutorial the end objective is to control the valve bridge of the rtds_vsc_PH3LEV2
component. This valve bridge component is designed in such a fashion that each valve is
controlled by a different bit of a firing word which is referenced as a parameter. Valve 1 is
controlled by bit 1, valve 2 by bit 2, valve 3 by bit 3 and so forth. If the bit associated with
any of the valves is one then the valve is conducting, if it is zero then the valve is blocking.
Assume that the bridge receives its firing pulse input word from the rtds_vsc_3LGFIR
component and that the contributions from each of its three comparators are left with their
default values which are listed in Table 4-I. Each comparator can make one of two possible
contributions to the firing pulse word depending on how the triangle wave and its
modulation signal compare. Notice that with the default contributions valves 1 and 2, valves
3 and 4 and valves 5 and 6 will always be fired in a complementary fashion as needed. The
contributions are also such that comparator 1 affects only bits 1 and 2, comparator 2 affects
only bits 3 and 4 and comparator 3 affects only bits 5 and 6. The implication of this is that
the contributions from all three comparators can be ORed together to form a single firing
pulse input word without affecting each other. This firing pulse input word is then ANDed
with a de-block signal before being passed to the valve bridge.
Table 4-I: Comparator Contributions to Firing Pulse Word

Contribution Contribution
Comparator Condition
(Decimal) (Binary)
Modulation
Wave#1≥Triangle 1 00 00 01
Wave
1
Modulation
Wave#1<Triangle 2 00 00 10
Wave
Modulation
Wave
2
Modulation
Wave
Modulation
Wave
3
Modulation
Wave
29
Although the component is flexible enough to block only selected valves, for this example all
valves are either blocked or de-blocked. Adding a simple switch that outputs an integer value
of 63 when de-blocked (ON state) and 0 when blocked (OFF state) will achieve the desired
objective.
4.3 RUNTIME INTERFACE

Create a RUNTIME interface similar to that shown in Figure 4.18. If the STATCOM is blocked,
then the voltage at bus 2 should drop significantly when the load is connected. If the
STATCOM is de- blocked the voltage at bus 2 should be regulated to around 1pu regardless
of whether the load is connected or not.
30
20210715
Figure 4.18: RUNTIME Interface for Simple STATCOM Example
31
4.4 ADDITIONAL EXERCISE: MONITORING SMALL TIME-STEP SIGNALS IN HIGH DEFINITION

When viewing a small time-step signal in RUNTIME the signal is only plotted each large time-
step by default and can thus appear distorted. In some cases, the full signal resolution may
be desired in RUNTIME.
In the previous case, TWAVEA was plotted over top MOD1WAV1. Zooming in on TWAVEA
shows that the peaks of the signal appear distorted, as in Figure 4.19. However, TWAVEA is
a very accurate triangle wave and simply has higher resolution than the plot displays.
Figure 4.19: Small Time-Step TWAVEA Signal Plotted against Large Time-Step Signal
4.4.1 SCOPE
We cannot continuously plot small time-step signals in RUNTIME because of the large
number of data points required. We therefore use a SCOPE component (rtds_vsc_SCOPE1)
to allow portions of a small time-step signal to be plotted in RUNTIME.
In DRAFT, place this component into the small time-step bridge box and edit the parameters
as follows. Enable monitoring of channel 1 and scope time signal output (mon1 and mon7).
Set the number of words to capture per channel to 11000 (limit of 20000 for each channel).
Change the input signal name for channel 1 to TWAVEA and output name to TWAVEhd.
Scope data capture is not done continuously; it is a triggered update using the trigger control
integer input name. If a rising edge of the trigger control signal is detected, new data is
collected. When you perform a steady state plot update, the same previously captured
32
words are displayed. The only time new data is collected is when a rising edge of the trigger
signal is detected.
If you want new small time-step data collected based on a trigger pattern, you could do this
as well using a pattern-trigger control signal. The pattern trigger is armed using a bit of the
trigger control input word (trignm). Upon arming the pattern trigger, the update is triggered
based on the pattern trigger input word (pattnm).
In this case the default trigger parameters can be used. To control triggering of the update,
add the control components shown in Figure 4.20.
Figure 4.20: SCOPE Component and Triggering Controls

To highlight the advantages of the SCOPE, add the plots seen in Figure 4.21 to your RUNTIME
interface. TWAVEhd vs TIMESIG is an X-Y plot with the small time-step time signal on the X-
axis and the small time-step scope signal on the Y-axis. In this example, when the
UpdatePlots pushbutton is pressed in RUNTIME new small time-step data is collected. This
example disables the pattern trigger control by setting the pattern trigger signal to 0.
Observe the functionality of the SCOPE by first comparing the distortion of TWAVEA to the
TWAVEhd signal. Also note that plotting TWAVEhd against time does not yield the true
33
representation of the signal. The X-Y plot is therefore required and will correctly match with
time. On this plot you should be able to see that a data point is plotted every small time-
step.
If you continue to trigger the scope to collect data, the X-Y plot may look strange. This is
because the update is not synchronized to the last 11000 words. The data could now be
starting at any location on the waveform. When looking at the X-Y plot you must also keep
in mind at which point you have selected to update data. If it happens to be at a point where
the small time-step time signal is being reset to 0, the results will look strange.
34
Figure 4.21: RUNTIME Interface for Observing SCOPE Functionality
4.6 ADDITIONAL EXERCISE: CHANGE IN THE DC BUS

In the previous case (Figure 4.2), the DC bus for the STATCOM was implemented as an ideal
source. An additional exercise would be to replace the source with a large capacitor, as this
more closely resembles a practical STATCOM. Figure 4.22 shows the change that needs to
be made to the power system. The change can be made by keeping the same component
35
(rtds_vsc_BRC3) for the DC bus, changing the branch type to RC and excluding the branch’s
optional voltage source in the branch. Choose the capacitor value to be 2000μF and make
the series resistance 0.0001Ω.
Figure 4.22: Bus with Capacitors Instead of Sources
The function of the STATCOM will remain the same, but the addition of the capacitor adds
another layer of complexity to the system. No longer can the power regulator be referenced
to zero as real power needs to be exchanged between the STATCOM and the power system
in order to maintain the charge on the capacitors. The Active Power Regulator developed
above will need to be augmented to achieve this objective.
4.6.1 DC BUS REGULATOR (FORMERLY ACTIVE POWER REGULATOR)

The voltage of a capacitor is governed by Equation 4-8. The voltage seen at the DC bus is
determined by the amount of current that can be directed to the bus. This provides a simple
relationship between DC Capacitor voltage, VDC, and Pinj. To increase VDC, inject more active
power, and hence current, to the STATCOM. Therefore, the DC bus can be regulated by
controlling the real power exchange. The PI controller seen in Figure 4.23 will perform the
required control.
1
𝑉𝑐 = ∫ 𝐼𝑐 𝑑𝑡 Equation 4-8
𝑐
36
Figure 4.23: Block Diagram of DC Bus Regulator
By cascading the two PI controllers of Figure 4.5 and Figure 4.23, the DC bus voltage can be
regulated indirectly by changing the load angle, δ. Figure 4.24 shows the complete block
diagram. The reason why the polarity is reversed for Pref and Pmeas, is because injecting P or
Q into the power system from the STATCOM is considered the ‘positive’ direction while
increasing the DC bus voltages, requires power flowing in the ‘negative’ direction.
Figure 4.24: Complete Block Diagram of DC Bus Regulator
Figure 4.25 shows the implementation of the DC Bus Regulator. An integrator time constant
of 0.25s and a proportional gain of 5 for the first PI controller seemed to provide reasonable
results. The parameters for the second PI controller are unchanged from earlier in the
tutorial.
Figure 4.25: Complete Block Diagram of DC Bus Regulator
4.6.2 VOLTAGE REGULATOR

The voltage regulator will be the same as in the previous cases where the DC bus contained
sources.
37

Create the same RunTime file from the previous case as seen in Figure 4.18. Once again, the
voltage at bus 2 should be around 1pu when the STATCOM is de-blocked. However, with the
addition of the capacitor, the active and reactive power flowing through network and the
STATCOM will deviate from zero since real power will be drawn to maintain the capacitor
voltage.
38
5 SIMPLE PWM TUTORIAL
5.1 OVERVIEW
This simple tutorial is meant as a quick introduction on how a simple Sinusoidal Pulse Width
Modulation (SPWM) scheme can be implemented on the RTDS Simulator using the small
timestep simulation environment. The example is fairly trivial but is nevertheless instructive.
The circuit shown in Figure 5.1 will be assembled and simulated.
Figure 5.1: Test Circuit
Ideal sources will be used for the DC Bus and a sinusoidal PWM scheme will be used to create
a switched voltage waveform at Bus #3. That switched waveform will be filtered to produce
a signal with reduced harmonic content at Bus #2. The voltage is then stepped-up to 93 kV
and will supply a purely resistive load.
5.2 STEP #1
The first step is to add a small timestep bridge box to your case. All portions of the circuit
running at the reduced timestep should be placed inside this box.
Copy a hierarchy box component from the Small Timestep/Power System/General library
into the draft case.
39
Figure 5.2: Location of small timestep bridge box in library
Right-click on the bridgebox that has been added to the simulation case and select
Parameters->Edit. The timestep for the components placed inside the bridgebox is set by
specifying the dt_size parameter. Set the parameter to 2500 ns.
Next, the circuit of Figure 5.3 should be assembled inside the small timestep bridge box.
Double click on the bridge box to open the canvas where the network can be built Please
note that in this first step the controls are simplified (ie: no firing pulses). These controls will
be enhanced in subsequent steps.
Figure 5.3: Simple Power Electronic Circuit
Explore the library to find the necessary components. Table 2 summarizes the library
location for the components used in this case.
40

DC Source Small Timestep/Power System/Sources rtds_vsc_BRC3
Small Timestep/Power System/Power rtds_vsc_PH3LEV2
2-level Converter Electronics/VSC Converters
HP filter Small Timestep/Power System/Passive Elements rtds_vsc_BRC3
Transformer Small Timestep/Power System/Transformers rtds_vsc_TRFS1PH
Resistive Load Small Timestep/Power System/Passive Elements rtds_vsc_BRC3
Reactor Small Timestep/Power System/Passive Elements Rtds_vsc_BRC3
DC Source Small Timestep/Power System/Passive Elements Rtds_vsc_BRC3
Table 2: Component Selection
A listing of main component parameters is given below. In this first step, no firing pulses are
provided to the two-level bridge.
DC Bus:
Voltage: ±20kV
Two Level Converter:

Enable DC Neutral Rail = Yes
Firing Pulse input: FPWORD
Valve Parameters: default
Load:
R = 86.49 Ω
Reactor:
L = 0.000505 Ω
Transformer:
Primary Voltage: 53.69 kV L-N, rms
Secondary Voltage: 7.967 kV L-N, rms
Rating: 33.33 MVA (1 phase)
Winding Resistance = 0.0 pu
Winding Reactance = 0.1 pu
Filter:
R = 0.90675 Ω
L = 1.1453e-4 H
C = 139.3 μF
Compile the case and create a simple RUNTIME interface where the 3-phase RMS voltages
at Buses 1, 2 and 3 are measured. Are they as expected?
41
5.3 STEP #2
With the basic circuit assembled, the next step is to create the controls for our SPWM
scheme. In a standard SPWM scheme a sinusoidal modulation signal is compared with a high
frequency triangle wave as demonstrated in Figure 5.4 (B). When the value of the triangle
wave exceeds that of the modulation signal then switch S1 of Figure 5.4 (A) will be turned
off. Conversely, when the amplitude of the triangle wave is less than that of the modulation
waveform then switch S1 will be turned on. The switch S2 will be controlled in a
Figure 5.4: Sinusoidal PWM Scheme
The signal Vout from the circuit will be a switched waveform similar to that shown in Figure
5.4 (C). With the PWM scheme that will be deployed it can be shown that the magnitude of
the filtered signal that would ideally appear at each phase of Bus 2 will be 𝑚 ∙ 𝑉𝐷𝐶 , where m
is the amplitude modulation ratio. Similar principles of operation apply to all three legs of
the bridge.
The control circuit shown in Figure 5.5 can be used to create the firing pulses for the switches
of all three phases. It consists of both main timestep and small timestep components. The
main timestep components are needed to support the small timestep components.
42
Figure 5.5: SPWM Controls
The main timestep controls create the modulation waveforms. These modulation
waveforms will have the same wave-shapes as the voltages we are trying to create.
The high frequency phase information is created by the angle wave generator
(rtds_vsc_ANGRAMP3). The angle information is passed to the high resolution triangle wave
generator (rtds_vsc_TRIWAV4). The generated high resolution triangle wave is then used by
another small timestep component, the firing pulse generator (rtds_vsc_3LGGIR), and is
compared to the modulation signals generated in the main timestep. This comparison must
be done in the small timestep simulation in order to accurately determine the instants at
which the switching events should occur. Additional details can be found in the more
comprehensive ‘Simple STATCOM’ exercise of the Small Timestep Tutorial.
Compile your case and create a RUNTIME interface that looks similar to that of Figure 5.6.
How do your simulation results compare to those shown? Change the amplitude
modulation index, m. Does it affect the simulation as you expect it should?
43
Figure 5.6: Runtime Metering And Control
5.4 STEP #3
Up until this point, all the simulations in this tutorial have consisted almost entirely of small
timestep components. When possible this is the preferred option but it isn’t always practical.
The main timestep library is much more extensive than the small timestep library and
sometimes the need for these models drives the need to interface small and main timestep
simulations. Also, small timestep simulation is relatively computationally intense when
compared to the main timestep simulation so it doesn’t always make sense to model
everything with the level of detail provided by the small timestep simulation.
In order to interface the main and small timestep simulations a component called an
interface transformer must be used. One side of the interface transformer will have only
main timestep components connected to it; the other side will only be connected to small
timestep components. Whenever possible the circuit should be divided at a point where
an actual transformer exists. This is due to the fact that the interface transformer has a
leakage reactance and a resistance. To minimize the impact of inserting the interface
transformer into the circuit it is best to insert it a point where a leakage reactance and a
resistance already exist. The presence of the leakage and resistance is a consequence of how
the interface transformer is modeled.
Some slight modifications to the case from Step #2 will be made; the resistive load will be
moved from the small-time step into the main timestep. Follow the instructions below:
44
1. Save the existing case under another name so that we can retain the case where
everything is simulated using a small timestep.
2. Replace the small timestep transformers with three single phase interface
transformers (rtds_vsc_IFCTRF1). Figure 5.7 illustrates how this can be done.
Figure 5.7: Small timestep circuit with Interface Transformer
3. Label the ‘Main Network Side’ of the interface transformers using a main timestep
bus label.
4. Duplicate main timestep bus label outside the VSC Bridge Box and connect a resistive
load as shown in Figure 5.8.
5. Compile the case and run it. Does it work as expected?
45
Figure 5.8: Main Timestep Side of Small timestep-Mainstep Interface
5.5 STEP #4 (OPTIONAL)
The control system from Step #2 can be modified so that a simple integral regulator keeps
the voltage at Bus #2 at some desired set-point. Modify the controller as indicated in Error! R
eference source not found. then compile and run the case again. Does the regulator work?
Figure 5.9: Optional Voltage Control
46
6 INTERFACING LARGE AND SMALL TIME-STEP SIMULATIONS

Up until this point, all the simulations in this tutorial have consisted entirely of small time-
step components. When possible, this is a good option, but it is not always practical. The
large time- step library is much more extensive than the small time-step library and
sometimes the need for these models drives the need to interface the small and large time-
step simulations. Also, small time-step simulation is relatively computationally intense when
compared to the large time-step simulation so it does not always make sense to model
everything with the level of detail provided by the small time-step simulation.
In order to interface the large and small time-step simulations a component called an
interface transformer must be used. One side of the interface transformer will have only
large time-step components connected to it; the other side will only be connected to small
time-step components.
There are several interface transformers available but the most recent and most stable
model is the rtds_vsc_IFCTRF1 component. Currently this interface transformer is only
available in single phase form; a three-phase transformer can be created using three of these
single-phase transformers. Two older interface transformers include the rtds_vsc_TF3 and
the rtds_vsc_STFR4 components. Use of these models, however, is not recommended since
the newer model is more stable.
Whenever possible the circuit should be divided at a point where an actual transformer
exists. This is due to the fact that the interface transformer has a leakage reactance and a
resistance. To minimize the impact of inserting the interface transformer into the circuit it is
best to insert it a point where a leakage reactance and a resistance already exist. The
presence of the leakage reactance and resistance is a consequence of how the transformer
is modeled. Details on the implementation of the rtds_vsc_IFCTRF1 component are given at
the end of this section.
As an exercise, the simple STATCOM from section 4 can be modified. The transformer will
be replaced by an interface transformer and the source and load will be modeled using large
time- step components since there is no need to model these devices with a small time-step.
Figure 6.1 illustrates how the original circuit is to be divided.
47
Figure 6.1: Simulating a Simple STATCOM using Two Different Time-Steps
The first step would be to remove the source, load and breaker from the small time-step
simulation and replace them with equivalent large time-step components. The transformers
in the small time-step bridge box will need to be replaced with interface transformers with
equivalent ratings, leakage reactance and resistance.
The next step is to connect the large time-step components to the interface transformer.
Fortunately, the VSC bridge box behaves similar to a conventional hierarchy box. If a large
time-step power system node is connected to the VSC bridge box using a wire, then that
node can be duplicated inside the VSC bridge-box and the compiler will recognize that the
nodes are in fact the same node and that they are electrically connected. With the node
duplicated inside the VSC bridge box, it can then easily be connected to the primary side of
the interface transformer. Figure 6.2 illustrates what the circuit should look like with the
source and load modeled in the large time-step. Some signals will need to be monitored and
some very minor changes will need to be made to the control system to get things working
like in Section 4.
48
Figure 6.2: Simple STATCOM Case Divided between Large and Small Time-Step Simulation
Facilities
6.1 INTERFACE TRANSFORMER

The rtds_vsc_IFCTRF1 interface transformer model is implemented as a travelling wave
transmission line. This approach to modeling the transformer was chosen because of the
stability that it provides. The transmission line is kept quite short; its traveling time is fixed
at 1.39 large time-steps. The inductance, L, of the transmission line is chosen so that it is
equal to the leakage of the interface transformer. The capacitance, C, of the transmission
line is then calculated using the travel time and the inductance of the line. For the purpose
of this calculation the line is assumed to be lossless. The actual model can accommodate the
presence of losses.
49
Assuming a lossless line, the travel time of wave propagating on a transmission line is given
by Equation 6-1.
𝑡𝑟𝑎𝑣𝑒𝑙 𝑡𝑖𝑚𝑒 = √𝐿 ∙ 𝐶
Equation 6-1
𝑤ℎ𝑒𝑟𝑒: 𝐿 𝑖𝑠 𝑡ℎ𝑒 𝑙𝑖𝑛𝑒 𝑖𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑖𝑛 𝐻
𝐶 𝑖𝑠 𝑡ℎ𝑒 𝑙𝑖𝑛𝑒 𝑐𝑎𝑝𝑐𝑖𝑡𝑎𝑛𝑐𝑒 𝑖𝑛 𝐹
With the travel time set to 1.39 times the large time-step, Equation 6-1 can be used to
determine the line capacitance. The result is given in Equation 6-2.
2
(1.39 ∙ ∆𝑇𝑙𝑎𝑟𝑔𝑒 ) Equation 6-2
𝐶=
𝐿
This capacitance is a direct consequence of modeling the transformer as a transmission line

and would not normally exist in the circuit. Care should be taken to make certain that this
capacitance is not too large. If it is, then it will start to impact the simulation, something
which should be avoided. In general, the value of XC should be significantly larger than the
surrounding impedances.
By inspection of Equation 6-2, it is evident that if the leakage of the interface transformer is
chosen very small then the capacitance, C, will be large. In order the avoid this situation the
interface transformer leakage must be greater than 0.05 pu.
The capacitance and inductance described above represent distributed parameters. In order
to be able to assess whether the capacitance of the line has become too large, it is helpful
to find the effective capacitance seen at terminals of the interface transformer. In order to
do this the π-circuit equivalent for the transmission line/interface transformer must be
found. Figure 6.3 shows this equivalent; an ideal transformer has been added to the
transmission line π-circuit equivalent to model the voltage transformation capabilities of the
interface transformer.
Figure 6.3: π-Circuit Equivalent for the Interface Transformer with Ideal Transformer
50
The effective capacitive reactance of the interface transformer seen from the large time-
step side of the interface transformer is labelled as XC and can be calculated using Equation
6-3 [3]. In this equation ZC is the characteristic impedance of the line, γ is the propagation
constant of the line and l is the length of the line.
−1
𝑌𝑒 −1 1 𝛾𝑙
𝑋𝐶 = ( ) = ( tan ℎ ( )) Equation 6-3
2 𝑧𝑐 2
With the assumption of a lossless line Equation 6-3 can be simplified to Equation 6-4.
−1
𝑌𝑒 −1 1 𝑗𝜔 ∙ 1.8 ∙ ∆𝑡𝑙𝑎𝑟𝑔𝑒
𝑋𝐶 = ( ) = ( tan ℎ ( ))
2 𝑧𝑐 2
Equation 6-4
𝐿
𝑤ℎ𝑒𝑟𝑒 𝑍𝐶 = √
𝐶
When a case containing an interface, transformer is compiled the effective capacitive

reactance is calculated for the rated frequency of the interface transformer and is listed in
the MAP file. For convenience, the effective capacitance of the line is also referred to the
small time-step side of the ideal transformer and listed in the MAP file. An excerpt of the
listing is provided below:
VSC component model of type "ifctrf1"

named: T1
within the BRIDGE named: VB1
in subsystem: #1
is assigned to GPC Card #2 Processor A
At a tap factor of 1.0, there is an effective

capacitive reactance connected between the
primary terminals of 2.704987e+004 Ohms.
Regardless of the tap factor, there is an

effective capacitive reactance connected between
the secondary terminals of 3.784344e+002 Ohms.
The MAP file can be viewed by pressing the view button in DRAFT’s toolbar and selecting
MAP File in the dialog that appears. Figure 6.4 shows the button that should be pressed.
51
Figure 6.4: Opening a MAP File
52
7 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP

TRANSMISSION LINES
Currently, each VSC bridge box can contain a maximum of 30 nodes and about 32 switching
devices. It is recognized that there is sometimes a need to model larger switching networks.
In response to this need, the VSC Cross−Card Bergeron Transmission Line model has been
developed. The transmission line model can be used either to model a transmission line in a
single VSC Bridge Box or they can be used to connect two VSC Bridge Boxes together. It is
this latter ability to link bridge boxes that will be the focus of this section.
The process of linking small time-step bridge boxes is analogous to connecting different racks
for the large time-step simulation. The network solutions for each bridge box are effectively
decoupled if the travelling time of the transmission line connected between them is greater
than a small time-step. This decoupling allows the network solutions to be solved
independently and results in significant computational savings. Given that a small time-step
is typically 1.5~2.5μs and assuming a wave propagation velocity of 3x108 m/s the minimum
length of the small time- step transmission line ends up being on the order to 430 to 740m
long, significantly shorter than the large time-step transmission lines which are typically on
the order of 15km long.
7.1 HARDWARE CONNECTIONS

Large time-step transmission lines are used to communicate from one rack to another. Signal
communication is managed by the GTWIF and in order to communicate from one rack to
another there has to be a fiber optic cable linking the GTWIF cards of the respective racks.
Analogously, small time-step transmission lines are used to communicate from one small
time-step bridge box to another. In order to communicate between the two bridge boxes
there must be a fiber optic link between them. Unlike with large time-step t-lines where
racks are linked through the GTWIF cards, small time-step t-lines are linked through the
GPC’s card GTCOM ports.
Each GPC card has four fiber optic ports, two are GTCOM ports and two are GTIO ports which
are used to connect IO cards. The topmost port is GTCOM port 3 while the second from the
top is GTCOM port 4. Please refer to Figure 7.1 for a diagram on how to locate these ports.
53
Figure 7.1: Location of GTCOM Ports on GPC Processor Card
As already stated, in order to connect a transmission line between one bridge box and
another, there must be a physical fiber optic cable connecting the cards on which the bridges
are running. The signals for up to 8 transmission lines can communicate over the same fiber
cable and both processors on a GPC card can simultaneously access the same GTCOM port.
Figure 7.2 shows three different examples of how small time-step bridge boxes can be
linked. The processors on which the bridge boxes are running have been selected arbitrarily.
A line connecting any two bridge boxes in the diagram indicates that one or more t-lines
span them; lines of the same color represent the same physical fiber optic cable. The GTCOM
ports to which each end of a fiber is connected are also indicated in Figure 7.2.
54
Figure 7.2: Sample Bridge Box Interconnections
7.2 SMALL TIME-STEP TRANSMISSION LINES

Similar to large time-step transmission lines, three things are needed to make a small time-
step transmission line (1) a sending end terminal, (2) a receiving end terminal and (3) a
calculation block. Figure 7.3 shows the DRAFT icons for these components. They are linked
by the compiler if they share the same ‘T-LINE NAME’.
55
Figure 7.3: (A) Sending End, (B) Receiving End and (C) Calculation Block for a Small Time-Step T-
Line
In order to link two bridge boxes, one end of the small time-step transmission line would be
placed in one of the bridge boxes and the other end would be placed in the second bridge
box; the calculation block can be placed in either. Figure 7.4 illustrates how a simple circuit
might be divided between two bridge boxes. Generally, the process of creating the data for
a small time- step t-line is identical to that needed for a large time-step transmission line.
Please review Tutorial Chapter 2: Simple AC System for details on this process.
Figure 7.4: Using a Transmission Line to Connect Two VSC Bridge Boxes
One important difference from large time-step transmission lines is that the GTCOM port
used must explicitly be specified inside each terminal of the transmission line. Figure 7.5
shows the parameter which must be changed in each of the transmission line terminals.
56
Figure 7.5: Specification of the GTCOM Port Inside a Transmission Line’s Terminals
When a case which includes small time-step transmission lines is compiled successfully then
a.txt file is generated that is named DRAFTFILENAME_comm_fiber_patching.txt. This file is
located in the project directory and lists where all the necessary fiber connections should be
made. This file is especially useful if you have many connections. The content of such a file
is listed below:
Optical fibers must be connected between

communication ports on the backs of
processor cards as follows:
END No. 1 END No. 2

rack card port <----> rack card port
7 1AB 3 7 1AB 4
Since the transmission line depends on a physical fiber connection, it becomes useful to be
able to fix the processor on which the small time-step bridge will run. If this is not done, then
the processor to which a given VSC bridge box is assigned can change from one DRAFT
compilation to the next. This would require that frequent changes to the GTCOM fiber
connections be made. Not only would this be tedious, it is also error-prone. The processor
to which a specific VSC Bridge is assigned can be manually set by the right-clicking on a given
bridge box and selecting Edit -> Parameters. Figure 7.6 show the parameters that need to be
modified in order to manually assign a bridge box to a specific physical processor.
57
Figure 7.6: Parameters Associated with Manual Processor Allocation of VSC Bridge Boxes
58
8 SMALL TIME-STEP IO
Importing and exporting signals into and out of the small time-step simulation is fairly
straight forward. This section provides a brief rundown of how to do this for both digital and
analog signals.
8.1 ANALOG OUTPUTS

All small time-step analog signals are output from the RTDS simulator on an individual basis.
The user must specifically indicate which signals they want output and where they would
like those signals output. This is typically done directly within individual small time-step
components. The signals available to be output will vary from one component to another. In
general, a signal can either be output to one of the processing card’s faceplate outputs or to
a GTAO card connected to the processor. The process of sending a signal to both of these
targets is described below.
8.1.1 FRONT PANEL AO

Generally small time-step components will have a tab named either ‘ENABLE FACEPLATE D/A
OUTPUT’ or another similar name. This tab allows the user to select the signals intended for
output through the front panel analog outputs. As mentioned, the signals available to be
output will vary from one component to another. After a signal has been selected for output
through the front panel then another tab will be become available. The name of the tab will
vary but it will be something along the lines of ‘FACEPLATE D/A CHANNEL ASSIGNMENT’ and
it will allow the signal to be assigned to a specific channel. The channel can be any value
between 1 and 12. The signal will be written to the channel of the processor on which the
model is running (either processor A or B). A scaling constant can be used to modify the
signal of interest so that it lies within the front panel analog outputs dynamic range of +/-
10V. A unique offset can also be added to each of the faceplate outputs. Figure 7.2 highlights
the parameters that would have to be changed if a branch current were to be monitored
though the front panel.
59
Figure 8.1: Menu Items related to Front Panel Analog Outputs
8.1.2 GTAO
The process of sending a signal to the GTAO is similar to that needed to output a signal
through the faceplate but a few additional steps are needed. Every small time-step
component must be assigned to a processor and each processor can access up to two GTAO
cards. Each GTAO is referred to as either ‘GTAO1’ or ‘GTAO2’. The first step is to enable
components within the small time-step bridge box to access the GTAO cards. This is done
inside the properties of the VSC bridge box as shown in Figure 8.2.
60
Figure 8.2: Enable Access to GTAO Card Inside the VSC Bridge Box
If analog output through at least one of the GTAOs has been enabled then the menu of Figure
8.3 will appear and details about the physical connections of the GTAO can be entered.
Specifically, the GTAO card number and the GTIO fiber port number to which it is connected
must be entered. It should be noted that only the first two GTAO cards in any chain can be
accessed.
Figure 8.3: Specify GTAO Card Number and GTIO Fiber Port to which it Connects
NOTE: Once access to the GTAO cards has been enabled within the small time-step bridge
box then signals can be freely assigned to the GTAO channels within individual
components. Failure to complete the above steps will trigger errors when the case is
compiled.
Generally small time-step components will have a tab called ‘ENABLE GTAO D/A OUTPUT’ or
something similar. This tab allows the user to select the signals intended for output through
a GTAO analog output card. Like with the faceplate analog outputs, the signals which are
available to be output will vary from one component to another. When at least one signal is
chosen for output through the GTAO, another tab will appear (if not already visible); in it the
user must specify the GTAO card to which each signal is to be sent. This is done by referring
to the ‘GTAO1’ or ‘GTAO2’ aliases that are assigned to physical GTAO cards in the small time-
step bridge box. The specific GTAO channel must also be specified; any value between 1 and
12 is valid but if multiple signals are assigned to the same channel of the same GTAO card
61
then an error will result upon compiling the case. A scaling constant must be specified for
each channel. The scaling constant is usually chosen so that a scaled signal falls within the
+/- 10V dynamic range GTAO card. Like the faceplate analog outputs, an offset can be added
to the scaled output and the output can be inverted if desired. Figure 8.4 highlights the
parameters that would have to be changed if a branch current were to be monitored through
a GTAO.
Figure 8.4: Menu Items Related to GTAO Analog Outputs
It is desirable to have the ability to control the processor to which a small time-step bridge
box is allocated. This is especially true when external equipment needs to be interfaced
through the small time-step component. In general, the compiler can automatically allocate
the bridge box to an available processor but the allocation can potentially change as a case
is developed. This opens up the possibility that a small change in a case could cause the small
time-step bridge box to get bumped to another processor and thus would require all the
external connections to be physically moved. This potential problem can be avoided by
manually assigning components to a processor; the small time-step bridge box will thus
always get allocated to the specified processor each time the case is compiled. Figure 8.5
shows the parameters in the bridge box which allow the user to manually assign it to a
specific processor.
62
Figure 8.5: Manual Processor Assignment of Small Time-Step Bridge Box
8.2 DIGITAL INPUT

8.2.1 GTDI
Digital input signals are used extensively in small time-step simulation for things like
providing firing pulses to power electronic switches. The GTDI IO card is required in order to
bring digital signals into the small time-step simulation. A small time-step bridge box can
access up to two different GTDI cards but they must be the first two GTDI cards in the chain.
As with the GTAO, the first step to using the GTDI is to enable components within the small
time-step bridge box to access them. This is done inside the properties of the VSC bridge box
as is shown in Figure 8.6.
Figure 8.6: Enable Access to GTDI Card Inside the VSC Bridge Box
After the digital input from the GTDI card has been enabled then the menu of Figure 8.7 will
appear where details about the physical connections of the GTDI can be entered; the GTDI
card number and the GTIO Fiber Port number to which it is connected must be specified.
Also, two signal names to which the inputs read from the GTDI card can be assigned should
be specified. The GTDI has 64 channels; channels 1-32 get assigned to GTDI word 1 and the
channels 33-64 get assigned to GTDI word 2. These words can then be referenced by various
small time-step components.
63
Figure 8.7: Specify GTDI Card Number, the GTIO Fiber Port, and the Signal Names for the Read
Signals
Once access to the GTDI cards has been enabled within the small time-step bridge box and
their inputs have been assigned to signals, then these signals can be freely referenced by
individual components. Most components that can accept digital inputs will have a tab called
‘FIRING PULSE INPUT’. If the option exists, then the source of the firing pulse input word
should be specified as ‘CC_WORD’. One of the signal names assigned inside the small time-
step bridge box can then be referenced inside the component. Figure 8.8 illustrates how this
can be done for the three-phase, two-level bridge component (rtds_vsc_PH3LEV2); one of
the GTDI’s input is presumed to have been assigned to the control word ‘GTDI1W1’ inside
the small time-step bridge box.
Figure 8.8: Referencing Inputs from a GTDI Inside a Small Time-Step Component
8.3 ANALOG INPUT

8.3.1 GTAI
In order to bring analog signals into the small time-step simulation the rtds_VSC_GTAI
component can be used. The icon for the component is shown in Figure 8.9.
64
Figure 8.9: Icon for Small Time-Step GTAI Component
This component works in much the same way that the large time-step GTAI component
works. Details about the physical connections of the GTAI must be specified; this includes
the GTAI card number and the GTIO fiber port number to which it connects. Each of the
GTAI’s channels can be enabled individually. A separate scaling constant and offset can be
specified for each channel. The read GTAI signals can also be made available in the large
time-step or through the front panel analog outputs if desired.
65
8.4 DIGITAL OUTPUT

8.4.1 GTDO
In order to output digital signals from the small time-step simulation the rtds_VSC_GTDO
component can be used. The icon for the component is shown in Figure 8.10.
Figure 8.10: Icon for Small Time-Step GTDO Component
This component works in much the same way that the large time-step GTDO component
works. Details about the physical connections of the GTDO must be specified; this includes
the GTDO card number and the GTIO fiber port number to which it connects. The 64 channels
of the GTDO card are divided into four 16 channel banks. Each bank is controlled by a
different control signal and can be enabled or disabled independently. The 16 least
significant bits of the first control signal are assigned to output channels 1-16; the 16 least
significant bits of the second control signal are assigned to output channels 17-32, etc.
66
9 SELECTING VALVE PARAMETERS

As discussed in Section 2 of this tutorial, several shortcuts are used to mimic the behavior of
a switch; an open circuit is modeled as an RC branch and a short circuit is modeled as an L
branch. This approach is selected primarily because it allows the freedom to select R, L and
C in such a fashion that the conductance value for when the switch is opened, goc, and when
it is closed, gsc, are the same. The change in switching state can then be completely
represented by changes in current injections. This significantly simplifies the required
calculations because the matrix inversion of Equation 2-5 is not required by the network
solution.
The validity of the modeling approach used for small time-step simulation is based upon the
accuracy with which a large resistance can be represented by an RC circuit and the accuracy
with which a small resistance can be represented by an inductance. The parameters R, L and
C must be selected with care in order to make certain that the chosen approximations are
accurate. In this section, the different constraints which are placed on the selection of these
parameters is discussed.
1. The main objective of modeling an open circuit as an RC circuit, and a short circuit as
an inductor is to avoid the need for a matrix inversion whenever a switch changes
state. In order to achieve this objective, the conductance values for both states must
be the same. This leads directly to Equation 9-1, the first constraint imposed on the
selection or R, L and C.
2𝐿 ∆𝑡
=𝑅+ Equation 9-1
∆𝑡 2𝐶
2. With the chosen modeling approach there is the potential for undesired interactions
between the switches. Consider two series connected switches, one in the ON state
and the other in the OFF state. Using the conventional modeling approach this would
be a large resistance in series with small resistance but using the proposed approach
it is actually represented by a series RLC circuit. It is possible that the response of
such a circuit could be poorly damped when subjected to a disturbance. If possible,
it is desirable to select R, L and C parameters for the switches such that the response
of the circuit to a disturbance is well damped. The challenge is that switches can be
connected in any arbitrary topology and that the equations relating damping to the
parameter choices will change accordingly. A heuristic approach must therefore be
adopted; the values of R, L and C are selected so that good damping is achieved for
series connected switches, one ON and the other OFF. This topology is illustrated in
Equation 9-1 and is one that is commonly found in VSC converters.
67
Figure 9.1: Series Connected Switches, one ON and the other OFF
𝐼(𝑠)
Writing the transfer function relating for 𝑉(𝑠) results in a second order function for which it
is easy to define the damping factor, δ, and natural frequency, ωn. The transfer function, δ
and ωn are given in Equation 9-2, Equation 9-3, and Equation 9-4.
𝐼(𝑠) 𝑠
= Equation 9-2
𝑉(𝑠) 𝐿 (𝑠 2 + 𝑠 𝑅 + 1 )
𝐿 𝐿𝐶
𝑅
2𝛿𝜔𝑛 = Equation 9-3
𝐿
1
𝜔𝑛 = Equation 9-4
√𝐿𝐶
The desired damping of the circuit is something that will be specified as a valve parameter;
the natural frequency is not so much a concern. Substituting out ωn from Equation 9-3 and
Equation 9-4 leads to Equation 9-5, the second constraint imposed on the selection or R, L
and C.
1 𝑅
2𝛿 = Equation 9-5
√𝐿𝐶 𝐿
3. As a result of the modeling method there are artificial losses which occur every time
a switch changes state. For slowly switched circuits these loses are not a concern but
as the switching frequency increases these losses start to accumulate. The aim of the
final constraint applied to the selection of R, L and C is to minimize these losses.
Consider Figure 9.2 which shows a comparison of the current established in an ideal switch
at turn-on versus the current established in an inductor, the chosen representation for a
switch in the ON state. Assuming that L will be quite small, when the switch starts to the
conduct the current should be established relatively quickly. This is required if good
simulation results are to be achieved. If the valve will stay in its switching state long enough
68
so that the inductor representing it charges to its full capacity then the energy stored equals
1
𝐸𝑠𝑐 = 2 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 . When the switch turns off then the energy stored is lost, because the L
branch is abruptly changed to an RC branch.
Figure 9.2: Comparison of Current Establishment in Ideal Switch and Small Time-Step Switch
Consider Figure 9.3 which shows a comparison of the voltage established across an ideal
switch versus the voltage established across the capacitor in an RC circuit. Assuming that the
capacitance will be quite small, when the switch is opened the voltage across the capacitor
should be established fairly quickly. This is required if good simulation results are to be
achieved. If the valve stays in its switching state long enough so that the capacitor
representing it charges to its full capacity the energy stored will be 𝐸𝑜𝑐 = 𝐶𝑣𝑏𝑙𝑜𝑐𝑘 . When the
switch turns on again the energy stored is lost, because the RC branch will abruptly be
changed to an L branch.
Figure 9.3: Comparison of Voltage Established Across an Ideal Switch and the Capacitance in an RC
Circuit
The goal is to minimize the total energy lost during a switching cycle. This quantity is given
by Equation 9-6.
𝐸𝑡𝑜𝑡𝑎𝑙 = 𝐸𝑠𝑐 + 𝐸𝑜𝑐

1 2 2 Equation 9-6
𝐸𝑡𝑜𝑡𝑎𝑙 = 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 + 𝐶𝑣𝑏𝑙𝑜𝑐𝑘
2
69
It can be shown that this is achieved when the Equation 9-7 is satisfied. This is the last of the
3 equations that are used to constrain the selection of R, L and C in the chosen valve
representation.
2
1 2
𝐶𝑣𝑏𝑙𝑜𝑐𝑘 = 𝐿𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡 Equation 9-7
2
Equation 9-1, Equation 9-5 and Equation 9-7 can be solved for the parameters R, L and C.
The results are given in Equation 9-8, Equation 9-9, and Equation 9-10.
∆𝑡 𝑣𝑏𝑙𝑜𝑐𝑘
𝐿 = √2 (𝛿 + √𝛿 2 + 1) Equation 9-8
2 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
2
∆𝑡 1 Equation 9-9
𝐶 = ((𝛿 + √𝛿 2
+ 1) )
2 𝐿
2𝐿 ∆𝑡 Equation 9-10
𝑅= −
∆𝑡 2𝐶
The parameters ∆t, δ, vblock and iconduct are all assumed to be known. The small time-step size
is calculated during the compile. The damping, blocked voltage during switching and
conduction current during switching are all user specifiable parameters. Components that
model switches using the method described above will generally have a properties tab
labelled VALVE PARAMETERS. Figure 9.4 shows such a tab for the rtds_vsc_PH3LEV2
component.
Figure 9.4: Properties Tab where Valve Parameters are Specified
70
After solving for R, L and C it is possible to write equations for XC and XL as a function of
frequency. These equations are given in Equation 9-11 and Equation 9-12.
∆𝑡 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐿 = √2 ∙ 2𝜋𝑓 (𝛿 + √𝛿 2 + 1) Equation 9-11
2 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
√2 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝑐 = Equation 9-12
∆𝑡
2𝜋𝑓(𝛿 + √𝛿 2 + 1) 2 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
Given that the damping factor, δ, is limited to lie between 0.7 and 1.33 and that the time-
step, ∆t, will generally be on the order of 2μs. Assuming that δ ~ 1 and ∆t ~ 2μs, Equation
9-11 and Equation 9-12 are approximately equal to Equation 9-13 and Equation 9-14.
𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐿 ≈ 1𝑥10−5 𝑓 Equation 9-13
𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
5
1𝑥10 𝑣𝑏𝑙𝑜𝑐𝑘
𝑋𝐶 ≈ Equation 9-14
𝑓 𝑖𝑐𝑜𝑛𝑑𝑢𝑐𝑡
𝑣𝑏𝑙𝑜𝑐𝑘 𝑣𝑏𝑙𝑜𝑐𝑘
By inspection up to about 10kHz, XL is at most about 0.1𝑖 and XC is at least 10𝑖 .
𝑐𝑜𝑛𝑑𝑢𝑐𝑡 𝑐𝑜𝑛𝑑𝑢𝑐𝑡
𝑣𝑏𝑙𝑜𝑐𝑘
If the ratio 𝑖 is selected as the base impedance then a short will be a relatively small
𝑐𝑜𝑛𝑑𝑢𝑐𝑡
impedance and an open circuit will be a relatively large impedance.
9.1 STRATEGY FOR SELECTING VBLOCK AND ICONDUCT

Quite often the default values for vblock and iconduct are reasonable and do not need to be
changed. If there is, however, some concern about whether the switch is approximating an
open circuit when OFF and a closed circuit when ON then the ratio of vblock and iconduct can be
changed so that it is approximately equal to the base impedance of the system. In cases
where abnormally high losses are observed, the values of vblock and iconduct can be adjusted
so that they more accurately represent the average blocked voltage and the average
conducted current seen by the switch. A balance must be struck between (1) having the
switch represent a large impedance when off/small impedance when on and (2) avoiding
excessive losses which are anomalies of the modeling approach.
71
10 PROCESSORS
DISTRIBUTING PROCESSING LOAD OVER TWO
The method used for modeling a switch in small time-step simulations begins to lose its
accuracy as the time-step increases. It is therefore desirable to keep the time-step small,
preferably below 2.5μs. The time-step used is a function of the complexity of the small time-
step circuit; as the number of components inside a VSC bridge box grows the time-step will
increase. An estimate of the small time-step is calculated when the case is compiled and the
calculated value is written to the MAP file. Inside the MAP file a section similar to the one
listed below shows the small time-step that is used.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
RISC-based VSC_NET1 Bridge model named:
VB1 in subsystem: #1
is assigned to GPC Card #1 Processor B
The Bridge model has 28 small

time-steps in each large time-step.
The small time-step size is 1.785714 microseconds.
The calculation time permitted for

each small time-step is 1724
nanoseconds.
There is no T0 output. If there had been

it would have gone out in small step number: 2.
Any T2 output is scheduled for small step number:
14.
The small-step clock count on processor A

is expected to be 1309 clocks without the margin.
The User specified margin is 360 nanoseconds ( 360 clocks ).
The VSC network solution method on 1st

processor is W-matrix.
Estimated W-matrix = 246
clocks. Estimated Gi-matrix =
434 clocks.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
If the time-step becomes large then it is advisable to distribute the calculation load over two
processors in order to reduce it. As a general guideline, if a small time-step circuit has more
than 18 single-phase switches or if several computation-heavy components (i.e. small time-
72
step machine model) are used then it is a good idea to use two processors. If the small time-
step is larger than 3μs then a warning will be issued, this signals to the user that the
processing load should be re-distributed.
By default, the small time-step bridge box taken from the library will run on a single
processor. In order to use two processors for the calculation of the small time-step
simulation the parameter rqnmp inside the VSC bridge box must be changed to Two. This is
Figure 10.1: Running Small Time-Step Simulation on Two Processors
After two processors have been requested in the bridge box’s properties menu then
individual components must be allocated to either processor one or processor two. Most of
the small time-step components will have a parameter called prc12; this parameter can be
assigned a value of either one or two and allows for the allocation of a component to a
particular processor when two processors have been requested by a bridge box. If only one
processor has been requested, then all components will be placed on that processor. Figure
10.2 highlights the prc12 parameter.
Figure 10.2: The prc12 Parameter used to Assign Small Time-Step Components to a Particular
Processor
73
11 REFERENCES
[1] T. Maguire and J. Giesbrecht. Small Time-step (<2μ Sec) VSC Model for Real Time
Digital Simulator. International Conference on Power System Transients (IPST’05).
Montreal, Canada. June 19-23, 2005.
[2] Mohan, Undeland, and Robbins. Power Electronics: Converters, Applications, and
Design. 2nd Ed. Toronto: John Wiley & Sons, Inc, 1995
[3] Prabha Kundur. Power System Stability and Control. Toronto. McGraw-Hill, Inc.
1994
74

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Substep

6.5 STEP #4 (OPTIONAL) ........................................................................................................................ 58

2 SUBSTEP SIMULATION BASICS

Figure 2.1: Current Source Parallel to a Resistor

Figure 2.2: Equivalent Power System Network

(a)Switch OFF (b)Switch ON

Figure 2.4: Substep Architecture

3 DIFFERENCE BETWEEN SUBSTEP AND SMALL TIME-STEP

[𝑉] = [𝐺]−1 [𝐼] Equation 3.1

(a) Closed Switch (b) Open Switch

The introduction of RTDS ® NovaCor platform in 2017 provides a significant increase in

Table 1: Comparison Between Small Time-Step And Substep

Node Limit Node limit = 30 (PB5/GPC) Node Limit = 60

Switch Model RLC Switching Resistive switching (without artificial

4 SIMPLE VOLTAGE RECTIFIER

Figure 4.1: Simple Voltage Rectifier Circuit To Be Assembled

4.1 SUBSTEP HIERARCHY BLOCK

Figure 4.2: Substep Hierarchy Box

(a) Substep Box Parameters

(b) Substep Options Parameters

4.2 VOLTAGE RECTIFIER CIRCUIT

Figure 4.4: Simple Voltage Rectifier Circuit To Be Assembled

Table 2: Component Selection For Simple Voltage Rectifier Circuit

Figure 4.6: Control Circuit for the 3 Phase Sine Wave

Figure 4.8: Firing Pulse Input Control Signal

Figure 4.9: Controls To Compute DC Voltage

Figure 5.1: Topology of the STATCOM Circuit

5.1 STATCOM CIRCUIT

Figure 5.2: STATCOM Circuit Built In Substep

Table 3: Component Selection For Simple STATCOM

Further details of the circuit are provided below.

Figure 5.4: Substep Signal Wave Repeater

Table 4: Control Components For Signal Wave Repeater Inputs

Component Library Component Name

Figure 5.6: Source Parameters

Figure 5.7: Breaker Parameters

Figure 5.8: Breaker Switch

Set the transformer electrical parameters based on Figure 5.9.

Figure 5.9: Transformer Electrical Parameters

5.5 TWO-LEVEL STATCOM CONVERTER, AC REACTORS, AND DC BUS

Figure 5.12: Firing Pulse Input

Figure 5.13: Valve Parameters

5.6 STATCOM CONTROLS

Figure 5.14: STATCOM Controls

5.7 BASE VALUES

Figure 5.16: Base Values

𝑉𝐿𝐿 Equation 5.5

Figure 5.17: Base Value Calculations

5.8 DC LINK VOLTAGE CONTROL

Figure 5.18: Per-Unit Calculation Of The DC Voltage, VDC

Figure 5.19: DC Voltage Control

Figure 5.20: Inside PI Controller Hierachy Box For Vdc Control

Figure 5.21: Sliders For Pi Controller Gains, And Vdc Reference

5.9 PLL, ABC-DQ TRANSFORM, AND FILTERS

5.10 PLL CONTROLS

Figure 5.22: PLL Controls

Component Library Component Name

Set the PLL parameters as shown in Figure 5.23.

Figure 5.23: PLL Parameters

5.11 ABC-DQ TRANSFORM CONTROLS

Figure 5.24: ABC-DQ Transform And Filters

Table 6: Components For ABC-DQ Transform And Filters

Component Library Component Name

5.12 PCC AC VOLTAGE CONTROL