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Abstract— Synchronizers play a main role in clock domain There are two digital systems which are working at different
crossing(CDC).Large multiple-clock domain systems on clocks. System1 is working at clock1 and system2 is working
chip(SoC) require synchronization in two cases: (1).When at clock2. When the data is transferred from one clock domain
transferring signals and data between various clock domains.(2).
to another clock domain data synchronization is required.
When receiving asynchronous inputs.Such synchronizations
often affected to metastability effects.Synchronizers which are
These two digital systems require a block to communicate
designed specifically for the elimination of metastability from the with each other[9]. A synchronizer samples an asynchronous
system are known as metastable hardened synchronizers.The signal and give an output which is synchronized version to the
performance parameters of synchronizer are metastability time local clock.
constant(�),metastability window(Tw) and Mean Time Between
Failure(MTBF).These parameters are affected by the technology B. Multistage Synchronizer
scaling , process variation , temperature variations and voltage Fig.2 shows typical multistage synchronizer.To
variations. mitigate the effects associated with metastability, latches and
flips flops are often used to synchronize the data [1], such as
Keywords- Metastability-Time-constant(� ), MTBF, CDC, PVT- the N pipelined flip flops shown in Figure.
variations, Technology Scaling
I. INTRODUCTION
In modern, many applications consist of multiple
clock domains. There is data transfer between these clock
domain systems. Synchronizer is used for data
synchronization. To determine the reliability of system
synchronizer plays a very essential role. System on chip
designs have thousands of clock domain crossings (CDC),
where the system is affected to metastability errors[1].
Synchronizers are used to convert domain timings, to mitigate
those failures and provide reliable signal transition between Fig.2.Multistage Synchronizer[1]
CDCs. The synchronizer is having a parameter such as �, Tw
Metastability resolution time is given as[1],S≈(N-1) × Tc
and MTBF.As the data changes in metastability window
where,Tc is the clock cycle time of the receiving clock
synchronizer suffers from a metastability problem,because of
domain.There is a probability that the circuit will not resolve
that failures occur in system. As metastability occurs we cant
its metastable state correctly within the allowed time.
predict the correct level of output whether it is ‘0’ or ‘1’.The
metastability problem can never be completely avoided but its C. MTBF(Mean Time Between Failure)
probability can be reduced. Mean Time Between Failure gives us information on
A. Basic Synchronizer how a particular element will fail.It also gives the average
time interval between two successive failures. The
performance of synchronizer is usually measured by the mean
time between failure(MTBF).MTBF is represented as
following equation[1],
Fig.7.Pseudo-NMOS Synchronizer[6]
The pseudo-nmos latch design shown in Fig.7 is a
very efficient synchronizer design with very low τ values.But
the propagation delay due to the circuit is very high.This
circuit is similar to the jamb latch design except for the
pseudo-nmos configuration[6].Operation of pseudo-nmos
latch design is as follow: when clock goes high, both PMOS
transistors are conducting. So q and qbar will be pulled to
VDD.As clock goes high q is set to high through PMOS when
d input is high and dbar is low,which disconnects any direct Fig.9.The degradation effects of PVT on �[1]
& threshold of transistors[4].As the temperature increases the
Vth decreases so, � also decreases.When supply voltage is
high & threshold voltage is low,� increases with
temperature.Simulations of � vs. temperature for different
supply voltages are shown in fig.12.Supply voltage has a large
effect on �.When VDD is decreased, Gm also decreased and
so � increases[4].So to have a higher value of � higher supply
voltage is recommended.
V. CONCLUSION
In this paper the working, advantages and
disadvantages of all the synchronizers are discussed. Pseudo-
NMOS synchronizer has a lower � value and higher MTBF
value among all the synchronizers.The effect of technology
Fig.10. � simulations for different process corners [3] scaling and PVT variations is also discussed.The value of �
decreases as the technology scales.As the temperature
increases and VDD decreases the value of � increases because
Gm increases.
REFERENCES
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