COMPRESSION

ASSIGNMENT 1
SUBMITTED BY

VLSIGURU DFT TRAINING SCAN INSERTION

ASSIGNMENT

COMPRESSION ASSIGNMENT
1. What is compression?
 Compression is a technique which is used to reduce the test time, data volume
and the size of the circuit and making sure that the test coverage remains
unchanged.
 To perform compression we make use of TESSENT TEST KOMPRESS tool
and the command for this is set context dft -edt.
 TESSENT TEST KOMPRESS achieves compression of scan test data by
controlling a large number of internal scan chains using a small number of
scan channels.
 Compression scan is low cost
 Debug is little tougher than Full scan and it is for production purpose.

2. Why need compression?

 Maintain high test quality ( Support for all fault types)
 Achieve high test compression of both test time and test data
 Have little or no impact on the functional design
 Add minimal test logic.
 Easily fit into the design flow.
 3. Explain compression architecture with decompressor and compactor?
EDT ARCHITECTURE
The embedded logic includes
Decompressor located between the external scan channel inputs and the
internal scan chain inputs which consists of a ring generator and phase shifter.
 LFSM [Linear finite state machine]
 Phase shifter
Compactor located between the internal scan chain outputs and the external
scan channel connected to the tester. It primarily consist of spatial compactor
and gating logic

4. Write internal diagram of Decompressor?

LFSM (Ring Generator):

  The ring generator is a unique linear finite state machine (LFSM) that is
obtained by applying a number of m -sequence preserving transformations to
the canonical form.

PHASE SHIFTER:

 The phase shifter logic enables the ring generator to drive the large number of
internal scan chain inputs, and reduces the linear dependencies among bit
streams supplied to the scan chain inputs by displacing them by at least the
longest chain length.
 The XOR gates in the phase shifter are driven by a limited number of ring
generator stages to reduce the propagation delay.
 The XOR gates in the phase shifter can be restricted to utilize a subset of the
ring generator stages. Such modularity is helpful in significantly reducing the
routing congestion when a large number of scan chains need to be driven by
the decompressor.

5. Define compression ratio? How do you decide compression ratio?

 Compression ratio is defined by the ratio of internal chains by external
channels.
Compression Ratio: = Internal chains/External Channels.

Compression ratio can be decided based on test coverage and the time taken for
testing and also making sure that the number of patterns generated is acceptable.

Channels Compression Internal Coverage Patterns Run times

ration scan chains
5 50 X 250 97% 5000 3 hours
5 60 X 300 98% 6000 4 hours
5 70 X 350 98.5% 7000 4.5 hours
5 80X 400 98.2% 9000 6 hours
5 90X 450 98% 11000 8 hours

EXTERNAL CHANNEL: Get into from the Tester (ATE) or Design Team.
COMPRESSION RATIO: As per the tool guidelines, need to maintain ideal
compression ratio.
INTERNAL SCAN CHAIN: Based on the external channel and the compression
ratio need to calculate the Internal scan chain.
 Here the 5 channels fixed from the tester requirements.
 The main goal is the high test coverage and less no of patterns. So here we are
choosing 5 channels with 70X Compression ratio with 350 internal scan
chains of 98.5 coverage which consists of 7000 patterns with 4.5 hours
runtime.
 Compared to the other channel it has more coverage and less number of
patterns so we are choosing this channel.
Analyse_compression -> By using this command the tool will automatically
calculate the no of patterns and test coverage.
 Tessent Testkompress( Mentor) 30 to 80 X ideal compression ratio.
DFT MAX ( Synopsys) :- 25 X to 50 X ideal compression ratio.
Genus ( Cadence) 100 X to 150 X ideal compression ratio.

6. What is X-Masking? Why we need X-masking?

X-MASKING:
The tool records an X in the pattern file in every position made un measurable
as a result the actual occurrence of an X in the corresponding cell of a different scan
chain in the same compactor group. This is referred as X-MASKING (or)X
BLOCKING.
NEED FOR X-MASKING:
 One common problem with different compactor strategies is handling of Xs
(unknown values).
 Scan cells can capture X values from unmodeled blocks, memories, non-scan
cells, and hard macros.
Assume two scan chains are compacted into one channel. An X captured in Chain 1 will then
block the corresponding cell in Chain 2. If this X occurs in Chain 1 for all patterns, the value
in the corresponding cell in Chain 2 will never be measured. This is illustrated in Figure
where the row in the middle shows the values measured on the channel output.

Fig 1: X Masking with Compactor

7. If keep on increasing compression ratio, what is the impact?

Due to increase in compression ratio the number of patterns increases and the
test time increases. It is also important to balance the compression target with the
testing resources and the design needs. If larger the compression ratio, find the below
adverse effect:
 LOWER TEST COVERAGE: Higher compression ratios increases the
compression per test pattern but also increases the possibility of generating
test patterns that cannot be compressed and can lead to lower test coverage.
 DECREASE IN OVERALL COMPRESSION: Higher compression ratio
also decreases the number of faults that dynamic compaction can fit into the
pattern. This can increase the total number of test patterns and therefore
decrease overall compression.
 ROUTING CONGESTION: There is no limit to the number of internal scan
chains however routing congestion may limit the compression ratio. Most
practical configurations will not exceed the compression capacity.

8. Why need decoding logic?

The decoder is needed in order to decode the masking code generated by the tool in
order the to block the X values coming from a specific channel.

9. Importance of EDT_CLOCK,EDT_UPDATE and EDT_BYPASS

EDT CLOCK
 edt_clock must not share with another clock or RAM control pin for several reasons:
a a) If shared with a scan clock, the scan cells may be disturbed when the edt_clk is
b pulsed in the load_unload procedure during pattern generation. .

a b) If shared with RAM control signals, RAM sequential patterns and multiple load
patterns may not be applicable.

a c) If shared with a non-scan clock, test coverage may decline because the edt_clk is
constrained to its off-state during the capture cycle.
Because the clock used in the EDT logic is different than the scan clock, lockup
cells can be inserted automatically between the EDT logic and the scan chains as
needed.
EDT UPDATE
The pin edt_update is used to reset/update two sets of registers:
 ring generator registers -- in the decompressor logic
 mask hold registers -- in the compactor logic

During the load procedure edt_update is activated. This causes the following:
 ring generator registers become 0
 Mask_hold_register is loaded with value in the mask_shift_register
This is needed because:
 Ring generator needs a predictable state before generating random values, in
this case all 0 is the predictable state.
 Mask_hold_register is designed to do per pattern masking. Each pattern has a
specific masking sequence.

EDT BYPASS
 Must be forced during scan (forced on its bypass test procedure and force off
in the EDT test procedures). It is not constrained so sharing it has no impact
on test coverage.

10. Write waveform in terms of edt_clk, scan_clk, edt_update, scan_enable

Part-2
1. What is the reason for increase in pattern count for compressed mode?
 The reason we can’t increasing the pattern length.
 High routing congestion
 PCB width is increased.

2. How to decide EDT channel count?

 While deciding the channel count we need to ask with design team how many
channels want to be used for this design.
 We can decide through number of pins available in the tester.
3. Use of Pipeline Stages between Pads and Channel Inputs or Outputs?
 To avoid hold violations.

4. What is the difference between Basic Compactor and Xpress Compactor?

 Basic compactor consists of decoder and in Xpress compactor consists of a
basic decoder and Xor decoder.
 In basic decoder only one scan chain is masked in order to prevent the X
values coming from non scan cells or hard macros. In Xpress compactor the
Xor decoder is used inorder to mask multiple chains and prevent the X values
from coming in. In Xpress compactor Mask shift registers are pretended with
input channels.
 If the design complexity is more(more number of X propagations) we can
use Xpress compactor, if the design complexity is small (Less number of
X propagations )we can use Basic compactor.

BASIC COMPACTOR :

 A mask code (pretended with a decoder mode bit) is generated with each test
pattern to determine which scan chains are masked or observed.
 The basic compactor determines which chains to observe or mask using the
mask code as follows ,
 The decompressor loads the mask code into the mask shift
register.
 The mask code is parallel-loaded into the mask hold register,
where the decoder mode bit determines the observe mode:
either one scan chain or all scan chains.
 The mask code in the mask hold register is decoded and each
bit drives one input of a masking AND gate in the compactor.
Depending on the observe mode, the output of these AND gates
is either enabled or disabled
XPRESS COMPACTOR:

 A mask code (prepended with a decoder mode bit) is generated with each test pattern
to determine which scan chains are masked or observed. The Xpress compactor
determines which chains to observe or mask using the mask code as follows:
  Each test pattern is loaded into the decompressor through a mask shift register
on the input channel.
 The mask code is appended to each test pattern and remains in the mask shift
register once the test pattern is completely loaded into the decompressor.
 The mask code is then parallel-loaded into the mask hold register, where the
decoder mode bit determines whether the basic decoder or the XOR decoder is
used on the mask code.
 The basic decoder selects only one scan chain per compactor. The basic decoder is
selected when there is a very high rate of X values during scan testing or during chain
test to allow failing chains to be fully observed and easy to diagnose.
 The XOR decoder masks or observes multiple scan chains per compactor, depending
on the mask code. For example, if the mask code is all 1s, then all the scan chains are
observed.
 The decoder output is shifted through a multiplexer, and each bit drives one input on
the masking AND gates in the compactor to either disable or enable the output,
depending on the decoder mode and bit value.