MBIST ASSIGNMENT

Name- MAHITHA.B
Email – mahithaece413@gmail.com
Batch- Oct ‘18’

1.) What are the inputs to MBIST Architect and what are the outputs, explain with
flow chart?
Inputs - Memory model ,libraray file and netlist
Output- Dofile, BIST patterns, Simulation testbench

When test_h =1 ,BIST controller is ON,tools start generating the pattern ,sending to
memory and comparator .then the memory will do read and right operation, hence it will go
to comparator,hence both pattern should be match,it is pass or fail.

2.) What is fault and explain the different types of memory faults?
The basic types of memory faults include stuck-at faults (SAF), transition faults (TF),
coupling faults (CF, CFin, CFid, and CFst), and neighbourhood pattern sensitive faults
(NPST).
 Stuck-at faults
 Transition faults
 Coupling faults
 Neighourhood pattern sensitive faults

Stuck-at Faults
A memory fails if one of its control signals or memory cells remains stuck at a
particular value. Stuck-at faults model this behavior, where a signal or cell appears to
be tied to power (stuck-at-1) or ground (stuck-at-0).

To detect stuck-at faults, you must place the value opposite to that of the stuck-at
fault at the fault location. For example, to detect all stuck-at-1 faults, you must place
0s at all fault locations. To detect all stuck-at-0 faults, you must place 1s at all fault
locations.
The basic method to test for stuck-at faults is writing 0’s to all cells, reading all cells,
writing all 1’s to all cells, and then reading all cells again.

Transition Faults
A memory fails if one of its control signals or memory cells cannot make the
transition from either 0 to 1, or from 1 to 0. the inability to change from 0 to 1, and a
down transition fault, the inability to change from a 1 to a 0.
 The figure shows a cell that might behave normally when a test writes and then
reads a 1. It might even transition properly from 1 to 0. However, when
undergoing a 0->1 transition, the cell could remain at 0—exhibiting stuck-at-0
behavior from that point on. However, a stuck-at-0 test might not detect this
fault if the cell was originally at 1.

To detect all transition faults in the memory array, a test must write a 0, followed by a 1,
and then read (detects up transition). The test must then write a 1, followed by a 0, and
then read (detects down transition).
The basic method to test for transition faults is to write (1->0) and immediately reading 0’s
at each address. Repeat this process to write (0->1) and read 1’s at each address.
Coupling Faults
idempotent coupling faults, commonly referred to as CFid, occur when one cell’s transition
forces a particular value onto another cell. For example, a 0->1 transition in cell_n causes
the value of cell_m to change to 1 if the previous value was 0. However, if the previous
value was 1, the cell remains a 1.

Neighorhood faults
Write operations on a group of surroundings shells that affects the value of one and more
neighboring cells.
Type of categories:- Active ,Passive and statics.
3.) Explain how an mbistcontroller works with a diagram and giving all blocks of
memory bist controller?

The BIST controller generates three main blocks :

 A signal generation blocks contains circuitry to produce addresses, RAM data

inputs ,control values and the expected RAM data outputs.
  A comparator to compare the values read from the memory with the expected
value cycle by cycle basis.

 A finite state machine is used to control the overall sequence of events.

4.) Explain the difference between RAM and ROM?

5.) Why cannot functional patternsbe used for testing memories?

We can not use functional pattern for testing memories because it will create more
functional vector and increase run time.

6.) List the difference types of MBIST algorithms?

Supports at speed operations
 7.) How to arrive to the optimal number of controllers in design. What factors govern
the controller/memory allocation?
Embedded memories are an indispensable part of any deep submicron System on a Chip
(SoC). The requirement arises not only to validate the digital logic against manufacturing
defects but also do robust testing of large memory blocks post manufacturing. MBIST
(Memory built-in self-test) provides an effective solution for testing of such large memories.
Verification of functioning MBIST is an essential part in any SoC design cycle, as it enables
the designer to detect beforeh and any issues related to MBIST. The main focus of this paper
is to discuss the general issues faced, and best practices to be followed, during MBIST
Verification.

It is strongly recommended to use remarked best practices during verification of MBIST and
keep a preciseness verification setup during Gate Level Simulation(GLS) of MBIST.

8.) Explain the purpose of collar,does every memory need a collar?

Collar are used during bypass mode. In scan memory are the black boxes , because of x-
propagation coverage lose occurs .but it will not affect the functionality , hence collar used
to get the coverage. The memory connected to mux will need collar .
 9.) What is the impact of not having bypass logic in the coller?
If bypass logic is not present in coller ,then coverage lose will occurs.

10)Where is the bypass logic present and does it affect memory bist operation. In
Which mode bypass logic be effective ?

Bypass logic present at the input of the memory. In scan mode bypass logic be effective

11) Explain the prons and cons of compressor and comparator?

The on-chip decompressor consists of a ring generator, which is further connected to a

phase shifter. The ring generator is a distinct form of a maximum-length linear finite state
machine.It offers three main benefits as compared with conventional LFSRs. First, the
propagation delay introduced by its feedback logic is significantly reduced. In fact, in
the worst case, only one 2-input XOR gate is placed between any pair of memory elements.
Second, the maximum internal fan-out is confined to only two branches. Furthermore, the
total length of feedback lines can be drastically reduced. The compressed test data are
provided to the decompressor through input channels connected to taps of the ring
generator by means of additional XOR gates placed between the memory elements. For
instance, four external channels feed the ring generator, each having two injectors. Due to
this arrangement, test data can be quickly distributed to the entire ring generator.
Furthermore, a phase shifter, which is added to the outputs of the ring generator memory
elements, allows the ring generator to mutually displace the produced sequences in various
scan paths and to reduce linear dependencies in its output sequences.

12) When is compressor used in the design?

The collar contains a compressor when you are not using comparators in the
controller.TheMBISTArchitect tool supports the ROM1 (also known as the ROM test
algorithm) and ROM2 test algorithms as pre-defined ROM testing algorithms. For ROM
testing the memory results are evaluated with a compressor and not a comparator. The BIST
controller generated by this most basic generation dofile has no diagnostics and no BISA.
There is one fail_hsignal for all memories under test, and the signal is “sticky”, so it stays
high after a failure is detected.
 13) If compressor used , should it be implemented for every memory?

If the memories are all ROMs, they will be tested with the “ROM1 test” algorithm on all
ports and evaluated by a compressor in the memory collar. The memories will be tested
concurrently (in parallel). The controller and testbenchassume that the memories are driven
by a clock which is in-phase with the bist_clk of the controller, but it not should be
implemented for RAM memory.

14) Explain the difference between sequential contiguous and interleaved testing?
In sequential contiguous:-
The controller performs all algorithms for first memory, then perform all algorithms for
second memory .
 In interleaved testing
The controller performs the first steps of the first algorithms on the first memory , then
perform the first steps of the first algorithms on the second memory.

15) Explain the prons and cons of interleaved and parallel testing for memories?
When a BIST controller is testing more than one memory, by default the controller tests them
in parallel. This requires controller hardware and routing proportional to the number of
memories being tested, but the total test time is only as fast as the single slowest memory. If
three memories would normally take 1000 cycles each to be tested individually, the total
concurrent test time is just 1000 cycles. Disadvantage of parallel testing are the
extra hardware, or it may cause bus contention in a scenario where the memories under test
share a tri-state data bus.In a sequential-interleaved test, the controller performs the first step
of the first algorithm on the first memory, then performs the first step of the first algorithm on
the second memory, and so on. Then it moves to the second step of the first algorithm for all
memories.If three memories would normally take 1000 cycles each to be tested individually,
but in each case 800 cycles are devoted to the RetentionCB algorithm, then in sequential-
interleaved test the total test time is 1400 cycles.

16) Explain the purpose of pipelining?

To avoid the timing delay ,area and speed operations ,pipelining stages is added.
At high frequency test you might incur timing violations in BIST with the default settings.
The logic inside the default BIST controller’s finite state machine might not meet your
frequency requirements, or perhaps the interconnect flight time between the controller and
the memory collar may be too large. Register pipelining allows you to successfully perform
BIST at high frequency. This section describes the options offered by the command “Setup
Pipeline Registers”.

The BIST controller will use a special indexing method to produce the expected data, and
the indexing logic will be pipelinedto line up with the actual data arriving from the RAM.

17) Is pipelining added on all inputs line of memory, if not explain why?
Pipelining cannot add on all inputs lines of memory. The embedded synchronous SRAM may
also have a pipelined access mode to raise clock rate. In the pipelined architecture,
Read/Write latency can be more than one clock cycle. The corresponding data are ready
after several cycles, when the address and OE signals are asserted. Similarly, in burst access
mode we can use a single address and the Read/Write command to access a contiguous run
of data. For functional test and diagnosis, we run March tests using single Read/Write
modes (i.e., without pipelining or burst access), as it is effective and easy to implement.

18) Explain the purpose of using multiple algorithms in the bist controller?
There are memory test algorithms known to detect the majority of commonly occurring
faults in memories. Many of these algorithms lend themselves well to built-in self-test (BIST)
because the hardware to generate the patterns is relatively small and can serve multiple on-
chip memories. The algorithms in most common use are the March tests. March tests
generate patterns that “march” up and down the memory addresses, writing values to, and
reading values from known locations. These algorithms can retrieve the proper parameters
from the memory model, automatically determining the memory size and word length.The
following table summarizes the most common memory test algorithms along with the
number of operations (if known), and the fault coverage.
 19) How are the algorithms applied to the memory?

By default, the MBISTArchitect™ tool assigns the March2 algorithm to all write or read/write
memory ports. It is possible to add additional testing algorithms to further
enhancetestcoverage. For example, you might have a memory with special address testing
needs for whichthe Unique Address algorithm provides extra coverage. In this case, you may
not want or need to apply the rigorous testing of the March2 algorithm.