Dynamic Logic

• Dynamic gates uses a clocked pMOS pullup

• Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

Y
 The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent
fight.
 
precharge transistor Y Y

Y inputs inputs
A f f

foot
footed unfooted
 Logical Effort
Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = gd = gd =
pd = pd = pd =

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = gd = gd =
2 pd = 3 pd = 2 pd =
 C2MOS
 The clocked transistors are placed in series with the p-
channel and n-channel transistor of a standard inverter.
 The layout is simplified because the source/drain regions of
the two p-channel transistors can be merged.
 The output of C2MOS is available during the entire clock
cycle.
 The load capacitor is the storage node for the dynamic
charge.
Pre charge Evaluate Logic

The path between power and ground is broken by

two series transistor. No DC current path from power
to ground will exit at mutually exclusive times.
Minimum-size transistors can be used throughout.
The path to VDD is used to precharge the output node
during part of the clock cycle, and the path to ground
is used to selectively discharge the output node
during another part of the clock cycle.
The output is taken high during precharge time and is
logically valid during the discharge cycle.
Valid output available is less than 50% (for square-
wave clock).
 Precharge Evaluate Logic

 Two phase operation determined by the clock signal 

n – block p – block
Precharge :  = 0, out = 1 Precharge :  = 1, out = 0
Evaluate :  = 1, out = F(x) Evaluate :  = 0, out = F(x)
 Input change during precharge and are stable during evaluate.
 Monotonicity
• Dynamic gates require monotonically rising
inputs during evaluation
– 0 -> 0 

– 0 -> 1 A

– 1 -> 1
– But not 1 -> 0 violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

 Monotonicity Woes
• But dynamic gates produce monotonically
falling outputs during evaluation
• Illegal for one dynamic gate to drive another!
A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot
Charge Leakage & Cap. Coupling

• Output is floating after clk = ‘1’ if inputs are ‘0’

• Since the current is not 0 when transistors are
in cutoff, current can leak away from the
output when all inputs are ‘0’
• Changes in input signals couple to the output
and intermediate nodes, also resulting in
voltage drops
 Charge Leakage

• Since the node is capacitive, we model it as a capacitor ‘C’ that can be used to
hold a charge.
The logic’1’ is given at input Vi and control. The voltage across the capacitor
increases to
Vmax = (VDD - Vt )
 Charge Leakage

Initially, Vs was at Vmax indicating that a logic 1 was stored on the capacitor.

However, since leakage currents remove charge, Vmax cannot be held and Vs
will decrease in time.

Eventually, Vs will fall to a level where it will be incorrectly interpreted as a logic

0 value.

Because the stored charge will leak away over time, this circuit is termed a
dynamic storage circuit.
 Dynamic Charge Storage

• The pass transistor can discharge the inverter gate to 0V to give a good low
logic level. In this case, the inverter output is high and PMOS feedback
transistor is OFF.
The pass transistor can pull the inverter input voltage high enough to force the
inverter’s output to a low logic voltage. This low voltage turns on the PMOS
feedback transistor, thereby pulling the inverter input to the upper supply
voltage and holding it there.
 Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
weak keeper
– Must be weak enough
1 k not to fight evaluation
X
H Y
A 2
2
 Charge Sharing
• Dynamic gates suffer from charge sharing


Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx  VY  VDD
C x  CY
 Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well
secondary
 precharge
Y transistor
A x
B