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DLD List of Experiments

This document contains a list of 16 experiments for the Digital Logic Design course in the B.Sc. Electrical Engineering program at Riphah International University. The experiments cover topics such as basic logic gates, combinational logic circuits, half and full adders/subtractors, encoders, decoders, multiplexers, latches, flip flops, shift registers, and counters. They are designed to help students achieve various course learning outcomes related to digital logic concepts and skills.

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Ishfaq Ahmad
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913 views2 pages

DLD List of Experiments

This document contains a list of 16 experiments for the Digital Logic Design course in the B.Sc. Electrical Engineering program at Riphah International University. The experiments cover topics such as basic logic gates, combinational logic circuits, half and full adders/subtractors, encoders, decoders, multiplexers, latches, flip flops, shift registers, and counters. They are designed to help students achieve various course learning outcomes related to digital logic concepts and skills.

Uploaded by

Ishfaq Ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Department of Electrical Engineering

Riphah College of Science and Technology


Riphah International University, Lahore Campus

Program: [Link]. Electrical Engineering Semester: III


Subject: EE-202 Digital Logic Design

List of Experiments
Level
S. No Experiments of CLO
Inquiry
0 4,6
Experiment 1 Introduction to digital logic trainer
1 4,6
Experiment 2 Verification of truth tables of basic logic gates
1 4,6
Experiment 3 Simulation and implementation of functions using basic logic gates
Design and implement a logic circuit with four input variables that 1 4,6
Experiment 4
will only produce a 1 output when exactly 3 input variables are 1
Design a combinational circuit with 4 inputs A, B, C and D and one 4,6
output E. E is equal to 1 when A=1 if B=0 or when B=1 provided 1
Experiment 5
that either C or D is also equal to 1. Otherwise, the output is equal to
0
To implement basic logic gates using universal gates (NAND & 1 4,6
Experiment 6
NOR)
To design and implement half adder and full adder, half Subtractor 1 4,6
Experiment 7(a)
and full subtractor.
Experiment 7(b) To design and implement half Subtractor and full subtractor. 1 4,6
Experiment 8(a) Investigate the operation of Encoders 1 4,6
1 4,6
Experiment 8(b) Investigate the operation of Decoders
Experiment 9(a) Investigate the operation of multiplexers 1 4,6
Experiment 9(b) Investigate the operation of demultiplexers 1 4,6

Experiment 10 Implementation of RS latches 1 4,6

Experiment 11 Implementation of JK flip flop 1 4,6


1 4,6
Experiment 12 Implementation of JK flip flop circuits
1 4,6
Experiment 13 To study shift-register operation
1 4,6
Experiment 14 To implement and study multivibrators using 555 timer IC
Department of Electrical Engineering
Riphah College of Science and Technology
Riphah International University, Lahore Campus

1 4,6
Experiment 15 Implement synchronous up/down counter using JK flip flop
2 4,6
Experiment 16 Open Ended Lab

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