module final_occ ( se,sclk,reset,fclk,si,out);

input se,sclk,fclk,si;
output out;
wire p,q,r,s,t,u,v;

upperblock a1(se,reset,sclk,fclk,s);
icg a2(t,s, gated_clk,out);
shift_reg a3(s,sclk,si,se,reset,t);

endmodule

module upperblock (se,reset,sclk,fclk,d);

input se,sclk,fclk,reset;
wire a,b,c,gated_clk;
output d;

not( a,se);
dff_ p(sclk,a,reset,b);
icg r(b,fclk,gated_clk,c);

assign d = (se) ? sclk : c;

endmodule

module icg(en,clk, gated_clk,en_out);

input en,clk;
output gated_clk,en_out;
reg en_out;
always @ (en or clk) begin
if (!clk)
en_out = en; // build latch
end
assign gated_clk = en_out && clk;
endmodule

module dff_(clk,in,reset,q);
input clk,in,reset ;
output reg q;
always@(posedge clk)
begin
if (reset)
begin
q<=0;
end
else
begin
q<= in;
end
end
endmodule
module shift_reg(fclk,sclk,si,se,reset,e);
input fclk,sclk,reset,se,si;
output e;
wire clk,in,q,e1;
wire[n-1:0] w;
parameter n = 3;

and o(in,si,se);
genvar i;
dff_ a (clk,in,reset,w[0]);
generate

for (i=1;i<n;i=i+1)
begin
dff_ b(clk,w[i-1],reset,w[i]);
end
endgenerate
dff_ c(clk,w[n-1],reset,q);

assign clk = (se) ? sclk : d;

or (e1,w[0],w[1],w[2],q);
or(f,e,se);
initial
begin
$monitor($time,"fclk=%b,sclk=%b,reset=%b,se=%b,si=%b,w=%b,q=
%b",fclk,sclk,reset,se,si,w,q);

end

endmodule