Chapter1:Compression :

1. what is compression?

2. why we are using compression in our dft flow?

3. what is significant of compression?
i. it reduces the ATE memory and channel requirement
ii. reduces test data volume results in shorter test application time
iii.it give higher throughput than traditional atpg.
4.Tessent testkompress which type of test pattern it will support ?
Tessent testkompress supports most of types except these following:
i. random pattern generation.
ii. Tessent FastScan™®MacroTest.. you can only apply macro test patterns
to a design with testkocmpress by accessing scan chains directly
,bypassing the edt logic.
5. Tessent testkompress which type of scan architecture it will support ?
Tessent testkompress logic supports MUX_DFF, LSSD, mixture of the scan
architecture.

Edt logic Support scan architecture

MUX_DFF MUX_DFF,LSSD and mixed

LSSD LSSD

6.what are the input of tessent testkompress ?

i. scan inserted gate level Verilog netlist.
ii. synthesis tool.
iii. Tessent cell library of models used for your design scan circuitry.
iv. Timing Simulator such as model sim.
7. What is the compression ratio or chain to channel ratio?
Compression ratio or chain to channel ratio= scan chains/scan channels
You can determine optimal chain: channel ratio for an application by varying
no.of scan chain and scan channel and generating test patterns by following
elements.
Test coverage: determine if the test effectiveness is adequate for the
application.
Data volume: determine how much test pattern data is generated after
compression whether it is with in the hardware limitations.
Atpg baseline (optional): compare test data statistics for atpg baseline and
with the compressed test patterns statistics .
8. if compression ratio is high what is the impact ?
Lower test coverage: Higher compression ratios increase the compression per
test pattern but also increase the possibility of generating test patterns that
cannot be compressed and can lead to lower test coverage
Decrease in overall compression: Higher compression ratios also decrease the
number of faults that dynamic compaction can fit into a test pattern. This can
increase the total number of test patterns and, therefore, decrease overall
compression.
Routing congestion: There is no limit to the number of internal scan chains,
However, routing constraints may limit the compression ratio. Most practical
Configurations will not exceed the compression capacity.

9. explain structure and function of compression ?

Fig: tester connected to a design with edt.
No additional logic(test points and x-bounding logic) inserted into core of the
design .therefore edt logic affects only scan channel inputs and outputs, thus
has no effect on functional paths.
Decompressor:
Feeds a large number of scan chains in your core design from a small
number of scan channels, and decompresses EDT scan patterns as they are
shifted in.
it is located between the external scan channel inputs and internal scan chain
inputs.
i. lfsm
ii. phase shifter.
Compactor:
Compacts the test responses from the scan chains in your core design
Into a small number of scan output channels as they are shifted out.
it is located between the internal scan chain outputs and external scan channel
outputs.
It primarily consists of a spatial compactor (s)logic and gating logic.
Bypass:
Bypasses the EDT logic by using multiplexers (and lockup cells if necessary) to
concatenate the internal scan chains into fewer, longer chains. Enables you to
access the internal scan chains directly through the channel pins.
Generated by default.
You can use any scan insertion tool, but you must adhere to the following
rules when defining the scan chains:
• Scan chains and bypass chains must use the same I/O pins.

• If the control pin used to select bypass or compression mode is shared with
the edt_bypass pin, the bypass chains must be active when the edt_bypass pin
is at 1, and the scan chains must be active when the edt_bypass pin is at 0.

• Test procedure file for the EDT logic must set up the mux select, so the
shortened internal scan chains can be traced.
Inserting bypass chains with a scan insertion tool ensures that lockup cells and
multiplexers used for bypass mode operation are fully integrated into the
design netlist to allow more effective design routing.

Test patterns:
A set of test patterns are stored on the ATE and each test patterns applies data
to the input of decompressor and hold the responses and observed on the
output of compactor.
Functional input and output pins are directly controlled(forced)and
observed(measured) by the tester.
10.what is the use of bypass logic?
I. debug the compressed test patterns.
ii.more effective design routing.
11. What is the internal flow and external flow of the design?

Fig1:Edt logic is outside the core(external flow).

Fig2:edt logic is located with in core(internal flow).

By default the tool is automatically inserts lockup cells as need in EDT logic.
They are placed with in EDT logic, between EDT logic and design core and in
bypass circuitry that concatenates to scan chains.
12. edt wave forms
 If shared with a scan clock, the scan cells may be disturbed when the
edt_clk is pulsed in the load_unload procedure during pattern
generation.
 If shared with RAM control signals, RAM sequential patterns and
multiple load patterns may not be applicable.
 If shared with a non-scan clock, test coverage may decline because the
edt_clk is constrained to its off-state during the capture cycle.

Because the clock used in the EDT logic is different than the scan clock, lockup
cells can be inserted automatically between the EDT logic and the scan chains
as needed. The tool inserts lockup cells as part of the EDT logic and never
modifies the design core.
You set the EDT clock to pulse before scan chain shift clock with the
pulse_edt_before_shift_clocks switch of the set_edt_option command.
By default edt and scan chain shift clocks are pulsed simultaneously.
• Makes creating EDT logic for a design in the RTL stage easier because scan
chain clocking information is not required. For more information on creating
EDT logic at the RTL stage, see “Integrating Compression at the RTL Stage” on
page 305.
• Removes the need for lockup cells between scan chains and the EDT logic
because correct timing is ensured by the clock sequence. Only a single lockup
cell between pairs of bypass scan chains is necessary. For more information,
see “Understanding LockupCells” on page 269.
• Simplifies clock routing because the lockup cells used for bypass scan chains
are driven by the EDT clock instead of a system clock. This eliminates the need
to route systemclocks to the EDT logic.
To use this functionality, the shift speed must be able to support two
independent clock pulses in one shift cycle, which may increase test time.

Latch-based EDT logic uses two clocks (a master and a slave

clock) to drive the logic. For reasons similar to those listed above for DFF-based
logic, you must not share the master EDT clock with the system master clock.
You can, however, share the slave EDT clock with the system slave clock.
Note:
During the capture cycle, the system slave clock, which is shared with the slave
EDT clock, is pulsed. This does not affect the EDT logic because the values in
the master latches do not change.
Similarly, in the load_unload cycle, although the slave EDT clock is pulsed, the
value at the outputs of the system slave latches is unchanged because the slave
latches capture old values.
In a skew load procedure, when a master clock is only pulsed at the end of the
shift cycle (so different values can be loaded in the master and slave latches),
the EDT logic is unaffected because the master EDT clock is not shared.
13. what are the uncompressed and compressed test patterns?

 Compressed ATPG test patterns can be written out in ASCII and binary
formats, and can read back into the tool.
When you create patterns with compression, the captured data is
stored with respect to the internal scan chains and the load data is stored with
respect to the external scan channels. The load data in the pattern file is in
compressed format—the same form it is fed to the decompressor.
 Uncompressed patterns, you can use this formats primarily debugging
simulation mismatch archiving.
14.compression which type of faults it support?
i.stuck_at..
ii.transition.
iii.iddq.
iv.path delay.
15. What is the post synthesis EDT ip creation and EDT pattern generation
flow?

EDT IP generation:
By default the tool writes out the RTL files in the same format as original
netlist. You can use either pre_synthesis flow or post_synthesis flow to
generate EDT IP and create TCD file

EDT pattern generation:

After EDT IP generated and embedded in the design.you use TCD file (tessent
core description) to perform connectivity extraction and pattern generation.
16. What is the pre synthesis EDT ip creation and EDT pattern generation
flow?
17.explain about TCD(tessent core description)?
The TCD file is generated with the write_edt_files command along with the
other EDT logic files during EDT IP generation. The TCD file contains the
description of the generated EDT IP.
The EDT IP TCD file describes the configuration of the EDT IP. You should never
modify the TCD file.