NXP Interview Questions

By deepa.b
VLSI design flow
Design specifications
RTL coding
Verification
Synthesis
DFT
PD
STA
Placing and routing
Chip manufacturing
DFT FLOW
SCAN

ATPG PD / STA

SIMULATION
SCAN
SCAN : scan is used to get controllability and
obserability at each and ever node in a design.
mux scan cell

D Q
S.I

S.E
CLK
Functional and scan patters
FUNCTIONAL PATTERNS
 It is used to test functioning
of the design .
 We need more functional
patters to test due to that
time consume will be more.
 Functional way of testing.
SCAN PATTERNS
It is used to test structural
way of the design.
We need less patterns to test
due to that time consume will
be very less.
DFT is structural way of
testing.
Design Rule Check Issue
Tracing violation
During ATPG pattern generation. I got chain trace
issue , I observed that one of scan ff clock getting “x” .
Then I traced back, it was coming from one of the Mux
where top level clock was bypassed.
Actually their scan ff were kept as non scan ff in
previous version of net list , but in new version it was
converted into scan ff. as I was using old dofile ,
constrained the select line of the mux which was
bypassing from top level clock was not mentioned . So I
mentioned in dofile , mux select pin then it got passed
DRC Violation
. Non scan flop
D Q
S.I
mux S.E
x 0
Clock 1

select
Lockup Latch
Lockup Latch are used to get half cycle delay in circuit
To over come data jumping issues ( hold violations).
Lockup latch is used place between two scan ff when
we use asynchronous clocks or synchronous clocks
with skew .
Lockup latch between two scan ff have to place in such
a way that it clock edge trigger should be opposite by
comparing to first scan ff (sff1 + , latch - , sff2+)
Without Lockup Latch
. SFF1 comb SFF2
D Q2
S.I Q1

S.E

CLK skew(0.2)
Waveform without LUL
S.I
Clk+ve

Q1

Clk+ve 2 12
(skew)
Q2
With Lockup Latch
. SFF1 comb SFF2
D latch Q2

S.I Q1

S.E

CLK skew
Waveform with LUL
S.I

Clk+ve

Q1

Clk+ve (skew)
latch it use clk–ve without skew

Q2
COMPRESSION
• Compression used to reduce
Test time
Test data volume
Due to compression , area will increase this is one of the
disadvantage.
No timing and timing
After scan insertion in gate level net list .
 ATPG will generated scan patterns for both no timing
and timing .
To generate ATPG patterns for no timing , net list will
get from scan team(pre layout).
To generate ATPG patterns for timing, net list will get
from PD and STA team(post layout).
Simulation
Simulation

Serial Parallel

Timing No timing Timing No timing

No Timing
No timing issue occur due to any structural faults in a
design.
No timing simulation inputs
TB (verilog test bench)
Scan insertion net list ( provided by scan team)
Verilog Lib
ATPG patterns which is generated by using net list
provided by scan team (pre layout net list).
Timing
Timing issue occur due to not meeting timing closes
due to that we may occur hold and setup violations.
Timing simulation inputs
TB (verilog test bench )
SCAN insertion net list(provided by PD/STA team)
Verilog Lib
ATPG Patterns which was generated by using net list
provided by PD/STA team (post team).
SDF (STA team will provide SDF file).
Timing issue
ATPG patterns were failing, one of the scan chain out
port showing mismatch. This patterns was passing in
no timing .
I observed that two scan flops are getting same data ,
due to that data was jumping. To avoid data jumping
we added latch b/w two scan flops.
So ,I informed to scan team . Then their inserted latch
between the scan flop. Then timing simulation was
passed.
This is hold violation (sdf_min).
Waveform of timing issue
S.I
CLK

Q1

CLK

Q2
Timing issue solution
S.I

CLK1

Q1

CLK2
latch latch use clk1-ve

Q2
. Where in above figure we have seen that their was
skew between a clock.
Normally data have to be capture in a SFF2 in
second cycle , but observing in above figure it was
capturing in first cycle only , due to that data will
jump.
To over come this kind of problem we need to add
lockup latch in between two scan cells.
Coverage
 Will Read :
Non scan cells
Black boxes
Feedback loop
Pin constrains
Sequence dept (fast seq , full seq)
By increasing abort limit (ND)
By Analysis AU faults (ex: tied cells)
UC/UO ( Test point )
Transition fault
Slow to rise node : Transition from 0 to 1
1

0
Slow to fall node : Transition from 1 to 0

0
Example
slow to rise fault (2,3)

1. Good

2. Fail

3. Fail timing window

Example
Slow to fall fault (1, 3)

1. Fail

2.Good

3.Fail timing window

Transition faults can be detected in functional
.frequency.
In at speed me have shift mode and capture mode
Where as number scan ff “n”, then in shift input we
need “n” clock pulse , in capture we need min clock
pulse is one and in shift output we need “n” clock pulse.
 If there is non scan cells between two scan cells we
need more capture pulse , to observe fault in to capture
cell.
To generate capture pulse by using OCC .
By changing cap_cycle_conf pin value in OCC. we can
generate required number of capture pulse.
Pre layout and Post layout
The main difference between pre layout and post
layout is that pre layout simulations take place before
completing the timing and power analysis.
 While post-layout simulations use net list from PD
and STA analysis (after closing timing issues and power
budget analysis .
Pre-layout simulations allow us to create power and
timing guidelines while post-layout simulations allow
us to improve our design and verify that our chip meet
all your needs.
FORMAL VERIFICATION
Formal verification is nothing but which verify only
boolean equivalent in net list, which ignore timing
information.
Through which we cannot guarantee that the internal
design meet the required specification.
Logical equivalent check (LEC) tool used to check
only boolean equivalent of net list generated by RTL.
FUNCATIONAL VERIFICATION
Functional Verification is defined as the process of
verifying that an RTL (Synthesizable Verilog, VHDL,
SystemVerilog) design meets its specification from a
functional perspective.